JPH0360096A - Manufacture of multilayer printed circuit board - Google Patents
Manufacture of multilayer printed circuit boardInfo
- Publication number
- JPH0360096A JPH0360096A JP1194928A JP19492889A JPH0360096A JP H0360096 A JPH0360096 A JP H0360096A JP 1194928 A JP1194928 A JP 1194928A JP 19492889 A JP19492889 A JP 19492889A JP H0360096 A JPH0360096 A JP H0360096A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- double
- bumps
- solder
- polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 29
- 229920000642 polymer Polymers 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000012790 adhesive layer Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 239000011889 copper foil Substances 0.000 abstract description 10
- 239000011229 interlayer Substances 0.000 abstract description 4
- 239000011230 binding agent Substances 0.000 abstract description 3
- 229910001220 stainless steel Inorganic materials 0.000 abstract description 3
- 239000010935 stainless steel Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 230000004927 fusion Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
多層プリント配線基板の眉間導体接続及び層間接着に係
る製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a manufacturing method relating to glabellar conductor connection and interlayer adhesion of a multilayer printed wiring board.
（従来の技術）
第２ｍ （ａ）、（ｂ）は、従来技術による４層プリン
ト配線基板製造方法の一実施例を示す断面図で、同図に
おいて１，５は両面プリント配線基板、２．３は両面プ
リント配線基板１上にパターン化された銅箔層、４は両
面プリント配線基板１上の両面パターンを導通接続する
ためのスルーホール、６，７は両面プリント配線基板５
上のパターン化された銅箔層、８は両面プリント配線基
板５上の両面パターンを導通するためのスルーホール、
９は半田バンブ、１ｏは半田バンブ９の融点より低い硬
化濃度を持つポリマー接着用絶縁層、１１は半田バンブ
融合、１２は絶縁接着層を示す。(Prior Art) 2m (a) and (b) are cross-sectional views showing an example of a method for manufacturing a four-layer printed wiring board according to the prior art, in which 1 and 5 are double-sided printed wiring boards, 2. 3 is a copper foil layer patterned on the double-sided printed wiring board 1; 4 is a through hole for electrically connecting the double-sided patterns on the double-sided printed wiring board 1; 6 and 7 are double-sided printed wiring boards 5.
The upper patterned copper foil layer 8 is a through hole for conducting the double-sided pattern on the double-sided printed wiring board 5.
9 is a solder bump, 1o is an insulating layer for polymer adhesion having a hardening concentration lower than the melting point of the solder bump 9, 11 is a solder bump fusion, and 12 is an insulating adhesive layer.
第２図（ａ）において、両面プリント配線基板１．５は
どちらも必要なスルーホール４．８や両面パターン２．
３．６．７を形成した通常の両面プリント基板である。In FIG. 2(a), the double-sided printed wiring board 1.5 includes necessary through holes 4.8 and double-sided patterns 2.5.
3.6.7 is a normal double-sided printed circuit board.
この両面プリント配線基板１．５の対向する面の銅箔３
，６上の導通接続箇所に半田バンブ９をクリーム半田の
印刷、半田リフローにより形成する。半田は一般的な共
晶半田を用いる。次に同じ対向する面の半田バンブ以外
の箇所全面にスクリーン印刷でポリマー接着用絶縁層１
０を形成し、バインダーを飛ばした前硬化状態としてお
く。こうして得られた基板を第２図（ａ）に示すように
バンブ同士向い合わせて、上下を平らなステンレス板（
図示せず）で挟み加圧しながら加熱する。条件は第一段
階として半田融点を越えた温度２２０℃２分程度のベー
パフェーズソルダリフローを行う。この時に対向した半
田バンブ９は加圧のため押しつぶされながら融合し、半
田バンブ融合１１が得られる。また、ポリマー接着用絶
縁層１０は温度上昇による粘度の低下と加圧により互い
に密着する。第二段階は引き続き温度を１５０℃に保ち
約１時間のポリマーの硬化を行わせ、絶縁接着層１２を
得て上下基板の接着を完了する。Copper foil 3 on the opposite side of this double-sided printed wiring board 1.5
, 6 are formed with solder bumps 9 by printing cream solder and solder reflow. General eutectic solder is used for the solder. Next, screen print an insulating layer 1 for polymer adhesion on the entire surface other than the solder bumps on the same opposing surface.
0 and leave it in a pre-cured state with the binder blown off. The thus obtained substrate was placed with the bumps facing each other as shown in Fig. 2(a), and the upper and lower sides were flat stainless steel plates (
(not shown) and heat while applying pressure. As a first step, vapor phase solder reflow is performed at a temperature of 220° C. for about 2 minutes, which exceeds the solder melting point. At this time, the opposing solder bumps 9 are crushed and fused due to the pressure applied, and a fused solder bump 11 is obtained. Further, the polymer adhesion insulating layers 10 are brought into close contact with each other due to a decrease in viscosity due to temperature rise and pressurization. In the second step, the temperature is maintained at 150° C. and the polymer is cured for about 1 hour to obtain an insulating adhesive layer 12 and complete the bonding of the upper and lower substrates.
（発明が解決しようとする課題）
以上の製造方法に於て、ポリマー接着用絶縁層１０のパ
ターン化及び製造上での目合わせが繁雑である。本発明
はこれを必要としないで、より簡単な方法で同様のＮ間
導通接続と層間接着を得る方法を提供するものである。(Problems to be Solved by the Invention) In the above manufacturing method, patterning of the polymer adhesive insulating layer 10 and alignment during manufacturing are complicated. The present invention does not require this and provides a simpler way to obtain similar N-to-N conductive connections and interlayer adhesion.
（発明の構成及び作用）
第１図に本発明による４層プリント配線基板の一実施例
を断面図で示す。図中の１は両面プリント配線基板、２
，３は両面プリント配線基板１上のパターン化された銅
箔層、４は両面プリント配線基板１上の両面パターンを
導通接続するためのスルーホール、５は両面プリント配
線基板、６゜７は両面プリント配線基板５上のパターン
化された銅箔層、８は両面プリント配線基板５上の両面
パターンを導通接続するためのスルーホール、９は半田
バンブ、１０は半田バンブ９の融点より低い硬化温度を
持つポリマー接着用絶縁層、１１は半田バンブ融合、１
２は絶縁接着層を示す。第１図（ａ）において、両面プ
リント配線基板１．５はどちらも必要なスルーホール４
，８や両面パターン２．３．６．７を形成した通常の両
面プリント基板である。両面パターン２，３，６．７を
形成している銅箔層の厚さは通常用いられている１８〜
３５μｍで十分である。この両面プリント配線基板１，
５の対向する面の銅箔３，６上の導通接続箇所に半田バ
ンブ９を、例えば、クリーム半田の印刷、半田リフロー
により形成する。半田は一般的な共晶半田を用いる。次
に同じ対向する面の半田バンブ上を含め全面にスクリー
ン印刷でポリマー絶縁層１０を形成し、バインダーを飛
ばした前硬化状態としておく。こうして得られた基板を
第２図（ａ）に示すようにバンブ同士向い合わせて、上
下を平らなステンレス板（図示せず）などで挟み、加圧
しながら加熱する。加熱条件は第一段階として半田融点
を越えた温度とし、この時点で半田バンブ９は、その上
にあったポリマー絶縁層１０を排し、加圧のため押しつ
ぶされながら融合しバンブ接続１１が得られる。同時に
ポリマー絶縁層１ｏは温度上昇による粘度の低下と加圧
により互いに密着した状態になり、続く第二段階ではポ
リマー硬化温度に設定することでポリマーの硬化を行わ
せ、絶縁接着Ｎ１２を得て、上下基板の接着を完了する
。なおポリマー絶縁層１０は加圧時に張り合わせ面から
はみ出して来るが、不要部分は切断、研磨などで取り除
く。(Structure and operation of the invention) FIG. 1 shows a cross-sectional view of an embodiment of a four-layer printed wiring board according to the invention. 1 in the diagram is a double-sided printed wiring board, 2
, 3 is a patterned copper foil layer on the double-sided printed wiring board 1, 4 is a through hole for electrically connecting the double-sided patterns on the double-sided printed wiring board 1, 5 is a double-sided printed wiring board, 6°7 is a double-sided A patterned copper foil layer on the printed wiring board 5, 8 a through hole for electrically connecting the double-sided patterns on the double-sided printed wiring board 5, 9 a solder bump, and 10 a curing temperature lower than the melting point of the solder bump 9. insulating layer for polymer adhesion, 11 is solder bump fusion, 1
2 indicates an insulating adhesive layer. In Figure 1(a), both sides of the double-sided printed wiring board 1.5 have the necessary through holes 4.
, 8 and double-sided patterns 2, 3, 6, 7 are formed. The thickness of the copper foil layer forming the double-sided patterns 2, 3, 6.7 is usually 18~
35 μm is sufficient. This double-sided printed wiring board 1,
Solder bumps 9 are formed at conductive connection points on the copper foils 3 and 6 on opposing surfaces of the copper foils 5 by, for example, cream solder printing or solder reflow. General eutectic solder is used for the solder. Next, a polymer insulating layer 10 is formed on the entire surface including the solder bumps on the same opposing surface by screen printing, and the resin is left in a pre-cured state with the binder removed. The thus obtained substrate is placed with the bumps facing each other as shown in FIG. 2(a), and the top and bottom are sandwiched between flat stainless steel plates (not shown), and heated while being pressurized. The heating conditions are such that the temperature exceeds the solder melting point in the first step, and at this point the solder bump 9 removes the polymer insulating layer 10 that was on it, and is crushed and fused due to the pressure applied to form the bump connection 11. It will be done. At the same time, the polymer insulation layers 1o become in close contact with each other due to the decrease in viscosity due to temperature rise and pressurization, and in the subsequent second step, the polymer is cured by setting the polymer curing temperature to obtain insulation adhesion N12, Complete adhesion of the upper and lower boards. Note that the polymer insulating layer 10 protrudes from the bonded surfaces when pressure is applied, but unnecessary portions are removed by cutting, polishing, etc.
（発明の効果）
本発明では製造工程上のマスクパターン、目合わせ作業
を減らすことが出来るため、工程の簡略化が図れる。(Effects of the Invention) In the present invention, the mask pattern and alignment work in the manufacturing process can be reduced, so the process can be simplified.
第１図は本発明の一実施例として４層多層基板の製造工
程を示す断面図、第２図は従来の技術による一実施例と
して４層多層基板の製造工程を示す断面図である。
１．５・・・両面プリント配線基板、２，３，６゜７・
・・銅箔層、４，８・・・スルーホール、９・・・半田
バンブ、１０・・・ポリマー接着用絶縁層、１１・・・
半田バンブ融合、１２・・・絶縁接着層。FIG. 1 is a cross-sectional view showing the manufacturing process of a four-layer multilayer board as an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of a four-layer multilayer board as an example of the conventional technology. 1.5...Double-sided printed wiring board, 2,3,6゜7・
...Copper foil layer, 4,8...Through hole, 9...Solder bump, 10...Insulating layer for polymer adhesion, 11...
Solder bump fusion, 12... Insulating adhesive layer.
Claims (1)
板において、対向する双方の該銅張りプリント配線基板
の銅パターン上の任意の対向する箇所に半田層を形成し
、さらにその上の半田層を含めた全面もしくは一部分に
半田融点以下の硬化温度を持つポリマー接着材層を形成
し、該対向面を重ね合わせ、第一段階で加圧しながら半
田融点以上の加熱により、該対向箇所の半田層間を融合
させ、第二段階でポリマー硬化温度条件を与えることに
より対向面間の導通及び接着を得ることを特徴とする多
層プリント配線基板の製造方法。In a multilayer board in which a plurality of copper-clad printed wiring boards are stacked, a solder layer is formed at any opposing location on the copper pattern of both opposing copper-clad printed wiring boards, and a solder layer is included above the solder layer. A polymer adhesive layer with a curing temperature below the solder melting point is formed on the entire surface or a part thereof, the opposing surfaces are overlapped, and in the first step, the solder layers at the opposing locations are fused by heating above the solder melting point while applying pressure. A method for manufacturing a multilayer printed wiring board, characterized in that conduction and adhesion between opposing surfaces are obtained by applying polymer curing temperature conditions in the second step.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1194928A JPH0360096A (en) | 1989-07-27 | 1989-07-27 | Manufacture of multilayer printed circuit board |
| US07/456,946 US5031308A (en) | 1988-12-29 | 1989-12-26 | Method of manufacturing multilayered printed-wiring-board |
| ES93118917T ES2085098T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF A MULTILAYER PRINTED CIRCUIT. |
| EP93118943A EP0607534B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
| DE68926055T DE68926055T2 (en) | 1988-12-29 | 1989-12-28 | Manufacturing process of a multilayer printed circuit board |
| ES93118943T ES2104023T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF MULTILAYER PRINTED WIRING PLATE. |
| EP93118917A EP0607532B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
| ES89124088T ES2069570T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF A PRINTED CONNECTION PLATE WITH MULTIPLE LAYERS. |
| DE68921732T DE68921732T2 (en) | 1988-12-29 | 1989-12-28 | Process for the production of printed multilayer printed circuit boards. |
| CA002006776A CA2006776C (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
| EP89124088A EP0379736B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
| DE68928150T DE68928150T2 (en) | 1988-12-29 | 1989-12-28 | Manufacturing process of a multilayer printed circuit board |
| KR1019890020640A KR940009175B1 (en) | 1988-12-29 | 1989-12-29 | Multi-printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1194928A JPH0360096A (en) | 1989-07-27 | 1989-07-27 | Manufacture of multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360096A true JPH0360096A (en) | 1991-03-15 |
Family
ID=16332675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1194928A Pending JPH0360096A (en) | 1988-12-29 | 1989-07-27 | Manufacture of multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360096A (en) |
-
1989
- 1989-07-27 JP JP1194928A patent/JPH0360096A/en active Pending
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