JPH0360051A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0360051A JPH0360051A JP1194697A JP19469789A JPH0360051A JP H0360051 A JPH0360051 A JP H0360051A JP 1194697 A JP1194697 A JP 1194697A JP 19469789 A JP19469789 A JP 19469789A JP H0360051 A JPH0360051 A JP H0360051A
- Authority
- JP
- Japan
- Prior art keywords
- tin foil
- tin
- lead
- gold
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 82
- 239000010931 gold Substances 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims abstract description 39
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052737 gold Inorganic materials 0.000 claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 230000005496 eutectics Effects 0.000 abstract description 22
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 241000282798 Rhinocerotidae Species 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
〔概要〕
リードが金一錫共晶体によって接続された半導体装置の
製造方法に関し、
リードとその接続相手との接続における製造歩留まりの
改善を目的とし、
一方の端部が半導体チップに接続されるリードを、金属
板の少なくとも一方の面に錫箔の接合された複合板から
形成し、該金属板より形成された主導体部に該錫箔より
形成され錫箔層が接合する該リードの該錫箔層に、該リ
ードの接続相手の金パッドが接続されてなることを特徴
とする半導体装置の構成、
前記複合板からリードフレームを形成し該リードフレー
ムに半導体チップを搭載するまたは、前記複合板に絶縁
フィルムを接着したものよりテープキャリアを形成しリ
ードに半導体チップを搭載することを特徴とする半導体
装置製造方法の構成である。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device in which leads are connected by a gold-tin eutectic, the present invention aims to improve manufacturing yield in connection between a lead and its connection partner, A lead connected to a semiconductor chip is formed from a composite plate having a tin foil bonded to at least one surface of a metal plate, and a tin foil layer formed of the tin foil is bonded to a main conductor portion formed from the metal plate. A configuration of a semiconductor device characterized in that a gold pad to which the lead is connected is connected to the tin foil layer of the lead, a lead frame is formed from the composite plate and a semiconductor chip is mounted on the lead frame, or This is a configuration of a semiconductor device manufacturing method characterized in that a tape carrier is formed by bonding an insulating film to the composite plate, and a semiconductor chip is mounted on the leads.
本発明は半導体装置の製造方法、特に、金一錫共晶体で
リードが接続される半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which leads are connected using a gold-tin eutectic.
半導体装置の量産プロセスにおいて、一端が半導体チッ
プに接続し他端がパッケージの基板等に接続される多数
のリードは、一般に、リードフレームまたはテープキャ
リアとして形成される。In the mass production process of semiconductor devices, a large number of leads, one end of which is connected to a semiconductor chip and the other end of which is connected to a package substrate or the like, are generally formed as a lead frame or a tape carrier.
Ｔ Ａ Ｂ （Ｔａｐｅ Ａｕｔｍａｔｅｄ Ｂｏｎｄ
ｉｎｇ）技術等を利用したリードの接続が金（Ａｕ）一
錫（Ｓｎ）共晶体によるとき、接続相手が金であるリー
ドの接続面には錫を被着させる必要がある。従来のかか
るリードは、金属板より形成したのち表面に錫めっきを
被着していた。T A B (Tape Automated Bond
When the leads are connected using a gold (Au)-tin (Sn) eutectic using a technique such as ing), it is necessary to deposit tin on the connection surface of the lead whose connection partner is gold. Conventionally, such leads have been formed from a metal plate and then coated with tin plating on the surface.
第４図はテープキャリアを使用した従来の半導体装置の
製造方法の説明図である。FIG. 4 is an explanatory diagram of a conventional method of manufacturing a semiconductor device using a tape carrier.
第４図（イ）において、テープキャリア（フィルムキャ
リア）の製造には、耐熱性絶縁フィルム（ポリイミドテ
ープ）２の上面に、金属板（銅板）３を接着した板材１
を使用する。In FIG. 4(a), in order to manufacture a tape carrier (film carrier), a metal plate (copper plate) 3 is adhered to the top surface of a heat-resistant insulating film (polyimide tape) 2.
use.
板材ｌの金パッド（１２）を接続（エツチング）して形
成されるテープキャリア４は、第４図（ＩＩ）に示す如
く、絶縁フィルム２から形成した絶縁フィルム基体８に
、金属板３から形成し導体パターン５が被着されてなる
。絶縁フィルム基体８は、リード６を表呈させる透孔９
を有する。導体パターン５は、放射状に配設された多数
のりード６の各外端部が一点鎖線１３の位置で角形枠状
連結部７に連結され、導体パターン５の全表呈面には錫
めっきが被着される。The tape carrier 4 formed by connecting (etching) the gold pads (12) of the plate material 1 is formed from the metal plate 3 on the insulating film base 8 formed from the insulating film 2, as shown in FIG. 4 (II). A conductor pattern 5 is then deposited. The insulating film base 8 has through holes 9 through which the leads 6 are exposed.
has. In the conductor pattern 5, each outer end of a large number of leads 6 arranged radially is connected to a rectangular frame-shaped connecting part 7 at a position indicated by a chain line 13, and the entire surface of the conductor pattern 5 is tin-plated. is deposited.
第４図（ハ）において、下面に金パッド１２の形成され
た半導体チップ１１をテープキャリア４に搭載し、錫め
っき膜１０の被着された各リード６の内端部と金パッド
１２とを熱圧着させると、その圧着部には金一錫共晶体
が生威し、該共晶体によってリード６とパッド１２は電
気的，機械的に接続されるようになる。In FIG. 4(c), the semiconductor chip 11 with the gold pads 12 formed on the lower surface is mounted on the tape carrier 4, and the inner ends of each lead 6 covered with the tin plating film 10 are connected to the gold pads 12. When thermocompression bonding is performed, a gold-tin eutectic grows in the bonded portion, and the lead 6 and the pad 12 are electrically and mechanically connected by the eutectic.
次いで、一点鎖線１３に沿って切断し各リード６を連結
部７から切り離したのち、第４図（二）に示すように、
錫めっき膜１０の被着された各リード６の外端部を、パ
ッケージ基体１４の上面に形成された金パッド１５に熱
圧着させると、その圧着部に生成された金一錫共晶体に
よって、リード６と金パッド１５は電気的，機械的に接
続される。Next, after cutting along the dashed line 13 to separate each lead 6 from the connecting portion 7, as shown in FIG. 4(2),
When the outer end of each lead 6 coated with the tin plating film 10 is thermocompression bonded to the gold pad 15 formed on the upper surface of the package base 14, the gold-tin eutectic produced at the bonded portion causes Leads 6 and gold pads 15 are electrically and mechanically connected.
なお、第４図（二）においてセラミック基体ｌ４は多層
配線構成であり、基体１４の下面より垂下する各リード
端子１６は、基体ｌ４内の配線によって、基体１４の上
面に形成された金パッド１５に接続しており、基体１４
の上面にセラミックキャップを被せ半導体装置１７が完
成する。In FIG. 4(2), the ceramic substrate 14 has a multilayer wiring structure, and each lead terminal 16 hanging down from the bottom surface of the substrate 14 is connected to a gold pad 15 formed on the top surface of the substrate 14 by the wiring inside the substrate 14. is connected to the base 14
A ceramic cap is placed on the top surface of the semiconductor device 17 to complete the semiconductor device 17.
［発明が解決しようとする諜Ｂ］
以上説明したように、２リードを金−錫共晶体で接続し
た従来の半導体装置において、リードに被着された錫め
っき膜の厚さは、１〜２μｍ程度の薄いものであった。[Secret B to be Solved by the Invention] As explained above, in a conventional semiconductor device in which two leads are connected by a gold-tin eutectic, the thickness of the tin plating film deposited on the leads is 1 to 2 μm. It was a minor one.
このような錫めっき膜は加熱を要する金−錫共晶体によ
る接続、特に、第１回目の接続で半導体チップと接続し
たのち、パッケージ基体と接続させる第２回目の接続に
際し錫の量が不充分であった。Such a tin plating film is used for connections using gold-tin eutectics that require heating, especially when the amount of tin is insufficient for the second connection to the package substrate after the first connection to the semiconductor chip. Met.
そこで、従来方法と同じめっきにより錫膜を厚くすると
、錫めっき膜は表面が粗れて厚さのばらつきが大きくな
ると共に、ホイスカーの発生、成長が顕著となり、金−
錫共晶体接続の不良率が高くなるという問題点があった
。Therefore, when the tin film is thickened by the same plating method as in the conventional method, the surface of the tin plating film becomes rough and the variation in thickness becomes large, and the generation and growth of whiskers becomes noticeable.
There was a problem in that the failure rate of tin eutectic connections was high.
［課題を解決するための手段］
上記問題点の解決を目的とした本発明方法は、その実施
例に係わる第１図によれば、内端部が半導体チップ１１
に接続されるリード６を、金属板３の上面に錫箔２２の
接合された複合板２１から形成し、金属板３からの主導
体部６ａに錫箔２２からの錫箔層６ｂが接合するり−ド
６の錫箔層６ｂに、リード６の接続相手の金パッド１２
．１５を接続することを特徴とした半導体装置２６、
および、金属板の上面と下面とに錫箔を接合した複合板
から形成したリードを利用したことを特徴とする半導体
装置、
さらに、金属板の少なくとも一方の面に錫箔を結合した
複合板からリードフレームを形成し、該リードフレーム
を使用することを特徴とした前記半導体装置の製造方法
、
前記複合板に絶縁フィルムを接着したものからテープキ
ャリアを形成し、リードを使用することを特徴とした前
記半導体装置の製造方法である。[Means for Solving the Problems] According to the method of the present invention aimed at solving the above-mentioned problems, as shown in FIG.
A lead 6 connected to the metal plate 3 is formed from a composite plate 21 with a tin foil 22 bonded to the upper surface of the metal plate 3, and a tin foil layer 6b from the tin foil 22 is bonded to the main conductor portion 6a from the metal plate 3. The gold pad 12 to which the lead 6 is connected is placed on the tin foil layer 6b of the lead 6.
．． 15, and a semiconductor device characterized in that it utilizes a lead formed from a composite plate in which tin foil is bonded to the upper and lower surfaces of a metal plate. A method for manufacturing a semiconductor device, characterized in that a lead frame is formed from a composite plate with tin foil bonded to one surface, and the lead frame is used; A tape carrier is formed from an insulating film bonded to the composite plate. The method of manufacturing the semiconductor device is characterized in that a lead is used.
リードの主導体部形成用の金属板に錫箔を接合した上記
手段によれば、リードとその接続相手とを金−錫共晶体
で接続するのに必要な錫の量が確保され、かつ、錫箔は
錫の厚めつきより表面が平滑にしてホイスカーが存在し
ないため、金−錫共晶体接続が均一化されることによっ
て、該接続に係わる不良率が低減される。According to the above method in which tin foil is bonded to the metal plate for forming the main conductor portion of the lead, the amount of tin necessary to connect the lead and its connection partner with the gold-tin eutectic is secured, and the amount of tin foil is Since the surface is smoother than that of thick tin and there are no whiskers, the gold-tin eutectic connection is made uniform, thereby reducing the defect rate related to the connection.
〔実施例〕 以下に、図面を用いて本発明方法の実施例を説明する。〔Example〕 Examples of the method of the present invention will be described below with reference to the drawings.
第１図（イ）〜（ニ）は本発明の第１の実施例による半
導体装置の製造方法の説明図、第２図（イ）〜（：）は
本発明の第２の実施例による半導体装置の製造方法の説
明図、第３図（イ）〜（ニ）は本発明の第３の実施例に
よる半導体装置の製造方法の説明図である。なお、第１
図（イ）、（ニ）と第２図（イ）８（＝）と第３図（イ
）、（、：）は側面図、第１図（ＩＩ＋）と第２図（Ｕ
）は一部分を破断した平面図、第１図（ハ）と第２図（
ハ）と第３図（０） 、 （ハ）は側断面図である。FIGS. 1(a) to (d) are explanatory diagrams of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. 2(a) to (:) are illustrations of a semiconductor device according to a second embodiment of the present invention. 3(a) to 3(d) are explanatory diagrams of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. In addition, the first
Figures (A), (D), Figure 2 (A) 8 (=), Figure 3 (A), (,:) are side views, Figure 1 (II+) and Figure 2 (U).
) is a partially cutaway plan view, Figure 1 (C) and Figure 2 (
Figures 3(0) and 3(c) are side sectional views.
第１図（イ）において、リードフレームの製造に使用す
る複合板２１は、金属板例えば厚さ３５μ隅の銅板３の
上面に、例えば厚さｌＯｔ！−の錫箔２２を接合（クラ
ッド）したものである。In FIG. 1(A), a composite plate 21 used for manufacturing a lead frame is placed on the upper surface of a metal plate, for example, a copper plate 3 with a thickness of 35 μm at a corner, and has a thickness of, for example, lOt! − tin foil 22 is bonded (clad).
複合板２１の金パッド（１２）を接続（エツチング）し
て形成されるリードフレーム２３は、第１図（ロ）に示
す如く、銅板３の金パッド（１２）を接続した導体パタ
ーン２４と、錫箔２２より形成され導体パターン２４の
全上面に被着する錫箔パターン２５にてなる。導体パタ
ーン２４は放射状に整列する多数のり一部６の主導体部
６ａを具え、主導体部６ａの上面には錫箔パターン２５
の一部である錫箔層６ｂが接合する。A lead frame 23 formed by connecting (etching) the gold pads (12) of the composite board 21 has a conductor pattern 24 connecting the gold pads (12) of the copper plate 3, as shown in FIG. It consists of a tin foil pattern 25 formed of tin foil 22 and covering the entire upper surface of the conductive pattern 24. The conductor pattern 24 includes a plurality of main conductor portions 6a of the glue portions 6 arranged radially, and a tin foil pattern 25 is formed on the upper surface of the main conductor portion 6a.
The tin foil layer 6b, which is a part of the above, is bonded.
第１図（ハ）において、リードフレーム２３に搭載され
る半導体チップ１１は、下面に形成された金パッド１２
をリード主導体部６ａの内端部の錫箔層６ｂに熱圧着さ
せる。その結果、半導体チップ１１とリード６とは金−
錫共晶体によって電気的１機械的に接続される。In FIG. 1(C), the semiconductor chip 11 mounted on the lead frame 23 has gold pads 12 formed on the lower surface.
is thermocompression bonded to the tin foil layer 6b at the inner end of the lead conductor portion 6a. As a result, the semiconductor chip 11 and the leads 6 are made of gold.
electrically and mechanically connected by a tin eutectic.
次いで、リードフレーム２３を主導体部６ａの接続部で
切断し、第１図（ニ）に示すように、各リード主導体部
６ａの外端部に被着された錫箔Ｎ６ｂと、パッケージ基
体１４の上面に形成された金パッド１５とを熱圧着によ
り接続させると、リード６と金パッド１５とは金−錫共
晶体によって電気的１機械的に接続される。そこで、基
体１４の上面にセラミックキャップを被せると半導体装
置２６が完成する。Next, the lead frame 23 is cut at the connection part of the main conductor part 6a, and as shown in FIG. When the lead 6 and the gold pad 15 formed on the upper surface are connected by thermocompression bonding, the lead 6 and the gold pad 15 are electrically and mechanically connected by the gold-tin eutectic. Then, by covering the top surface of the base body 14 with a ceramic cap, the semiconductor device 26 is completed.
第２図（イ）において、テープキャリア（フィルムキャ
リア）の製造に使用する板材３１は、主導体金属の薄板
例えば厚さ３５μｍの銅板３の上面に例えば厚さ１０μ
ｍの錫箔２２を接合（クラッド）した複合板２１、主導
体金属板３の下面に接着した耐熱性絶縁フィルム（ポリ
イミドテープ）２にて構成される。In FIG. 2(A), a plate material 31 used for manufacturing a tape carrier (film carrier) is a thin plate of main conductor metal, for example, a copper plate 3 having a thickness of 35 μm, and a thickness of, for example, 10 μm.
It is composed of a composite plate 21 bonded (clad) with a tin foil 22 of 300 mm, and a heat-resistant insulating film (polyimide tape) 2 adhered to the lower surface of the main conductor metal plate 3.
複合板２１および絶縁フィルム２の金パッド（１２）を
接続（エツチング）して形成されるテープキャリア３２
は、第２図（０）に示す如く、銅板３の金パッド（１２
）を接続した導体パターン３３と、錫箔２２より形成さ
れた錫箔パターン３４と、透孔３６のあいた絶縁フィル
ム基板３５にてなる。導体パターン３３は放射状に整列
する多数のり一部６の主導体部６ａを具え、主導体部６
ａの上面には錫箔パターン３４の一部である錫箔１６ｂ
が接合し、絶縁フィルム基板３５の透孔３６にはり−ド
６が表呈する。Tape carrier 32 formed by connecting (etching) the composite plate 21 and the gold pad (12) of the insulating film 2
As shown in FIG. 2(0), the gold pad (12
), a tin foil pattern 34 formed from the tin foil 22, and an insulating film substrate 35 with a through hole 36. The conductor pattern 33 includes a plurality of main conductor portions 6a of the glue portions 6 arranged radially, and the main conductor portions 6a are arranged radially.
On the top surface of a is a tin foil 16b that is part of the tin foil pattern 34.
are bonded to each other, and the beam 6 is exposed in the through hole 36 of the insulating film substrate 35.
第２図（ハ）において、テープキャリア３２に搭載され
た半導体チップ１１は、下面に形成された金パッド１２
をリード主導体部６ａの内端部の錫箔層３４に熱圧着さ
せる。その結果、半導体チップ１１とり−ド６とは金−
錫共晶体によって電気的１機械的に接続されるようにな
る。In FIG. 2(C), the semiconductor chip 11 mounted on the tape carrier 32 has gold pads 12 formed on the bottom surface.
is thermocompression bonded to the tin foil layer 34 at the inner end of the lead conductor portion 6a. As a result, the semiconductor chip 11 and the board 6 are made of gold.
The tin eutectic provides an electrical and mechanical connection.
次いで、テープキャリア３２を主導体部６ａの接続部で
切断し、第２図（＝）に示すように、各リード主導体部
６ａの外端部に被着された錫箔層３４と、パッケージ基
体１４の上面に形成された金パッド１５とを熱圧着によ
り接続させると、リード６と金パッド１５とは金−錫共
晶体によって電気的、Ｓ械的に接続される。そこで、基
体１４の上面にセラミックキャップを被せると半導体装
置３７が完成する。Next, the tape carrier 32 is cut at the connection part of the main conductor part 6a, and as shown in FIG. When the lead 6 and the gold pad 15 formed on the upper surface of the lead 14 are connected by thermocompression bonding, the lead 6 and the gold pad 15 are electrically and S-mechanically connected by the gold-tin eutectic. Then, by covering the top surface of the base body 14 with a ceramic cap, the semiconductor device 37 is completed.
第３図（イ〉において、リードフレームの製造に使用す
る複合板４１は、金属板例えば厚さ３５μｍの銅板３の
上面に、例えば厚さ１０μｍの錫箔４２を接合（クラッ
ド）し、銅板３の下面に例えば厚さ１０μｍの錫箔４３
を接合（クラッド）したものである。In FIG. 3 (A), a composite plate 41 used for manufacturing a lead frame is made by bonding (cladding) a tin foil 42 with a thickness of 10 μm to the top surface of a metal plate 3, such as a copper plate 3 with a thickness of 35 μm. For example, a tin foil 43 with a thickness of 10 μm is placed on the bottom surface.
It is made by joining (cladding).
第３図（ＴＩ）において、複合板４Ｉの金パッド（１２
）を接続（エツチング）して形成されるリードフレーム
４４は、第１図（ＩＩ）に示すリードフレーム２３と平
面形状が同一であり、銅板３の金パッド（１２）を接続
した導体パターン２４の全上面に錫箔４２より形成され
た錫箔パターン４５が接合し、導体パターン２４の全下
面には錫箔４３より形成された錫箔パターン４６が接合
される。導体パターン２４は多数の主導体部６ａを具え
、主導体部６ａの上面と下面には錫箔パターン４５また
は４６の一部である錫箔Ｎ６ｂが接合する。In Figure 3 (TI), the gold pad (12
) is formed by connecting (etching) the lead frame 44, which has the same planar shape as the lead frame 23 shown in FIG. A tin foil pattern 45 made of tin foil 42 is bonded to the entire top surface, and a tin foil pattern 46 made of tin foil 43 is bonded to the entire bottom surface of the conductor pattern 24 . The conductor pattern 24 includes a large number of main conductor parts 6a, and tin foil N6b, which is a part of the tin foil pattern 45 or 46, is bonded to the upper and lower surfaces of the main conductor parts 6a.
第３図（ハ）において、リードフレーム４４に搭載され
た半導体チップ１１は、下面に形成された金パッドＩ２
とリード主導体部６ａの上面内端部の錫箔層６ｂに熱圧
着させる。その結果、半導体チップ１１とリード６とは
金−錫共晶体によって電気的９機械的に接続される。In FIG. 3(C), the semiconductor chip 11 mounted on the lead frame 44 has a gold pad I2 formed on the lower surface.
and thermocompression bonded to the tin foil layer 6b at the inner end of the upper surface of the lead conductor portion 6a. As a result, the semiconductor chip 11 and the leads 6 are electrically and mechanically connected by the gold-tin eutectic.
次いで、リードフレーム４４を主導体部６ａの接続部で
切断し、第３図（＝）に示すように、各リード主導体部
６ａの下面外端部に被着された錫箔層６ｂとパッケージ
基体１４の上面に形成された金パッド１５とを熱圧着さ
せると、リード６と金パッド１５とは金−錫共晶体によ
って電気的２機械的に接続される。そこで、基体１４の
上面にセラミックキャップを被せると半導体装置４７が
完成する。Next, the lead frame 44 is cut at the connection part of the main conductor part 6a, and as shown in FIG. When the lead 6 and the gold pad 15 formed on the upper surface of the lead 14 are bonded by thermocompression, the lead 6 and the gold pad 15 are electrically and mechanically connected by the gold-tin eutectic. Then, by covering the top surface of the base 14 with a ceramic cap, the semiconductor device 47 is completed.
なお、前記実施例において主導体金属には鋼の薄板を使
用したが、本発明は銅の薄板に替えて他の金属薄板、例
えばリードフレーム用複合板にステンレス等の薄板を使
用し、実施例と同等の効果が得られる。In the above embodiments, a thin steel plate was used as the main conductor metal, but in the present invention, instead of the copper thin plate, another thin metal plate, such as a thin plate of stainless steel or the like, is used as a composite plate for a lead frame. The same effect can be obtained.
また、第３の実施例に使用した複合板４１の一方の面（
錫箔４２または４３）に絶縁フィルム（ポリイミドテー
プ）を接着し、その板材より第２の実施例におけるテー
プキャリア３２と同様なテープキャリアを作成すれば、
本発明方法に係わる他の構成例の半導体装置が実現する
。Also, one side (
If an insulating film (polyimide tape) is adhered to the tin foil 42 or 43) and a tape carrier similar to the tape carrier 32 in the second embodiment is made from the plate material,
A semiconductor device having another configuration example related to the method of the present invention is realized.
以上説明したように本発明方法によれば、リード主導体
部形成用の金属板に錫箔を接合した複合板を利用するこ
とによって、リードとその接続相手とを金−錫共晶体で
接続するのに必要な錫の量が確保され、かつ、錫箔は錫
の厚めつきより表面が平滑にしてボイスカーが存在しな
いため、金−錫共晶体接続が均一化されることによって
、該接続に係わる半導体装置の不良率が、従来の１７５
〜１／１０に低減されるようになった。As explained above, according to the method of the present invention, by using a composite plate in which tin foil is bonded to a metal plate for forming a lead conductor part, a lead and its connection partner can be connected using a gold-tin eutectic. The necessary amount of tin is secured, and the surface of the tin foil is smoother than the thicker tin, and there is no voice car. Therefore, the gold-tin eutectic connection is made uniform, and the semiconductor device related to the connection is improved. The defect rate of 175
It has now been reduced to ~1/10.
第１図は本発明の第１の実施例による半導体装置の製造
方法の説明図、
第２図は本発明の第２の実施例による半導体装置の製造
方法の説明図、
第３図は本発明の第３の実施例による半導体装置の製造
方法の説明図、
第４図は金−錫共晶体接続を利用した従来の半導体装置
の製造方法の説明図、
図中において、
２は絶縁フィルム、
３は金属板、
６はリード、
６ａは主導体部、
６ｂは錫箔層、
１１は半導体チップ、
１２、１５は金パッド、
１４はパッケージ基体、
２１．４１は複合板、
２２、４２．４３は錫箔、
２３．４４ はリードフレーム、
２６．３７．４７は半導体装置、
３２はテープキャリア、
を示す。
旦す−トフし一ム
（
本発明の第１の突７ｉ！例ｔｒ！＋犀体裟夏Ｏ製逍方法
の逆明因早
図
１１＋捧イ２ト・ラー７７゜
第 ２ 文
、木茫明の第３のツζ′袴ｆｉｌ二Ｉう午譚イ本に夏の
製造巧；太の説明間第 ３ 記FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is an explanatory diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 4 is an explanatory diagram of a conventional method of manufacturing a semiconductor device using gold-tin eutectic connection. In the figure, 2 is an insulating film; 3 is an insulating film; is a metal plate, 6 is a lead, 6a is a main conductor part, 6b is a tin foil layer, 11 is a semiconductor chip, 12, 15 are gold pads, 14 is a package base, 21.41 is a composite board, 22, 42.43 are tin foils , 23.44 is a lead frame, 26.37.47 is a semiconductor device, and 32 is a tape carrier. (The first thrust of the present invention 7i! Example tr! + Reverse light and early diagram of the method of producing rhinoceroses in summer 11 + Dedication 2 to 77゜ 2nd sentence, Mokusaku The Ming Dynasty's third book ζ' Hakama fil 2 I Ugotan's book on summer production; Tai's explanation part 3
Claims (1)
ード（６）を、金属板（３）の一方の面に錫箔（２２）
の接合された複合板（２１）から形成し、 該金属板（３）より形成されたの主導体部（６ａ）に該
錫箔（２２）より形成された錫箔層（６ｂ）が接合する
該リード（６）の該錫箔層（６ｂ）が、該半導体チップ
（１１）に形成された金パッド（１２）と半導体チップ
搭載基体（１４）に形成された金パッド（１５）に接続
されてなることを特徴とする半導体装置。 ２）一方の端部が半導体チップ（１１）に接続されるリ
ード（６）を、金属板（３）の一方の面に錫箔（４２）
を接合し他方の面に錫箔（４３）の接合された複合板（
４１）から形成し、 該金属板（３）より形成されたの主導体部（６ａ）に該
錫箔（４２）により形成された錫箔層（６ｂ）が該半導
体チップ（１１）に形成された金パッド（１２）に接合
し、半導体チップ搭載基体（１４）に形成された金パッ
ド（１５）に接続されてなることを特徴とする半導体装
置。 ３）金属板（３）の少なくとも一方の面に錫箔（２２、
４２、４３）を接合して前記複合板（２１、４１）とし
、該複合板（２１、４１）の不要部を除去して前記リー
ド（６）を有するリードフレーム（２３、４４）を形成
し、該リードフレーム（２３、４４）のリード（６）の
錫箔層（６ｂ）に前記半導体チップ（１１）の金パッド
（１２）を接続し、 該リードフレーム（２３、４４）の不要部を除去したの
ち、 該錫箔層（６ｂ）を前記半導体チップ搭載基体（１４）
の金パッド（１５）に接続することを特徴とする前記請
求項１または２記載半導体装置の製造方法。 ４）金属板（３）の少なくとも一方の面に錫箔（２２、
４２、４３）を接合して前記複合板（２１、４１）とし
、該複合板（２１、４１）の下面に絶縁フィルム（２）
を接着し、 該複合板（２１、４１）と該絶縁フィルム（２）の不要
部を除去して前記リード（６）を有するテープキャリア
（３２）を作成し、 該テープキャリア（３２）のリード（６）の錫箔層（６
ｂ）に前記半導体チップ（１１）の金パッド（１２）を
接続し、 該テープキャリア（３２）の不要部を除去したのち、該
錫箔層（６ｂ）を前記半導体チップ搭載基体（１４）の
金パッド（１５）に接続することを特徴とする前記請求
項１または２記載半導体装置の製造方法。[Claims] 1) A lead (6) whose one end is connected to the semiconductor chip (11) is attached to one side of the metal plate (3) using a tin foil (22).
The lead is formed from a bonded composite plate (21), and the tin foil layer (6b) formed from the tin foil (22) is bonded to the main conductor portion (6a) formed from the metal plate (3). (6) The tin foil layer (6b) is connected to the gold pad (12) formed on the semiconductor chip (11) and the gold pad (15) formed on the semiconductor chip mounting base (14). A semiconductor device characterized by: 2) A lead (6) whose one end is connected to the semiconductor chip (11) is attached to one side of the metal plate (3) using tin foil (42).
A composite board (
41), and a tin foil layer (6b) formed from the tin foil (42) is formed on the main conductor portion (6a) formed from the metal plate (3), and a tin foil layer (6b) formed from the tin foil (42) is formed from the gold formed on the semiconductor chip (11). A semiconductor device characterized by being bonded to a pad (12) and connected to a gold pad (15) formed on a semiconductor chip mounting base (14). 3) Tin foil (22,
42, 43) are joined to form the composite plate (21, 41), and unnecessary parts of the composite plate (21, 41) are removed to form a lead frame (23, 44) having the lead (6). , connect the gold pad (12) of the semiconductor chip (11) to the tin foil layer (6b) of the lead (6) of the lead frame (23, 44), and remove unnecessary parts of the lead frame (23, 44). After that, the tin foil layer (6b) is attached to the semiconductor chip mounting base (14).
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is connected to a gold pad (15) of the semiconductor device. 4) Tin foil (22,
42, 43) are joined to form the composite plate (21, 41), and an insulating film (2) is placed on the lower surface of the composite plate (21, 41).
and removing unnecessary parts of the composite plate (21, 41) and the insulating film (2) to create a tape carrier (32) having the lead (6), and the lead of the tape carrier (32). (6) Tin foil layer (6
After connecting the gold pad (12) of the semiconductor chip (11) to b) and removing unnecessary parts of the tape carrier (32), the tin foil layer (6b) is connected to the gold pad of the semiconductor chip mounting base (14). 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is connected to a pad (15).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1194697A JPH0360051A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1194697A JPH0360051A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360051A true JPH0360051A (en) | 1991-03-15 |
Family
ID=16328769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1194697A Pending JPH0360051A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360051A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009020068A (en) * | 2007-07-13 | 2009-01-29 | Ono Sokki Co Ltd | Movable floor for vehicle testing device, and vehicle testing device equipped with the floor |
| WO2016027593A1 (en) * | 2014-08-22 | 2016-02-25 | 株式会社 豊田自動織機 | Bonding structure, bonding material and bonding method |
-
1989
- 1989-07-27 JP JP1194697A patent/JPH0360051A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009020068A (en) * | 2007-07-13 | 2009-01-29 | Ono Sokki Co Ltd | Movable floor for vehicle testing device, and vehicle testing device equipped with the floor |
| WO2016027593A1 (en) * | 2014-08-22 | 2016-02-25 | 株式会社 豊田自動織機 | Bonding structure, bonding material and bonding method |
| JPWO2016027593A1 (en) * | 2014-08-22 | 2017-05-25 | 株式会社豊田自動織機 | Bonding structure, bonding material, and bonding method |
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