JPH035988A - Dynamic memory - Google Patents

Abstract

PURPOSE:To enlarge the logical amplitude of a memory cell when data are stored, to reduce the burden of a sense amplifier when the data are read and to securely access the data at high speed by changing the potential of a not- referring side in the memory cell of a dynamic memory. CONSTITUTION:When the data are written and the logical value of the data to be appear in a bit line 1 is 1, out of potential generating circuits, the circuit to generate the lower potential is connected to the data not-referring side of a memory cell 3 connected to the bit line 1. When the logical value of the data to appear in the bit line 1 is 0, out of the potential generating circuits, the circuit to generate the higher potential is connected to the data not-referring side of the memory cell 3. Accordingly, the voltage potential of the data to be stored is made large only for difference between the two potentials to be generated by the potential generating circuits. Thus, the voltage amplitude of the memory cell is enlarged and when the data are read, the burden of the sense amplifier can be reduced. Then, the data can be securely accessed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application The present invention relates to a dynamic memory.Prior Art FIG. 2 shows a circuit around a cell of a conventional dynamic memory. In the same figure, 1 is a bit 1L2 is a word chain that drives transistor 6 3 is a memory cell) 5 4 is a data reference power supply for memory cell 3 5 is a data non-reference power supply for memory cell 3 6 is a bit line for data of memory cell 3 l
The transistor 12 is a dummy cell corresponding to the memory cell 3, and the bit line equalizer precharges the two bit lines to a constant potential. Even if the sense amplifier circuit has a sense amplifier circuit, the reading operation of the memory cell data logical value 1 by the sense amplifier will be explained using FIG. Then, when the transistor 6 is driven by the word line 2, a change in potential based on the stored data appears on the bit line 1. Electric image of 4 Precharge electric image Capacity of memory cell 3 Determined by the capacitance of bit line 1, and the larger the voltage amplitude of the stored data in memory cell 3, the sharper the voltage is. As shown in Figure 3, the bit line 1 is amplified by detecting a change in potential. (As shown in Figure 2 above, the potential on the opposite side 5 of the data reference side 4 of the memory cell 3 is kept at a potential between the power supply potential and the ground potential by the potential generation circuit throughout the data access of the memory cell 3. Tahachi
The voltage amplitude of the memory cell 3 is half the value of the power supply voltage.9 Problems to be Solved by the Invention With the above configuration, the voltage amplitude of the memory cell during data storage is small, and the voltage amplitude when reading data is Therefore, it is an object of the present invention to provide a dynamic memory capable of more reliable and faster data access.

Means for Solving the Problems The present invention solves the above-mentioned problems.8 By reading and writing data and the value of data appearing on the bit line, one of the three potential generation circuits is set to the data non-reference side of the memory cell. According to the above-described structure, if the data appearing on a bit line has a logical value of 1 during data writing, the data in the memory cell connected to that bit line is not referenced. The circuit that generates a lower potential among the potential generation circuits is connected to the side. If the data appearing on the bit line has a logical value of 0 ('L), the circuit that generates a higher potential among the upper potential generating circuits is connected to the data non-reference side of the memory cell connected to that bit line. Therefore, the voltage amplitude of the stored data (the difference between the two potentials generated by the potential generation circuit) increases. Embodiment 1 Hereinafter, a dynamic memory according to an embodiment of the present invention will be explained with reference to FIG. , 4 is the data reference side L of the memory cell 3 5 is the data non-reference side of the memory cell 3 @ 6 is the transistor driven by the word line 2 8 is the load transistor for dividing the voltage 7 is the width of the load transistor 8 Sufficiently large transistor length 9
11 is a transistor for connecting the potential generated at point A to the data non-reference side 5 of the memory cell 3. lO is a transistor for connecting the potential generated at point B to the data non-reference side 5 of the memory cell 3. is a transistor for connecting the potential generated at point C to the data non-reference side 5 of the memory cell 3. Part 1 is a transistor 7 which is a key point in the present invention.
, 8 and a transistor 9,
The operation of the dynamic memory of this embodiment will be explained below using the connection circuit of IQ and 11. At the time of writing, R/W becomes a logic value O,
The read potential selection transistor 11 is turned off. Then, with the bare load transistor 8 of the same size and the transistor 7 whose width is sufficiently larger than the load transistor 8, at point A (from the ground potential (Vcc - VTll) / 2
ff1LVcc: Power supply voltage VTII: Threshold voltage of transistor 7, LB
At the point (from ground potential to (Vcc+V TO) / 2 (2)
Here, when data of logical value 1 appears on the bit line 1, the low potential selection transistor 9 is driven, and the potential of the data non-reference side 5 of the memory cell 3 is shown as (1). Also, when data with a logic value of 0 appears on the bit line 1, the high potential selection transistor 10 is driven, and the potential on the data non-reference side 5 of the memory cell 3 becomes the potential shown in (2).Logic value The potential of the bit line in the case of 1 is VCC with respect to the ground potential, and the potential of the bit line in the case of logic 0 is equal to the ground potential, so in both cases, the voltage amplitude applied to both ends of the memory cell 3 ( Up (
Even if the value of 2) is larger than the value of half the power supply voltage of the conventional example, the following: At the time of reading, R/W becomes a logical value 1, and the potential ζ at point C becomes Vcc/2. (3)
The potential at point C is then connected to the data non-reference side 5 of the memory cell 3 by the read potential selection transistor 11. Here, when data of logical value l is stored in the memory cell 3, the potential ζ of the data reference side 4 of the memory cell 3 becomes a value from the ground potential to Vcc+VTII/2 (4). Furthermore, when data with a logical value of 0 is stored in the memory cell 3, the potential of the data reference side 4 of the memory cell 3 (from the ground potential to VTN/2
(5) Therefore, compared to the conventional technology, the bit line opening during readout can be made larger, ensuring data readout and achieving high speed. Dai By changing the potential on the non-reference side of the memory cell of dynamic memory,
By increasing the logic amplitude of memory cells when storing data and reducing the load on the sense amplifier when reading data, more reliable and faster data access is achieved.

[Brief explanation of the drawing]

FIG. 1 shows a memory cell peripheral circuit diagram according to an embodiment of the present invention. FIG. 2 shows a conventional memory cell peripheral circuit diagram.

Claims (1)

[Claims] A dynamic memory equipped with a circuit that changes the potential on the non-data reference side of the memory cell to three levels depending on the data value appearing on the bit line and data reading/writing.