JPH0358706U - - Google Patents

Info

Publication number
JPH0358706U
JPH0358706U JP11837189U JP11837189U JPH0358706U JP H0358706 U JPH0358706 U JP H0358706U JP 11837189 U JP11837189 U JP 11837189U JP 11837189 U JP11837189 U JP 11837189U JP H0358706 U JPH0358706 U JP H0358706U
Authority
JP
Japan
Prior art keywords
communication
instruction means
programmable controller
storage means
communication methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11837189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11837189U priority Critical patent/JPH0358706U/ja
Publication of JPH0358706U publication Critical patent/JPH0358706U/ja
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案実施例の回路構成を示すブロツ
ク図、第2図は本考案実施例の外観を示す斜視図
、第3図は本考案実施例のCPU1が実行する制
御手順を示すフローチヤート、第4図は従来例の
システムの接続状態を示す斜視図である。 1……CPU、1−1……プログラム指示スイ
ツチ、2……ROM、3……RAM。
Fig. 1 is a block diagram showing the circuit configuration of the embodiment of the invention, Fig. 2 is a perspective view showing the external appearance of the embodiment of the invention, and Fig. 3 is a flowchart showing the control procedure executed by the CPU 1 of the embodiment of the invention. , FIG. 4 is a perspective view showing the connection state of a conventional system. 1...CPU, 1-1...Program instruction switch, 2...ROM, 3...RAM.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の通信方式を選択指示する指示手段と、前
記複数の通信方式に対応してプログラマブルコト
ローラとの間で通信を行うための複数の通信プロ
グラムを予め記憶した記憶手段と、前記指示手段
により指示された通信方式の通信プログラムを前
記記憶手段から読出して実行する演算処理手段と
を具えたことを特徴とするプログラマブルコント
ローラの入出力装置。
an instruction means for selecting and instructing a plurality of communication methods; a storage means storing in advance a plurality of communication programs for communicating with a programmable controller corresponding to the plurality of communication methods; and an instruction means provided by the instruction means. 1. An input/output device for a programmable controller, comprising: arithmetic processing means for reading out and executing a communication program of a communication method from the storage means.
JP11837189U 1989-10-09 1989-10-09 Pending JPH0358706U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11837189U JPH0358706U (en) 1989-10-09 1989-10-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11837189U JPH0358706U (en) 1989-10-09 1989-10-09

Publications (1)

Publication Number Publication Date
JPH0358706U true JPH0358706U (en) 1991-06-07

Family

ID=31666541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11837189U Pending JPH0358706U (en) 1989-10-09 1989-10-09

Country Status (1)

Country Link
JP (1) JPH0358706U (en)

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