JPH0358423A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the production of non-volatile and insulating aluminum fluoride increasing the contact resistance by a method wherein a silicon ion- implanting process in the surface of a lower wiring film exposed to an interlayer connecting hole is provided. CONSTITUTION:A silicon implanted iayer 7 is formed by ion-implanting process in the surface of a lower layer wiring film 3 exposed to an interlayer connecting hole 9. Later, a metallic film 5 produced by reducing metal fluoride gas is selectively deposited on the lower layer wiring film 3 through the silicon implanted layer 7 during the metal burying process. That is, a volatile silicon fluoride is selectively formed by the silicon implanted layer 7 so that the non- volatile and insulating aluminum fluoride which is produced when the metallic film 5 is directly deposited on the lower layer wiring film 3 may not be produced. Through these procedures, the contact resistance can be lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for interlayer connection of A multilayer interconnections required in sub-ξchron standard VLSI and the like.

l (Prior art) As device miniaturization progresses, ,11 (or its alloy,
Wiring (hereinafter referred to simply as Aj2) cannot cope with the miniaturization of its wiring width and the increase in the aspect ratio (hole depth/closed dimension) of interlayer connection holes that connect the upper and lower layers of 80 multilayer wiring. This causes problems in wiring technology, such as reduced reliability.

Therefore, as a new wiring technology, a method of selectively forming metals such as tungsten (W) and molybdenum (Mo) into interlayer connection holes using CVD has been proposed. It is attracting attention as a promising method to solve this problem.

However, when connecting AA multilayer wiring with these metals such as W and Mo, raw material gases (WF b , M o F & )
The fluorine (F) generated when the fluorine (F) decomposes reacts with the bottom @AN cotton and forms insulating and non-volatile aluminum fluoride (AffiF.) during the initial deposition process, resulting in extremely high contact resistance. There is a problem with this.

In view of the above problem, as shown in FIG. 2, the surface of the first layer Al wiring film 3 is coated with MoSi2 or TISi. barrier layer 6
There are some methods that lower the contact resistance by pulling .

This means that the exposed portion of the interlayer connection hole of the underlying wiring layer is M
o S i z or T t S i z, the reduction reaction of the source gas by Mo or Ti does not occur, and in the initial stage of W or Mo deposition, the deposition proceeds only by the reduction reaction of Si, making it difficult to sublimate. Reaction by-products (/lF
This is because 3) does not occur.

In FIG. 2, l is an St substrate, 2a and 2b are interlayer insulating films, 3 is a lower layer AN wiring film, 4 is an upper layer Al wiring film,
5 is embedded metal (W, Mo, etc.) for connecting between the eyebrows, 6
is a barrier layer.

[The problem that the invention aims to solve]

However, when manufacturing the structure described above, in order to form the barrier layer 6 for reducing the contact resistance, it is necessary to add two steps: a step of depositing the barrier layer 6 and an etching step. In other words, the more multilayered the structure, the more the number of steps will be required. Furthermore, if manufacturing takes into account the barrier layer deposition thickness, the thickness of the lower AI2 wiring film will become thinner by that thickness, and the resistance value per unit cross-sectional area of the Af wiring WA3 will increase. .

In view of the above problems, the present invention can lower the contact resistance by adding only one process, and reduce the lower layer AI! ．．
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the resistance value per unit cross-sectional area of a wiring film does not increase.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a connection in which an insulating film is deposited on a lower wiring film made of aluminum or an alloy thereof, and an interlayer connection hole communicating with the lower wiring film is opened at a predetermined position of the insulating film. a metal embedding step in which a metal fluoride gas is annulated and a metal film made of the reduced metal is selectively deposited in the interlayer connection hole; In the method of manufacturing a semiconductor device, the method includes an upper layer forming step of forming an upper layer wiring portion electrically connected to the lower layer wiring film through a film on the insulating film, the contact hole forming step Subsequently, an implantation step is added to form a silicon implantation layer by implanting silicon ions into the surface of the lower wiring film exposed in the interlayer connection hole, and in the metal embedding step, the silicon implantation layer is The method is characterized in that the metal film is deposited on the lower layer wiring film via the metal film.

[Effect]

Through the implantation process, a silicon implantation layer is formed on the surface of the lower wiring film exposed within the interlayer connection hole. Thereafter, in a metal embedding step, a metal film obtained by reducing the metal fluoride gas is selectively deposited on the lower wiring film via this silicon injection layer.

That is, volatile silicon fluoride is selectively formed by the silicon injection layer, and the above-mentioned nonvolatile and insulating aluminum fluoride ξ, which is formed when a metal film is directly deposited on the underlying wiring film, is formed. is not born.

〔Example〕

Hereinafter, the present invention will be explained based on examples.

FIG. 1 is a sequential cross-sectional view of the manufacturing process of a semiconductor device showing an embodiment of the manufacturing method of the present invention.

Refer to FIG. 1(a) For example, a first layer of Al having a predetermined pattern is formed on a silicon (Sl)W plate l on which predetermined elements (not shown) such as MoSFETs are formed, with a silicon oxide-based insulating film 2a interposed therebetween. The wiring film 3 was formed. Note that the insulating film 2a is an AN wiring-Si
This is an insulating film between the eyebrows that electrically insulates and separates the substrates. In addition, the Al wiring film is usually formed by sputtering Af/St.
A film is deposited and formed into a predetermined pattern through photolithography and etching steps.

Further, a contact hole is provided in the insulating film 2a to electrically connect the element formed on the substrate l and the Al wiring film 3 (not shown). Note that the aspect ratio of the contact hole also increases as devices become smaller, and the thickness of the Al sputter-deposited in the contact hole becomes extremely thin inside, causing problems such as wire breakage and deterioration of reliability due to electromigration. . Therefore, the known W
A W film was selectively deposited only on the exposed portion of the Si substrate in the contact hole by tungsten (W) selective CVD using Fb gas, and then the Aj2 wiring film 3 was formed.

A silicon oxide-based insulating film 2b is deposited on the first-layer Al wiring film 3 by the CVD method, and then a resist 8 having a pattern between the eyebrows is formed at the location where the connecting hole between the eyebrows is planned to be formed in the insulating film 2b. Apply. Then, using the resist 8 as a mask, the insulating film 2b is
An interlayer connection hole 9 was formed by etching.

Refer to FIG. 1(C) Here, a W film is selectively formed in the interlayer connection hole 9, but if the W film is deposited directly on the exposed first layer AA wiring film 3 as described above. , insulating and nonvolatile aluminum fluoride ξ (Aj!F3) is formed during the initial deposition process, resulting in an increase in contact resistance.

Therefore, using the resist 8 used for forming the interlayer connection hole 9 as a mask, silicon (St) ions are implanted to form a high concentration Si implantation layer 7 in the first layer wiring film 3.

After removing the reference resist 8 shown in FIG. 1(d), the WF. W film 5 is formed in interlayer connection hole 9 by tungsten selective CVD method using gas.
selectively deposits.

Since the Al wiring film 3 at the bottom of the interlayer connection hole has a St implantation layer 7 formed by implanting St ions, silicon fluoride (SiF4), which has a lower bio-free energy than the aforementioned aluminum fluoride (AlF), is formed. ) are selectively produced. Note that this S i F4 is volatile and does not remain at the contact interface. Therefore, at the beginning of the deposition of the W film 5, the deposition proceeds only by the reduction reaction of the ion-implanted St, and nonvolatile and insulating aluminum fluoride (AfF.) is not generated.

Furthermore, since the Si in the Si injection layer 7 is consumed by the reduction reaction of Sl at the initial stage of W film deposition, the composition of the St injection layer 7 changes before and after the W film 5 is deposited.

Note that if St is not sufficiently consumed by the reduction reaction,
This implanted Si causes W) 115 and Af wiring I.
f! Although reducing the contact resistance at the l3 interface is suppressed, the ion implantation conditions ( There is no problem as long as the acceleration voltage and dose are selected. Once the exposed portion of the A1 wiring film 3 at the bottom of the interlayer connection hole 9 is covered with the W film, fluorine (F) and Al straw (A/!) will not react directly.

After that, H2 reduction reaction or SiH.
A W film 5 is deposited by the reduction reaction.

Referring to FIG. 1(e), a second layer of An wiring film 4 is formed. As in the step shown in FIG. 1(a), an Al.Si film was deposited by sputtering and shaped into a predetermined wiring pattern by photolithography and etching.

Thereafter, an insulating film for vancivation was applied, and a bonding pad was formed (not shown).

As mentioned above, in this example, the first layer A is formed by ion implantation.
Since the Si injection layer 7 is formed on the n-wiring nQ 3 and the W film 5 is deposited on it, volatile silicon fluoride (S I F4) is selectively used at the beginning of the W film deposition. Raw, non-volatile and insulating aluminum fufluoride (A2F3)
will never be born. Further, the ion-implanted Si is consumed by a reduction reaction. Therefore, the contact resistance at the interface between the Affi wiring film and the W film can be reduced.

Furthermore, in the case shown in FIG. 2, two additional steps (deposition and etching of a Harrier layer) are required to form the barrier layer 6, but in this embodiment, only one step of ion implantation is added. A multilayer wiring technology that reduces contact resistance can be provided.

Further, in the case shown in FIG. 2, since the barrier layer 6 exists on the lower layer A2 wiring film 3, An! &! The resistance value per unit cross-sectional area of the wire film 3, that is, the sheet resistance value increases.

However, according to this embodiment, the Al wiring film 3 can be manufactured without increasing the resistance value per unit cross-sectional area.

In addition, in the step shown in FIG. 1(d), the interlayer connection hole 9
Since the A1 wiring is completely buried with W to flatten the surface, the A1 wiring is made of two layers in the first embodiment, but it is possible to make it three layers,
It is also easy to create four layers. moreover. , an interlayer connection hole 9 can be provided directly above the contact hole (not shown) with the Si substrate 1, and an interlayer connection hole with the upper layer wiring can be provided directly above the contact hole 9, and the connection area can be reduced.

Note that, as mentioned above, it is not necessarily necessary to completely fill the interlayer contact hole with W, but if W is deposited to some extent and the aspect ratio of the interlayer contact hole is reduced, the reliability of the AN wiring can be prevented from decreasing. In that case, as is well known, it is preferable to set the film thickness of each film to be thicker toward the upper layer, taking into consideration surface irregularities and steps.

In the above embodiment, selective CVD of tungsten (W) is performed in the step shown in FIG. It may be something.

Further, in the various embodiments described above, the present invention is applied between the A1 wiring layers, but it goes without saying that it can also be applied to bonding pad types, for example.

〔Effect of the invention〕

As described above, in the present invention, by simply adding an implantation step of implanting silicon ions into the surface of the underlying wiring film exposed in the interlayer connection hole, the non-volatile and insulating aluminum fluoride immersion method that increases contact resistance can be used. Generation can be prevented. That is,
An excellent effect is that contact resistance can be lowered by adding only one process.

Further, in the present invention, since the barrier layer is not particularly shaped, there is an excellent effect that the resistance value per unit cross-sectional area of the lower wiring film does not increase due to the barrier layer shape.

[Brief explanation of drawings]

FIGS. 1(a) to (8) are sectional views in the order of manufacturing steps showing an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a semiconductor device according to a conventional manufacturing method. l... silicon substrate, 2a, 2b... interlayer insulating film,
3... Lower N (first layer) Af wiring film, 4... Upper layer (second layer) AN wiring film, 5... Embedded metal film, 6...
Barrier layer, 7... St injection layer, 8... Resist, 9
...Interlayer connection hole.

Claims (2)

[Claims] (1) A contact hole forming step of depositing an insulating film on a lower wiring film made of aluminum or its alloy, and opening an interlayer contact hole communicating with the lower wiring film at a predetermined position of the insulating film, and metal fluoride. a metal embedding step in which a metal film made of the reduced metal is selectively deposited in the interlayer connection hole by annularizing the gas; In the method for manufacturing a semiconductor device, the method includes an upper layer forming step of forming an electrically connected upper layer wiring portion on the insulating film, and subsequent to the connecting hole forming step, the upper layer wiring portion is exposed in the interlayer connecting hole. An implantation step is added to form a silicon implanted layer by implanting silicon ions into the surface of the lower wiring film, and in the metal embedding step, the metal film is deposited on the lower wiring film via the silicon implanted layer. A method of manufacturing a semiconductor device, characterized in that: (2) The metal fluoride gas is WF_6 gas or Mo
2. The method of manufacturing a semiconductor device according to claim 1, wherein F_6 gas is used and the metal film is W or Mo.