JPH0682663B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in an interlayer connection method for Al multi-layer wiring required in a submicron standard VLSI or the like.

[Conventional technology]

As device miniaturization progresses, the width of Al (or its alloy, simply referred to as Al hereinafter) wiring is becoming smaller, and the aspect ratio (hole depth / closed area) of the interlayer connection hole that connects the upper and lower layers of Al multilayer wiring However, it is not possible to cope with the increase in the size), and the reliability of the wiring is reduced, which causes problems in wiring technology.

Therefore, as a new wiring technique, a method of selectively forming a metal such as tungsten (W) or molybdenum (Mo) in the interlayer connection hole by CVD has been proposed, and a geometrical shape related to the wiring as described above is proposed. It is receiving attention as a promising method for solving problems.

However, when connecting the Al multi-layered wirings with these metals such as W and Mo, the fluorine (F) generated when the source gas (WF ₆ , MoF ₆ ) decomposes reacts with the lower layer Al wirings and insulates in the initial stage of deposition. Form non-volatile and non-volatile aluminum fluoride (AlF ₃ ),
There is a problem that the contact resistance becomes very high.

In view of the above problem, as shown in FIG. 2, the first-layer Al wiring film 3
There is a method of lowering the contact resistance by drawing a MoSi ₂ or TiSi ₂ barrier layer 6 on the surface of the.

This is because the exposed part in the interlayer connection hole of the underlying wiring layer is MoSi
_Since it is ₂ or TiSi ₂ , the reduction reaction of the source gas by Mo or Ti does not occur, and the deposition proceeds only by the reduction reaction of Si at the initial stage of W or Mo deposition, and the reaction by-product (AlF _This is because ₃ ) does not occur.

In FIG. 2, 1 is a Si substrate, 2a and 2b are interlayer insulating films, 3 is a lower Al wiring film, 4 is an upper Al wiring film, 5 is a buried metal (W, Mo, etc.) for interlayer connection, 6 is a barrier layer.

[Problems to be Solved by the Invention]

However, in the case of manufacturing the above structure, in order to form the barrier layer 6 for reducing the contact resistance, two steps of depositing the barrier layer 6 and etching are inevitably added. That is, the number of steps increases as the number of layers increases. Further, if the barrier layer deposition thickness is taken into consideration, the thickness of the lower Al wiring film becomes thin by that thickness, and the resistance value per unit cross-sectional area of the Al wiring film 3 increases. Become.

In view of the above problems, the present invention provides a method for manufacturing a semiconductor device which can reduce the contact resistance by adding only one step and which does not increase the resistance value per unit cross-sectional area of the lower Al wiring film. The purpose is to

[Means for Solving the Problems]

In order to achieve the above-mentioned object, the present invention is such that an insulating film is deposited on a lower layer wiring film made of aluminum or its alloy, and an interlayer connecting hole communicating with the underline wiring film is opened at a predetermined position of the insulating film. A hole forming step; a metal embedding step of reducing the metal fluoride gas to selectively deposit a metal film made of the reduced metal in the interlayer connection hole; and a metal film in the interlayer connection hole. A method of manufacturing a semiconductor device, comprising: an upper layer forming step of forming an upper layer wiring part electrically connected to the lower layer wiring film via the upper layer forming step on the insulating film; An implantation step of ion-implanting silicon to form a silicon-implanted layer is added to the surface of the lower-layer interconnection film exposed in the interlayer connection hole, and in the metal burying step, the lower-layer interconnection film is formed through this silicon-implanted layer. On top Characterized by being adapted to deposit a metal film.

[Action]

By the implantation process, a silicon implantation layer is formed on the lower wiring film surface exposed in the interlayer connection hole. Then, in a metal burying step, a metal film obtained by reducing the metal fluoride gas is selectively deposited on the lower wiring film through the silicon injection layer.

That is, volatile silicon fluoride is selectively formed by the silicon injection layer, and the above-mentioned non-volatile and insulating aluminum fluoride that is generated when a metal film is directly deposited on the lower wiring film is not generated. .

〔Example〕

 Hereinafter, the present invention will be described based on examples.

FIG. 1 is a sectional view of a semiconductor device in the order of manufacturing steps showing an embodiment of the manufacturing method of the present invention.

See FIG. 1A. For example, a first-layer Al wiring having a predetermined pattern on a silicon (Si) substrate 1 on which a predetermined element (not shown) such as MOSFET is formed via a silicon oxide insulating film 2a. The film 3 was formed. The insulating film 2a is an interlayer insulating film that electrically insulates and separates between the Al wiring and the Si substrate. Further, the Al wiring film is usually formed by depositing an Al.Si film by sputtering, and is formed into a predetermined pattern through photolithography and etching steps.

A contact hole is formed in the insulating film 2a to electrically connect the element formed on the substrate 1 and the Al wiring film 3 (not shown). The aspect ratio of the contact hole also becomes larger with the miniaturization of the device, and the film thickness of Al sputter-deposited in the contact hole becomes extremely thin inside the contact hole, causing problems such as disconnection or reliability deterioration due to electromigration. . Therefore, the W film is selectively deposited only on the exposed portion of the Si substrate of the contact hole by the tungsten (W) selective CVD using the known WF ₆ gas,
After that, the Al wiring film 3 was formed.

See FIG. 1 (b). A silicon oxide type insulating film 2b is deposited on the first-layer Al wiring film 3 by a CVD method, and then a resist 8 having an opening pattern at a position where the insulating film 2b is to be formed with an interlayer connection hole. Apply.
Then, the insulating film 2b was etched using the resist 8 as a mask to form the interlayer connection hole 9.

See FIG. 1C. Here, although the W film is selectively formed in the interlayer connection hole 9, the W film is directly formed on the exposed first Al wiring film 3 as described above.
When the film is deposited, insulative and non-volatile aluminum fluoride (AlF ₃ ) is formed in the initial stage of the deposition, and the contact resistance increases.

Therefore, silicon (Si) is ion-implanted using the resist 8 used for forming the interlayer connection hole 9 as a mask to form a high-concentration Si-implanted layer 7 in the first-layer Al wiring film 3.

After removing the resist 8, the W film 5 is selectively deposited in the inter-layer connection hole 9 by the tungsten selective CVD method using WF ₆ gas, as is known in the art.

The Al wiring film 3 at the bottom of the interlayer connection hole is formed by Si ion implantation.
Since the Si implantation layer 7 is formed, silicon fluoride (SiF ₄ ) having a lower generation free energy than that of aluminum fluoride (AlF ₃ ) is selectively generated. This SiF ₄ is volatile and does not remain at the contact interface. for that reason,
At the initial stage of deposition of the W film 5, the deposition proceeds only by the reduction reaction of ion-implanted Si, and non-volatile and insulating aluminum fluoride (AlF ₃ ) is not generated. Further, since Si in the Si implantation layer 7 is consumed by the reduction reaction of Si at the initial stage of W film deposition, the composition of the Si implantation layer 7 changes before and after the deposition of the W film 5.

If Si is not sufficiently consumed by the reduction reaction, it is suppressed that the injected Si reduces the contact resistance at the interface between the W film 5 and the Al wiring film 3.
There is no problem if the ion implantation conditions (accelerating voltage, dose amount) are selected so that the W film has a necessary and sufficient amount of Si for covering the exposed portion of the Al wiring film 3 at the bottom of the interlayer connection hole 9. Once the exposed portion of the Al wiring film 3 at the bottom of the interlayer connection hole 9 is covered with the W film, fluorine (F) and aluminum (Al) will not directly react.

After that, the W film 5 is deposited by the H ₂ reduction reaction or the SiH ₄ reduction reaction as usual.

See FIG. 1E. The second layer Al wiring film 4 is formed. Similar to the step shown in FIG. 1A, an Al.Si film was deposited by sputtering and formed into a predetermined wiring pattern by photolithography and etching.

After that, an insulating film for passivation was deposited and a bonding pad was formed (not shown).

As described above, in this embodiment, the first layer Al is formed by ion implantation.
Since the Si injection layer 7 is formed on the wiring film 3 and the W film 5 is deposited thereon, volatile silicon fluoride (SiF ₄ ) is selectively generated at the beginning of the W film deposition, Non-volatile and insulating aluminum fluoride (AlF ₃ ) is not produced. The ion-implanted Si is consumed by the reduction reaction. Therefore, the contact resistance at the interface between the Al wiring film and the W film can be reduced.

In addition, in the structure shown in FIG. 2, it is necessary to add two steps (deposition and etching of the barrier layer) to form the barrier layer 6, but in this embodiment, only one step of ion implantation is added, and the contact is made. It is possible to provide a multi-layer wiring technology that reduces resistance.

Further, in the structure shown in FIG. 2, the barrier layer 6 is the lower Al wiring film 3
Since it exists above, the resistance value per unit cross-sectional area of the Al wiring film 3, that is, the sheet resistance value increases. But,
According to this embodiment, the Al wiring film 3 can be manufactured without increasing the resistance value per unit cross-sectional area.

In the step shown in FIG. 1D, the interlayer connection hole 9
Since W is completely filled with W to flatten the surface, the Al wiring has two layers in the above-described embodiment, but it is easy to form three layers or four layers. Further, the interlayer connection hole 9 can be provided directly above the contact hole (not shown) with the Si substrate 1, and further, the interlayer connection hole with the upper layer wiring can be provided immediately above the contact hole, and the connection area can be reduced.

Note that it is not always necessary to completely fill the interlayer connection hole with W as described above, and the reliability of the Al wiring can be prevented from being lowered by depositing it to some extent to reduce the aspect ratio of the interlayer connection hole. In that case, as is well known, the film thickness of each film may be set thicker toward the upper layer in consideration of surface irregularities and steps.

In the above embodiment, the selective CVD of tungsten (W) is performed in the step of FIG. 1D, but not limited to W, for example, molybdenum (Mo) is selectively deposited. May be

Further, although the present invention is applied between the Al wiring layers in the various embodiments described above, it is needless to say that the present invention can be applied, for example, when forming a bonding pad.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the generation of non-volatile and insulating aluminum fluoride that increases the contact resistance by the implantation step of ion-implanting silicon into the surface of the lower wiring film exposed in the interlayer connection hole. That is, there is an excellent effect that the contact resistance can be reduced by preventing the generation of aluminum fluoride without providing the step of providing the barrier layer.

Further, in the present invention, since the barrier layer is not specially formed, there is an excellent effect that the resistance value per unit cross-sectional area of the lower wiring film does not increase due to the formation of the barrier layer.

[Brief description of drawings]

1A to 1E are cross-sectional views in order of manufacturing steps showing one embodiment of the present invention, and FIG. 2 is a sectional view showing a structure of a semiconductor device by a conventional manufacturing method. 1 ... Silicon substrate, 2a, 2b ... Interlayer insulating film, 3 ... Lower layer (first layer) Al wiring film, 4 ... Upper layer (second layer) Al wiring film, 5 ...
… Embedded metal film, 6 …… Barrier layer, 7 …… Si injection layer, 8 ……
Resist, 9 …… Interlayer connection hole.

Claims (2)

[Claims] 1. A connecting hole forming step of depositing an insulating film on a lower wiring film made of aluminum or an alloy thereof and opening an interlayer connecting hole communicating with the lower wiring film at a predetermined position of the insulating film. A metal embedding step of reducing the metal oxide gas and selectively depositing a metal film made of the reduced metal in the interlayer connection hole; and the lower wiring film through the metal film in the interlayer connection hole. And a step of forming an upper layer wiring portion electrically connected to the insulating film on the insulating film, the method further comprising: exposing the inside of the interlayer connection hole after the connection hole formation step. A step of implanting silicon into the surface of the lower wiring film to form a silicon injection layer is added, and in the metal embedding step, the metal film is formed on the lower wiring film through the silicon injection layer. To accumulate The method of manufacturing a semiconductor device characterized by the. 2. The metal fluoride gas is WF ₆ gas or MoF
_{6. The} method of manufacturing a semiconductor device according to claim 1, wherein the gas is ₆ gas, and the metal film is W or Mo.