JPH0358285A - Method and processor for magnifying and reducing picture - Google Patents

Abstract

PURPOSE:To execute magnification/reduction processing according to the magnification of an arbitrary rational number by fetching a picture element, which is sent out from a first memory by a first clock, into the second memory by the second clock. CONSTITUTION:In order to execute magnification/reduction processing in the process of transfer from a memory 100 to a memory 110, the clocks of various frequencies are generated from a fundamental clock signal by a digital circuit on read and write sides. Namely, in the case of the magnification processing, the second clock is set to the peak operating frequency of the second memory 110 and the first clock is set to a frequency reduced less than the second clock respectively. In the case of the reduction processing, the first clock is set to the peak operating frequency of the first memory 100 and the second clock is set to a frequency reduced less than the first clock respectively. Thus, the magnification is precisely designated over a wide range and the magnification and reduction can be executed. Further, a circuit can be formed by the normal digital circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for enlarging and reducing an image and a processing apparatus therefor, which can perform enlargement and reduction processing at an arbitrary magnification at high speed. [Prior Art] Various methods have been proposed to perform high-speed enlargement/reduction processing of ten images. For example, the Ir image enlargement processor described in Japanese Patent Application Laid-Open No. 64-21681 (hereinafter referred to as Proposal A
Alternatively, there is a ``partial area variable magnification display method'' (hereinafter referred to as proposal B) described in Japanese Patent Laid-Open No. 63-129417. [Problem to be solved by the invention] In the above proposal A, by handling multiple bits at once, the expansion process is performed by a factor of N/n (here, N is a fixed positive number) at high speed. , N stages of magnification can be specified. That is, one column is a, b, c, d, e, f・
By repeatedly outputting each bit of a line consisting of a plurality of bits of .
, Ce a, dle, e, f, f, ... to double the line length, or to triple the line length by increasing each bit to 3 or 4. This is a method of enlarging each image by a factor of .5. However, this method requires a large logic circuit such as a barrel shifter, and the conversion speed changes depending on the enlargement ratio. For example, in 2x enlargement processing, the speed becomes as low as in bit-by-bit processing. Further, in the above proposal B, by independently setting the address scanning frequency of the image memory, it is possible to independently control the enlargement/reduction ratio inside and outside the window. For example, in the process of reducing a map and enlarging or resizing symbols to the same size, the reading speed of the original image memory is made variable. However, in this method, because the frequency is set relative to the scanning speed of the C,RT display device, for example,
Considerable high-speed operation is required. Therefore, there may be cases where digital circuits such as ordinary memories and counters cannot cope with this. For example, in workstations such as offices, in order to smoothly zoom documents including drawings, images with different scaling ratios are generated in a short time of 0.1 seconds or less.
This needs to be displayed on the screen. In addition, when pasting a drawing, that is, excluding a limited space that occupies a part of a page, and characters are arranged in the remaining part,
In order to enlarge or reduce the image to a size that matches the dimensions of the blank space and fit it there, enlargement/reduction processing is required in fine steps of 1/1000. The purpose of the present invention is to solve these conventional problems, to enlarge and reduce images by specifying detailed magnification over a wide range, and to be able to enlarge and reduce images using ordinary digital circuits. An object of the present invention is to provide a method and a processing device thereof. [Means for Solving the Problems] In order to achieve the above object, the method for enlarging/reducing an image according to the present invention includes (a) sending out pixels from a first memory at a first clock; A method for enlarging/reducing an image pattern to be imported into a memory using a second clock, wherein in the case of enlarging processing, the second clock is set to the highest operating frequency of the second memory, and the first clock is set to a higher operating frequency than the second clock. Set each to the reduced frequency, and in the case of reduction processing,
The feature is that the first clock is set to the highest operating frequency of the first memory, and the second clock is set to a frequency lower than that of the first clock. Also, (mouth) the first
Among the second clocks, when using a clock whose frequency is lower than that of the other clock, another feature is that the other clock is delayed by a predetermined ratio. (c) When creating a clock with a frequency lower than that of the other clock among the first and second clocks, in order to generate a clock whose frequency is pseudo-reduced with respect to the reference clock, Let the reciprocal of the rational number be an arbitrary rational number, separate the rational number into the value of the integer part and the value of the remainder, and have a length of ゛Ql. which is an integral multiple of the denominator of the rational number.
Another feature is that the reference clocks are thinned out by creating a series of numbers and spacing them by the sum of the value of the integer part and the value of the series. (2) When creating a second clock with a frequency lower than the first clock when the image is small, in the X direction, the reference clock is on the sending side of the solid state, and the thinning is on the receiving side. In the Y direction, a clock with an increased frequency is supplied to the pixel sending side, and a reference clock is supplied to the pixel receiving side. Furthermore, the image smooth zooming method according to the present invention is (e) an image pattern scaling method in which pixels are sent from a first memory at a first clock and pixels are imported into a second memory at a second clock. There it is,
In the case of enlargement processing, the second clock is set to the highest operating frequency of the second memory, and the first clock is set to a frequency lower than that of the second clock. The clock is set to the highest operating frequency of the first memory, and the second clock is set to a frequency lower than that of the first clock, and enlargement/reduction processing is performed continuously, and the clock is continuously reduced. Another feature is that the rate is changed and displayed. Further, the screen enlargement/reduction processing device of the present invention has a first clock that sends out pixels using a first clock.
a second memory that captures pixels at a second clock; and a second memory that captures pixels using a second clock; When reducing the image, the first clock is set to the highest operating frequency of the first memory, and the second clock is set to a frequency lower than the first clock. The feature is that a control circuit is provided to supply the memory. Also,
(g) Another feature is that a shift register is provided in one or both of the sending part of the first memory means and the taking part of the second memory means. [Operation] In the present invention, enlargement/reduction processing is performed in the process of transfer from memory to memory. For this purpose, clocks with different frequencies are generated on the read side and the write side from a basic clock signal by digital circuits. This makes it possible to specify the magnification in fine increments and to perform high-speed conversion processing. For example, if the value after the decimal point of the magnification is set in 512 increments, it is 256K bits, 10
If the interval is 24, each memory of the IM bit can be used for control, so it is possible to smoothly perform drawing insertion processing, zooming display, etc. Further, the conversion speed is not related to the speed of the image memory, and processing can be performed at a pixel rate determined approximately by the operating speed of the shift register, so high-speed conversion processing is possible. Furthermore, since the number of gates in the circuit can be small, the device can be constructed using ultra-high-speed elements. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an image enlargement/reduction processing device showing one embodiment of the present invention. In FIG. 1, 100 is the original II image memory that stores the original image, 110 is the result image memory that stores the enlarged/reduced image, and 120 and 130 are used to change the image by timing control when transferring it to other images. Multiplying shift register, 20
0 is a control circuit that generates a timing signal for scaling processing. Signals for these memories 100, 110 and shift registers 120, 130 include address signals lot, Ill and pixel signal 102 shown by double lines;
There are shift clock and load signals shown as solid lines. That is, 101 is an address signal for the original image memory +00, and +02 is a read pixel signal corresponding to that address. This pixel signal is a signal obtained by reading out n adjacent Akebono lines in parallel. This pixel signal 10
2 is taken into the shift register +20 by the load signal 122. The shift register 120 performs parallel input serial output operation, and receives the shift clock + from the control circuit 200.
In synchronization with 21, the serial signal 123 is sequentially applied to the second
The data is transferred to the shift register 130 of. shift register 1
30 performs serial input parallel output operation, and shift clock 1
A shift operation is performed in synchronization with 31, and the parallel signal 133 is transferred to the resultant image memory 110. With this configuration, even if you use low-cost and low-speed memory, you can still use shift registers! By simply increasing the speed of 20, the serial output signal 123 can be made faster. Now, if the operating ratio of the memory and the shift register, that is, the speed ratio, is nl, the value of the ratio can be set to a value of 4, 8, 16.32, etc. Furthermore, if the width of the shift register 130 is n2, then
The shift register 130 writes the parallel output signal 133 into the result image memory +10 in synchronization with the write pulse 132 every time n2 pixels are aligned. The pixel signal to the resulting image memory 110 is written to the address specified by the address signal ill. The control circuit 200 receives the above-mentioned address signal lot, 111.
, 210 is a read-side control unit which generates shift clocks 121, 131, etc. based on the X clock pulse 211. 21 and it
/ n and the load signal 122 is created. The read-side control unit 21O includes an X address counter 221 that counts based on the X clock pulse 211 and a Y address counter 222 that counts based on the Y clock pulse 212, and together generates the address signal 101 of the memory 100. Next, 230 is a control section on the writing side. This control section 230 includes an X address counter 242 and a Y address counter 241, as on the read side, and uses the shift clock 13 based on the X clock pulse 232 and the Y clock pulse 23l.
1, a write pulse 132 to memory 110, and address signal Ill. Reference numeral 250 in the control section 200 is a clock pulse switching circuit that inputs the pulses generated by the clock generation circuit and switches to various clock pulses used on the output side. As mentioned above, when enlarging, the reference clock is supplied to the writing side, and a thinned-out clock is supplied to the reading side, but when scaling down, the reference clock is supplied to the reading side, and a thinned-out clock is supplied to the writing side. , respectively. The clock pulse switching circuit 250 is a switching circuit for switching this supply in the opposite direction. 300 in the control unit 200 is a clock generation circuit that generates two types of clocks with different frequencies for each of X and Y. Details of the clock generation circuit 300 will be described with reference to FIG. FIG. 2 is a block diagram of main parts of the switching circuit and clock generation circuit in FIG. 1. The switching circuit 250 includes four signal selectors 251, 2
It consists of 52, 253, 254. The outputs of these signal selectors 251 to 254 are X clock pulse 211% Y clock pulse 21 on the read side.
2. X clock pulse 232 and Y clock pulse 231 on the writing side. These signal selectors 251-2
54 are switched all at once by an instruction signal 202 indicating whether to enlarge or reduce. When enlarging, signal selector 2
51 is the reduced frequency clock 313 of X, the signal selector 252 is the reference clock 311 of X, and the signal selector 25 is
3 selects the reduced frequency clock 314 of Y, and the signal selector 254 selects the reference clock 312 of Y. On the other hand, during reduction, the opposite selection is made, and the signal selector 25l is set to the reference clock 31 of X.
1, the signal selector 252 selects the reduced frequency clock 3 of
13, the reference clock 312 whose signal selector 253 is Y
, the signal selector 254 selects Y's reduced frequency clock 3l
4, respectively. Next, the clock generation circuit 300 in FIG. 2 is shown as an example including frequency generators 301 and 302 that generate two types of clocks.The 6-frequency generator 301 transfers its oscillation frequency to the shift register 120. or set to the highest operating frequency F of 130. If α is the reciprocal of the expansion rate or reduction rate for the frequency F, then the frequency generator 3
The generation frequency of 02 is αF. 303 is a clock generation circuit that generates the fundamental frequency of these frequency generators 301-302. PLL (Phase Loced L) used for frequency control of broadcast receivers
If oop) control is applied to this circuit, it is possible to generate a frequency that is an integral multiple of the clock generated by the clock generation circuit 304 based on the clock generated by the clock generation circuit 304. For example, if the frequency of the clock generation circuit 303 is 100K}
If {z, α=0.95, the frequency generator 301
, 302 frequencies of 10MHz and 9.5MHz.
It can be set to z. As shown in FIG. 2, the outputs of the frequency generators 13301 and 302 are directly output as the X reference clock 311 and the reduced frequency clock 313. On the other hand, the Y reference clock 312 is divided into l/L by the frequency divider 305 based on the output of the frequency generator 30l, and then
It is output to the clock pulse switching circuit 250. Here, L is a converted prime number in the horizontal direction on the writing side when enlarging, and on the reading side when reducing. The Y low frequency clock 314 is outputted to the clock pulse switching circuit 250 after the output of the frequency generator 1302 is divided into l/L by the frequency divider 306 . FIG. 3 is a diagram showing the operating principle of the image enlargement/reduction processing device of the present invention. Figure 3(a) shows the enlarged 1.4 times, and Figure 3(b) shows the enlarged eggs by 19/8 times.
Figure (C) shows a reduction process of 1/1.4 times. First, in FIG. 3(a), ab of the original image in row A
cd...10 pixels of J are enlarged, and some of the pixels 'li4c+e, h, j are expanded to 2 pixels as shown in the row B, making the total 14 pixels. In this case, while 10 clocks as shown in row C are supplied to the read side, 14 clocks as shown in row E are supplied to the write side. The lines to indicate the number of pixels in the enlarged image for each pixel of the original image in A, where ab is 1x, C is 2x, d is 1x, and e is 2x. shows. In this case, the pixels to be stretched need to be evenly distributed. To do this, use the original image! It is sufficient to sample and capture the signal for 14 pixels within a period of sending out O pixels, and write it into the image memory. To do this, for example, as shown in C, the shift clock 121 is sent to the original image as a clock with a period of 140 ns, and the shift clock 121 is sent to the original image as a clock with a period of 140 ns.
31 can be captured using a clock with a period of IOOns as shown in E. This requires a circuit that generates a clock of any frequency. The second line shows another method, which is based on the clock shown in E and thins it out to create a pseudo clock of 14
This is a method of generating a clock with a period of 0 ns. Time point O shows the decimated clock, and the resulting image is the same. FIG. 3(b) shows the 2,375 times enlargement process using the same symbols as in FIG. 3(a), and the same symbols indicate the same methods. In this case, the lIi element of the original image is 2 or 3i! It has been extended to 11. That is, the 8 pixels (a to h) shown in A are expanded to 2 or 3 pixels as shown in B, increasing to a total of 191i1 pixels. In this way, as is clear from FIGS. 3(a) and 3(b), there are at most two types of pixels in the enlarged image corresponding to one pixel of the original image even in enlargement processing at any magnification. That is, in (a) there are two types, 1x and 2x, and in (b), 2x and 3x. These values are two integer values sandwiching the magnification rate. In other words, in (a) it is 1.4 times, so it is the value of l and 2 that sandwich this value, and in (b) it is 2, 3
Since it is 75 times, the values are 2 and 3 that sandwich this value. Therefore, in the information on , the value of the integer part of the magnification ratio is replaced with the sequence of 0, l shown in (g). for example,
In the case of (a), 1.4 times is an integer part l and the remainder is 2/5, so the information in g is a sequence formed by two l and the remaining O with a period of 5. ．． In case (b),
The integer part of 2.375 is 2 and the remainder is 3/8, so
It is expressed as a number sequence formed by three 1's and the remaining 0 with a period of 8. In principle, for rational numbers greater than or equal to 1. There is a sequence of numbers with periodic integer values and denominators as described above. Note that, in practice, a power of 2 is selected as the denominator number in consideration of the efficiency of storing the sequence. FIG. 3(c) shows a case where 5/7 times reduction processing is performed. The 7 pixels of abc...g of the original lli image are:
As shown in the mouth, d and g are omitted, resulting in 5 pixels. In order to obtain such a result, it is sufficient to send out the pixel A with a clock having a period of 100 ns, and sample and capture it with a clock having a period of 140 ns. In addition, as another method, it is also possible to use a thinned-out clock as shown in (E) for the basic clock shown in (2). this is,
This is the same as the signal shown in 2 in case (a). is the number of corresponding pixels of the original image seen from each pixel of the mouth, and is a sequence of numbers with a period of 5. In other words, what is output as a sequence of 1 vs. 1 is a sequence of 1, and what is output as a sequence of 2 vs. 1 is a sequence of 2. This sequence can also be expressed as a sequence of II numbers l and 0, as shown in g. That is, in the case of reduction processing, the reciprocal of the reduction ratio can be taken to obtain the same sequence of integer values as in the case of enlargement processing, and a shift clock can be generated based on this sequence. Note that the reduction rate can be any rational number less than or equal to 1. However, for the same reason as mentioned above, the numerator is a power of 2,
It is also desirable that the number be the same as the number used for expansion. For example, when collecting l024, N/1 when enlarged.
An enlargement ratio of 0.024 is obtained, and a reduction ratio of 10247N (both N=any integer greater than or equal to 1025) is obtained when reduced. The Glock generation circuit 300 in FIG. 2 generates an analog clock on the time axis shown in C and H in FIG. In this case, although the configuration shown in FIG. 2 is simple, the shift register 130 may sample and take in data at unstable timings when the output of the shift register 120 switches. However, in the case of an image, no matter which pixel of 0.1 the image at the boundary point becomes, it will not be affected much, so unstable operation at the boundary point is considered to be no problem. Furthermore, according to the general idea, the Y low frequency clock 314 in FIG. 2 is output independently of the The line to be read and written changes with . Furthermore, in the case of reduction processing, the thinned-out Y low frequency clock 314 is supplied to the writing side, and the Y reference clock 311 is supplied to the reading side, so that in the thinned-out row, the reading row is switched. However, writing continues without changing the writing line, and as a result, in the image memory 110, writing is redundantly performed at the same location, which is wasteful. However, in another embodiment, measures are taken to prevent such a situation from occurring. 4 is a diagram showing a combination of clocks supplied to the read/write control section of FIG. 1, and FIG. 5 is a timing chart showing an example of the Y-axis clock signal corresponding to FIG. 4. . First, a method for preventing duplicate writing from occurring during reduction will be explained with reference to FIGS. 4 and 5. Figure 4 (a
) shows a method of supplying clocks to the read side and write side during enlargement processing, Fig. 4(b) shows a method of supplying clocks during reduction processing, and Fig. 4(C) shows an improved method of supplying clocks during reduction processing. It shows. The arrow indicates a reference pulse, the white circle on the arrow indicates a pulse that has been thinned out, and the black circle on the arrow indicates an added pulse. First, during enlarging, as shown in Figure 4(a), the read side supplies a reduced glock (thinned pulse) for both X and Y, and the write side supplies a reference clock (reference pulse) for both X and Y. supply This ensures that the writing side is scanned at maximum speed and without overlap, so no wasted processing is performed. next,
At the time of reduction, in the case of FIG. 4(b), on the reading side,
A reference clock (reference pulse) is supplied to both Y and X, and a reduced clock (thinned pulse) is supplied to both X and Y on the write side. In this case, the reading side will operate at the highest speed. However, since it is difficult to thin out and extract a plurality of pixels on the X-axis on the read side, it is unavoidable that the write side does not operate at the maximum speed. On the other hand, regarding the Y-axis on the writing side, the thinned out pulse clock is supplied, so that data is written redundantly. In this case, since the thinned out pulses are supplied once per row, there is room for improvement. FIG. 4(C) shows a method that improves the above-mentioned points in FIG. 4(b). For the X-axis, the clock supply method is the same as in (b), but for the Y-axis, the write side outputs one pulse for l rows, and the read side outputs additional pulses to match the ratio of numbers. In other words, instead of supplying a reference clock to the read side and a thinned-out pulse clock to the write side, by supplying fixed pulses to a specific position on the read side, the added pulse clock on the read side can be transferred to the write side. A reference pulse clock is supplied to each. In this case, at the joint of scans in the X direction,
It is sufficient to send multiple clocks to the reading side all at once. In Fig. 5(a), (b), and (c), Fig. 4(a) respectively
(b) shows the supply timing of the Y-axis clock corresponding to (c). In FIG. 5(b), since the thinned out pulses are supplied to the write side, the same pixels as the previous row are written in the thinned out row in duplicate.
In FIG. 5(C), since the reference pulse is supplied to the writing side, there is no need to worry about duplicate writing. In this case, as shown by a clock 212, on the reading side, 2 pulses are supplied every other time. FIG. 6 is a diagram showing the internal structure of the read control section 210 and write control section 230 in FIG. 1. In the read control unit 210, the input clock pulse 21+ is sent out as it is as the shift clock 122. The load signal 121 is generated by dividing the input clock pulse 211 into I/nl by a frequency divider 2+4.The ax address counter 221 counts based on the output of the frequency divider 214. Further, the Y address counter 222 counts the Y input clock pulses 212. The input signal 201 is a start pulse for processing, and by inputting this signal, the value of the initial value register 216 of the Y address is taken into the counter 222. Also, in the OR circuit 217, the start pulse 201 and Y
The input clock pulse 212 is logically summed to initialize the X address counter 221 and the frequency divider 214. Furthermore, 218 is a delay element that provides a delay in order to perform pixel alignment at the beginning of the row. In other words, when sending nl pixels from the original image memory 1oo to the shift register 120, in order to start from the middle S pixel, the first s-
All you have to do is shift out the pixel number 1 and discard it. In that case, the value of s-1 is obtained by taking the lowest part of the X initial value register 215. For each row, a start signal 2l3 is sent to the write control unit 230 after s-1 clocks have elapsed. The write control section 230 has almost the same function as the read control section 210. The shift clock 131 uses the X input clock pulse 231 as is. The write pulse 132 is generated by dividing the X input clock pulse 231 by a frequency divider 234 to l/n 2. The X address counter 241 counts based on the output of this frequency divider. The activation signal 213 initializes the frequency divider 234 to
The value of the initial value register 235 is taken into the address counter 241. The Y address counter 242 takes in the value of the initial value register 236 with the start pulse 201 and counts the Y input clock pulses 232. In the write control unit 230, a 6x end determination circuit 237 that determines the end of each process for X and Y detects the end value register 23 by observing the value of the X address counter 241.
When a pulse is issued in accordance with the value of 8, the X end signal 2
38 is sent. By observing the value of the Y address counter 242, the Y end determination circuit 239 sends out a Y end signal 243 when the pulse 232 is output in agreement with the value of the end value register 240. A flip-flop 244 indicates that the process is in progress, and is set by the star l pulse 201 and reset by the Y end signal 243. The output value 233 from the flipflop 244 is sent to the clock generation circuit 300. The above is the read control unit 210 and write control unit 230.
This is an explanation. FIG. 7(a) is an overall block diagram of the clock generation circuit in FIG. 1, and FIG. 7(b) is a block diagram of the pseudo variable frequency clock generation circuit in FIG. 7(a). As shown in FIG. 7(a), the clock generation circuit 300 is composed of a basic clock oscillator 320 and two pseudo variable frequency clock generators 310. One of the pseudo variable frequency clock generators 310 is for the X-axis and the other for the Y-axis. The frequency of the base clock oscillator 320 is set to the highest speed at which the circuit will operate. Basic clock oscillator 3
Outputs 321 from 20 are input to two pseudo variable frequency clock generators 310, respectively, and an operation enable signal 32 is also input to the pseudo variable frequency clock generators 310.
3, the output 233 of the flip-flop 244 shown in FIG. 6 is used for the X-axis, and the X end signal 238 shown in FIG. 6 is used for the Y-axis. Outputs 311 and 313 from the pseudo variable frequency clock generator 310 for the X axis are sent to the clock pulse switching circuit 250, and outputs 312 and 314 from the pseudo variable frequency clock generator 310 for the Y axis are also sent to the clock pulse switching circuit 250. It will be done. FIG. 7(b) is a detailed configuration diagram of the pseudo variable frequency clock generator in FIG. 7(a). The system basic clock 321, which is the output of the basic clock oscillator 320, is the output of the pseudo variable frequency clock generator 310.
is fed into the circuit 310 by being gated by the operation enable signal 323 at the OR gate 322 at the entrance of the other pseudo variable frequency clock generator 3 ]
Also sent to 0. 324 is a memory that stores the thinning pattern shown in 2 of FIG. 3(a). The capacity of this memory 324 is, for example, 1024 for one pattern.
Since 1024 bits are prepared, an IM bit is required. One pattern is read m bits at a time from the thinning pattern memory 324 and set in the shift register 325. Here, m is a value necessary to absorb the difference in operating speed between the memory 324 and other circuits. One pattern is 1024 bits, m
=8, it will be sent out every 128 times. The shift clock of the shift register 325 is provided by this circuit 3.
Clock pulse 313 or 314 which is the output of 10
It is. This shift clock is converted to 1/m by the frequency divider 326.
The frequency is divided into an update pulse 327. Update pulse 3
27 serves as a data capture pulse for the shift register 325 and a clock for the address counter 328 of the memory 324. The address counter 328 takes in the value of the start address register 329, which is determined according to the value below the decimal point of the scaling ratio, every l cycles. If the magnification increments are fixed, the pattern is supplied as described above. If it is desired to perform scaling processing using an arbitrary rational number, a pattern thereof is generated and written in the thinning pattern memory 324. On the other hand, if the maximum value used as the integer part of the reciprocal of the enlargement rate or reduction rate is N, and the value at each time is S, then the value S
is set in register 330. Decoder 331 sends 'bi' to one of the output lines 332-i in accordance with the value S. The shift register 333 performs a shift operation using the output clock of the AND gate 322 which is gated with the basic clock 321 using the operation permission signal 323 . When 'l' is input to the shift register 333, it is transmitted to the next bit every time the output clock of the AND gate 322 is input. Since the signal passes through the AND gate 334-i where the output 332-i of the decoder 331 is 1, the signal passes through the OR gate 336 and reaches the AND gates 337 and 338. When this point is reached, if the signal 339 at the output terminal of the shift register 325 is i 0 +, the gate 33
8 passes, and the output signal 341 becomes 'l' via the OR gate 340. When the signal 34l becomes 1°, the output side of the AND gate 340 is connected to the AND gate 342.
Since the basic clock is sent to the input side of the gate 342
to supply output 313 or 3l4 and advance shift register 325 by one. The output signal 341 is sent from the output side of the OR gate 340 to the manual side of the shift register 333, so that it is inputted into the shift register 333 again and follows the same process as described above. As a result, when the output signal 339 of the shift register 325 is 1 () T , the ■ bits of the shift register 333 form a loop, and the output signal 341 has an interval of l clocks. When the output signal 339 is ``l'', a flip-flop 341 is further added to the loop, and an interval of I+l clocks is increased. That is, as shown in FIG. 3(a) or (b)-2, a thinned out clock is output. In the circuit of FIG. 7(b), in order to generate a clock with a pseudo frequency reduction, first, when reducing the reciprocal of the reduction rate to an arbitrary rational number, for example, 1/2.3 times, , the value of the integer part of the reciprocal rational number 23/10, here 2, is set in the register 330. Then, according to the value, the decoder 33l converts l output lines 332-2 into 11
+ so that only 334-2 of the N gates 334 is allowed to pass through. The shift register 333 has substantially the length of the integer part value (2). In the above case, the remainder is 3/
10, the signal 339 has a period of 10 “O +
A sequence of i-bis containing three ``1''' is sent out, and a clock signal sequence is generated on the reduced frequency side with an interval equal to the sum of 2 in the integer part and O and l in the sequence part. That is, 2222222222 Integer part + OIO0100100 Number sequence of length IO 23223
22322 Pseudo variable frequency clock generator 31 shown in FIG. 7(b) with a total pulse interval of 23
0 is a command for generating the X-axis clock, and in this case, the signal 233 of the write control unit 230 is used as the operation permission signal 323. Furthermore, when using the circuit shown in FIG. 7(b) to generate the Y-axis clock, when reducing the
A clock as shown in FIG. 5(b) is generated. Also,
In order to make the improvement shown in FIG. 5(C), an additional circuit shown in FIG. 8 is added to the Y-axis clock generation circuit 310 of FIG. 7(b). FIG. 8 is a diagram showing an example of an additional circuit of the pseudo variable frequency clock generator. In the circuit of FIG. 8, the signal 238 is
This is a signal that is output for l clocks each time scanning in the X-axis direction is completed at 30. This additional circuit includes a signal selector 351 that is switched by a signal 202 indicating whether to enlarge or reduce.
and 352 are provided. During enlargement, both selectors 351 and 352 operate to select signal 238,
Signal 238 is output as output signals 323 and 314. In this case, the result will be the same even without this additional circuit. In other words, signal 238 has occurred! Only the clock operates the circuit shown in FIG. 7(b). On the other hand, during reduction, the selectors 351 and 352 perform reverse selection operations. That is, the selector 351 selects and outputs the output of the flip-flop 353, and the selector 352 selects and outputs the signal 341, respectively. This flip-flop circuit 353
is a JK type flip-flop, and the system basic clock 321 is used as the clock. signal 23
When 8 is input, flip-flop 3 is input at the next clock.
53 is turned on and sends out an operation permission signal 323. Pseudo variable frequency clock generator 310 shown in FIG. 7(b)
operates at the rate of the system basic clock until it outputs signal 341 and flip-flop 353 turns off. This period includes one or more Y reference clocks 312
and one Y decay clock 314 is output. Since this clock 314 updates the Y address of the write memory, it is possible to ensure that the Y address of the write memory always advances by l in the next scan in the X-axis direction. As described above, in this embodiment, (a) the value after the decimal point of the magnification is set to 256K bits, 102K bits, for example, in increments of 512.
By performing control using the IM bit memory in increments of 4, it is possible to specify the scaling factor with an arbitrary value. Furthermore, it is possible to perform processing at a pixel rate determined only by the operating speed of the shift register, and high-speed conversion processing is possible regardless of the speed of the image memory. (c) Since the number of gates in the circuit can be small, it can be constructed using ultra-high-speed elements. [Effects of the Invention] As explained above, according to the present invention, it is possible to perform scaling processing at any rational number magnification, and it is possible to specify the magnification in fine increments of the wood grain, thereby reducing the work of fitting drawings. can be performed with high precision, and smooth zooming display is also possible. In addition, high-speed processing is possible regardless of the speed of the image memory, and the circuit can be constructed using ultra-high-speed elements.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a scaling processing circuit showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a variable frequency clock generation circuit and a switching circuit in FIG. 1, and FIG. An explanatory diagram of the processing method, FIG. 4 is a diagram of a combination of clocks supplied to the read control section and write control section of FIG. 1, and FIG. 5 is a Y-axis clock signal shown corresponding to FIG. 4. 6 is a diagram showing an example of the configuration of the read control section and write control section in FIG. 1, and FIG. 7 is a diagram showing the configuration of the clock generation circuit and the built-in pseudo variable frequency clock generator in FIG. 1. FIG. 8 is a diagram showing an example of the structure of an additional circuit of the pseudo variable frequency clock generator in FIG. 7. 100: Original image memory, 110: Result image memory, 12
0,130: Shift register, 200: Control circuit, 21
0: Readout control unit, 230: *Writing control unit, 22
1,242:X address counter, 222,241:Y
Address counter, 250: Clock pulse switching circuit,
300: Clock generation circuit, 251-254: Selector, 301-303; Frequency generator, 304: Clock generation circuit, 305, 306: Frequency divider, 214, 234 Frequency divider, 221, 222, 241, 242: X, Y address counter, 216, 236: Initial value register, 2l8:
Delay element, 237: X end determination circuit, 238 End value register, 239: Y end determination circuit, 320: Basic clock oscillator, 31o: Pseudo variable frequency clock generator,
322, 334, 337, 338, 342: Theory Fl! Product gate, 336, 340.217: OR gate, 33
1: Decoder, 333, 325: Shift register, 32
4: Thinning pattern memory, 328: Address counter, 329: Start address register, 353. 341: Flip flop. Representative Patent Attorney Masatoshi Isomura Figure 3 (Part 1) (a) 1.4 times magnification 11111111111 1.11011011101101 111111111111111 (11212) (00101) 10 shots 14 shots from 1O Figure 3 (Part 2) (b) 19A times Enlarged photo 101010010101001010.011111
111111111111111 (22322323) (00100101) Figure 3 (Part 3) (c) ]. //1.4 times reduction d11l1111l11111engineeringho11101101110110 (11212) g(00101) Fig. 5 (a) Enlargement (b) Reduction (c) Reduction (improvement) Ha, 212,, 232 Fig. 6 Fig. 233 Fig. 7 (Part 1) (a) 300

Claims (1)

[Claims] 1. An image pattern enlargement/reduction method in which pixels are sent out from a first memory at a first clock and the pixels are taken into a second memory at a second clock, in the case of enlargement processing. In this case, the second clock is set to the highest operating frequency of the second memory, and the first clock is set to a frequency lower than that of the second clock. 1. A method for enlarging/reducing an image, characterized in that the first clock is set to the highest operating frequency of the first memory, and the second clock is set to a frequency lower than that of the first clock. 2. When creating a clock with a frequency lower than that of the other clock among the first and second clocks,
2. The image enlarging/reducing method according to claim 1, wherein the other clock is thinned out at a predetermined ratio. 3. When creating a clock with a frequency lower than that of the other clock among the first and second clocks,
In order to generate a clock whose frequency is pseudo-reduced relative to the reference clock, the reciprocal of the reduction rate is an arbitrary rational number,
Separate the rational number into the value of the integer part and the remainder value, create a sequence of '0' and '1' whose length is an integer multiple of the denominator of the rational number, and divide the value of the integer part and the value of the sequence. 3. The image enlargement/reduction method according to claim 1, wherein the reference clocks are thinned out at intervals corresponding to the sum of the reference clocks. 4. When reducing the above image, when creating a second clock with a frequency lower than that of the first clock, in the X direction, the reference clock is placed on the pixel sending side and the thinned out clock is placed on the pixel receiving side. 4. The image processing system according to claim 1, wherein, in the Y direction, a clock of increasing frequency is supplied to the pixel sending side, and the reference clock is supplied to the pixel receiving side. How to enlarge/reduce. 5. A method for enlarging/reducing an image pattern in which pixels are sent out from a first memory at a first clock and the pixels are taken into a second memory at a second clock, and in the case of enlarging processing, the second The clock is set to the highest operating frequency of the second memory, and the first clock is set to a frequency lower than the second clock. In the case of reduction processing, the first clock is set to the highest operating frequency of the second memory. The second clock is set to the highest operating frequency of the first memory, and the second clock is set to a frequency lower than the first clock, and enlargement/reduction processing is performed continuously, and the clock is reduced for each processing of one screen. A smooth screen that is characterized by changing the display rate.
Zoom method. 6. a first memory that sends out pixels with a first clock;
a second memory that captures the pixels at a second clock;
When enlarging an image, the second clock is set to the highest operating frequency of the second memory, and the first clock is set to a frequency lower than the second clock. When reducing an image, the second clock is set to a frequency lower than the second clock. the clock at the highest operating frequency of the first memory, and the second clock at the highest operating frequency of the first memory.
An image enlargement/reduction processing device comprising: a control means for setting a frequency lower than the clock of the clock and supplying the frequency to the first and second memories. 7, the sending part of the first memory, and the second
7. The image enlarging/reducing processing apparatus according to claim 6, further comprising a shift register in one or both of the input portions of the memory.