JPH0356497B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a line switching circuit, and in particular, in a digital wireless transmission line that divides digital multiplexed signals into multiple streams and transmits them, the present invention relates to a line switching circuit that is used to switch between working and backup systems. This invention relates to a line switching circuit that performs line switching without bit sequence errors.

(Prior art) In general, in digital wireless transmission lines using multilevel QAM (quadrature amplitude modulation), etc., countermeasures are taken for line maintenance and operation, or fault countermeasures for deterioration of transmission quality due to selective fading in the radio wave propagation path. As such, one backup system is provided for a plurality of active systems, and lines are switched between the active and backup systems in a timely manner in accordance with the above-mentioned measures. Conventionally, line switching circuits that switch between the working system and the backup system have been used for the backup system at the transmitting terminal station.
It is equipped with a means for switching the transmission signals of the working system and the backup system, a received signal distribution means is provided in the backup system on the side of the receiving terminal, and a received signal synchronization switching means is also provided in the working system (Yamago et al.: 4/5 GHz).
Line switching device for 200 Mb/s digital radio system, 1985 National Conference of the Institute of Electrical Communication Engineers, pp8
-46).

Figure 6 is a block diagram showing the main parts of both transmitting and receiving end stations of a digital wireless transmission line using a conventional line switching circuit. This is an example of a case consisting of. In FIG. 6, during normal operation, k systems of digital multiplexed signals are transmitted through branch circuits 31-1 to 31-k, code conversion circuits 34-1 to 34-k, and transmission signal processing circuits 35-1 to 35-k, respectively. 35-k and transmission signal distribution circuit 37
-1 to 37-k, are sent to the receiving end station side via a predetermined modulation transmission system, and at the receiving end station side, the digital signals of each working system are demodulated via a predetermined receiving demodulation system. are frame synchronization circuits 38-1 to 38-k and synchronization switching circuit 40, respectively.
-1 to 40-k, received signal processing circuits 41-1 to 4
1-k, code conversion circuits 42-1 to 42-k, and switching circuits 43-1 to 43-k, and are output to the corresponding digital multiplex conversion terminal equipment. Regarding the standby system, the pilot signal generated in the pilot generation circuit 33 on the transmitting terminal side is transmitted to the switching circuits 32-1 to 32-k, the code conversion circuit 34, the transmitted signal processing circuit 35, and the transmitted signal switching circuit 36. is sent to the receiving end station via a predetermined modulation transmission system, and at the receiving end station,
frame synchronization circuit 38, received signal branch circuit 39,
The signal is input to the pilot detection circuit 44 via the received signal processing circuit 41, the code conversion circuit 42, and the switching circuits 43-1 to 43-k, and is detected.

If the current system is to be switched to the backup system due to maintenance operations of the current system or due to factors such as wireless line failures, for example, in Fig. 6,
The digital signal of the active system that is sent from the transmission signal distribution circuit 37-1 to the transmission signal switching circuit 36 of the backup system is transmitted to the transmission signal switching circuit 36 of the protection system.
In this case, the pilot signal is placed on the backup system instead of the pilot signal and sent to the receiving end station via the modulation transmission system of the predetermined backup system. On the receiving side, the digital signal of the active system that is the target of line switching is input to the synchronization switching circuit 40-1 via the frame synchronization circuit 38-1, and the digital multiplexed signal via the backup system mentioned above is also input. The signal is input to the synchronization switching circuit 40-1 via the frame synchronization circuit 38 and the received signal distribution circuit 39. In the synchronous switching circuit 40-1, the bit information of the digital signal via the wireless line of the above-mentioned working and backup systems is compared based on the digital signal via the working system, and when the bit information of both systems match, the bit information of the digital signal is switched to the working system. Line switching is performed from the system to the backup system. Thus,
The digital signal via the wireless line of the standby system is transmitted to the synchronous switching circuit 40-1 and the received signal processing circuit 4.
1-1, code conversion circuit 42-1 and switching circuit 4
3-1, the signal is output to a predetermined digital multiplex conversion terminal device.

In addition, the code conversion circuit 34- on the transmitting terminal side
1. Equipment failure in either the transmission signal processing circuit 35-1, the transmission signal distribution circuit 37-1, the synchronization switching circuit 40-1 on the reception terminal side, the reception signal processing circuit 41-1, or the code conversion circuit 42-1. If this occurs, the switching circuit 31-1 is switched, and the digital multiplexed signal branched in the branch circuit 31-1 is input to the code conversion circuit 34 of the standby system instead of the pilot signal, and the following code is used. The signal is sent to the receiving terminal via the conversion circuit 34, the transmission signal processing circuit 35, and the transmission signal switching circuit 36. On the receiving end station side, the digital signal via the backup system is processed by a frame synchronization circuit 38,
The switching circuit 43- via the received signal distribution circuit 39, the received signal processing circuit 41 and the code conversion circuit 42
1, and is output to a predetermined digital multiplex converter through the circuit switching action of the switching circuit 43-1.

(Problems to be Solved by the Invention) In a digital wireless transmission line using the above-mentioned line switching circuit (synchronous switching circuits 40-1 to 40-k in FIG. It is necessary to equip the backup system with a transmission signal switching circuit for line switching between systems, and to equip each active system with a transmission signal distribution circuit, which complicates the circuit configuration of the transmission terminal and increases the scale of the equipment. In addition to the problem of switching between the active and standby systems, the switching control between the active and standby systems is complex. This has the disadvantage that frame synchronization occurs in the frame synchronization circuit of the standby system on the station side, and the time required for line switching becomes relatively long, degrading line efficiency. Moreover, when the digital signal is divided into M sequences and transmitted in accordance with the modulation method in a digital radio transmission line, in order to eliminate the above-mentioned drawbacks, the M sequence digital signal sequence is transferred to the wireless line before speed conversion. If we attempt to take countermeasures by dividing the frequency by N to widen the range of uninterrupted switching between the working and standby systems due to fluctuations in the propagation path at
In addition to the phase uncertainty of the digital signal sequence that occurs during sequence conversion, there is also phase uncertainty that occurs due to the N division effect, and due to this phase uncertainty, there is However, there is a problem in that a code error occurs in the digital signal string to be switched, which may cause a line failure in the digital radio transmission line. Figure 3 a, b, c, d
What is shown in FIG. 3 and e is that during the four-sequence conversion in the case of M=4 described above, for one series of digital signals of m (an integer greater than 1) bit configuration shown in FIG. 3a, the third This indicates that the four types of digital signal sequences shown in FIGS. b, c, d, and e may be output in a corresponding manner. Generally, in the case of M-sequence conversion, there is a possibility that M types of M-sequence digital signal sequences may be generated, which causes uncertainty in the phase. Therefore, due to the two phase uncertainties mentioned above, the phases of the digital signal sequences in the working and standby systems cannot match in the working and standby switching circuit system at the receiving end station. Line switching becomes extremely difficult.

(Means for Solving the Problems) As a means for solving the above-mentioned problems, the line switching circuit of the present invention is formed by a predetermined number of active systems and a backup system, and a predetermined digital multiplex conversion terminal equipment. In a digital radio transmission line that divides and transmits a digital multiplexed signal inputted from a digital signal into M sequences, each of the M sequence digital signal sequences sent to a receiving terminal station via the above-mentioned current system is successively divided into N frequencies. Then, through a working system frequency dividing means that outputs (M×N) digital signal sequences defined by a predetermined phase and a predetermined switching means on the transmitting terminal side, The M-sequence digital signal strings sent to the receiving terminal station via the backup system are divided by N, and the (M×N)-series digital signal strings defined by a predetermined phase are obtained by ( (M×N) system/(M×N) output from the frequency dividing means of the working system and the standby system.
a signal string selection means for selecting and outputting one (M×N) series of digital signal strings from among the series of digital signal strings via a predetermined selection control signal; (M×N) of the output system and backup system
Compare and check the bit information of the digital signal string of the series using the bit information of the digital signal example in either the active or standby system that is subject to deselection by line switching, and check whether or not there is a mismatch in the bit information. bit comparison means for generating and outputting the selection control signal in response to the selection control signal;
Phase synchronization means for forming a time reference signal corresponding to either the active or standby system to be selected by line switching, and a predetermined switching control signal outputted from the signal train selection means. (M
×N) series of digital signal streams at a point in time when the bit information of the digital signal series matches, a signal switching means for performing a signal switching operation between the (M×N) series of digital signal streams of the current system and the standby system; and the signal switching means. A parallel/serial conversion means is provided for parallel/serial converting the (M×N) series of digital signal strings outputted from the converter and outputting an M series of digital multiplexed signals.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and the line switching circuit 27 in FIG.
-1 to 27-k details are shown. FIG. 2 is a block diagram showing the main parts of a transmitting terminal station and a receiving terminal station of a digital wireless transmission line to which this embodiment is applied. As shown in FIG. 1, this embodiment has a standby frequency dividing means consisting of a buffer memory 1 and a clock frequency dividing circuit 2, and a working frequency dividing means consisting of a buffer memory 6 and a clock frequency dividing circuit 7. , signal string selection circuits 3 and 8 and buffer memory 5,
10 and a bit comparison circuit 1.
4, phase comparator circuit 11, and voltage controlled oscillation circuit 12
and a phase synchronization means including a clock frequency divider circuit 13, clock selection circuits 4 and 9, a signal switching circuit 15, a bit error measurement circuit 16, a signal string selection control circuit 17, and a parallel/serial conversion circuit 18. We are prepared. The digital wireless transmission line shown in FIG. 2 is an example of a current system consisting of k (an integer greater than 1) systems, and the transmitting terminal station has the following:
Branch circuits 19-1 to 19-k and switching circuit 20-
1 to 20-k, a pilot generation circuit 21, code conversion circuits 22, 22-1 to 22-k, and transmission signal processing circuits 23, 23-1 to 23-k,
On the receiving terminal side, frame synchronization circuits 24, 24-
1 to 24-k, and received signal processing circuits 25 and 25-
1 to 25-k, the signal supply circuit 26, the line switching circuits 27-1 to 27-k of the present invention, the code conversion circuits 28, 28-1 to 28-k, and the switching circuit 29-
1 to 29-k, and a pilot detection circuit 30.

In FIG. 2, k systems of digital multiplexed signals inputted from a predetermined digital multiplex conversion terminal station are divided into branch circuits 19-1 to 19-k and code conversion circuits 22-1 to 22-k, respectively, during normal operation.
22-k, transmission signal processing circuits 23-1 to 23-k
The digital signals of each working system are sent to the receiving end station via a predetermined modulation and transmission system, and at the receiving end station, the digital signals of each working system are demodulated via a predetermined receive demodulation system, and are sent to the receiving end station via a frame synchronization circuit. 24-1
~24-k, received signal processing circuit 25-1~25-
k, circuit switching circuits 27-1 to 27-k of the present invention,
The signals are output to corresponding digital multiplex converters via code conversion circuits 28-1 to 28-k and switching circuits 29-1 to 29-k. Regarding the standby system, the pilot signal generated in the pilot generation circuit 21 is transmitted through the switching circuits 20-1 to 20-1.
20-k, is inputted to the frame synchronization circuit 24 via the code conversion circuit 22 and the transmission signal processing circuit 23, through a predetermined modulation transmission system and reception demodulation system of the backup system, and is input to the frame synchronization circuit 24 through the reception signal processing circuit 25 and the signal supply circuit. 26, code conversion circuit 28 and switching circuit 2
The signals are input to the pilot detection circuit 30 via signals 9-1 to 29-k and detected.

When switching from the current system to the backup system, for example, in the current system [1] shown in FIG. The digital multiplexed signal of the current system is
Instead of the pilot signal sent from the pilot generation circuit 21, it is sent to the code conversion circuit 22, and then sent to the signal supply circuit 26 via the transmission signal processing circuit 23, frame synchronization circuit 24, and reception signal processing circuit 25. is input. Signal supply circuit 2
6 transfers the digital signal of the working system sent from the transmitting terminal station via the backup system to the line switching circuits 27-1 to 27-2 of the corresponding working system.
The digital signal of the current system is supplied to the circuit switching circuit 27-k.
Sent to 1. Therefore, the same digital signal is simultaneously input to the line switching circuit 27-1, one via the current system and the other via the backup system. In addition, this line switching circuit 27-1
The fixed delay amount in both the working and standby systems should be the same in front of the system. In the digital radio transmission line shown in FIG. 2, the code conversion circuits 22, 22-1 to 22-k of each system including the working and backup systems convert k systems of digital signals sent from the digital multiplex conversion terminal equipment. The multiplexed signals are each divided into M series of digital signal sequences and sent to corresponding transmission signal processing circuits 23, 23-1 to 23-.
The embodiment shown in FIG. 1 is an example in which the number of systems is M=4.

In FIG. 1, four digital signal sequences D ₁ , D ₂ , D ₃ and D ₄ in the backup system and the working system are connected to the corresponding buffers.
The signals are input to memories 1 and 6 and stored at predetermined addresses. In addition, the clock signal CLK of each system is also input to the corresponding clock frequency divider circuits 2 and 7, and the clock signal CLK of each system is inputted to the corresponding clock frequency divider circuits 2 and 7.
The frequency is divided to generate clock signals having 16 time phase differences as shown in FIGS. 4c and 5c, and the clock signals φ ₁ , φ ₂ , Output as φ ₃ ,..., φ ₁₆ . These clock signals are sent to the corresponding buffer memory 1 and clock selection circuit 4, respectively.
is input to the buffer memory 6 and the clock selection circuit 9, and in the buffer memories 1 and 6, the aforementioned four series of digital signals are read out via the clock signal, respectively. digital signal string (D ₁₁ ,
D ₂₁ , D ₃₁ ,…, D ₄₄ ), (D ₂₁ , D ₃₁ , D ₄₁ ,…,
D ₁₁ ), (D ₃₁ , D ₄₁ , D ₁₂ ,…, D ₂₁ ),…, (D ₄₄ ,
D ₁₁ , D ₂₁ , . . . , D ₃₄ ) are output and sent to the corresponding signal string selection circuits 3 and 8. in this case,
The output phases of the clock signals φ ₁ , φ _{2 ,} φ ₃ , ..., φ ₁₆ output from the clock frequency dividers 2 and 7 are determined by the phase difference in the digital signal train caused by the M-sequence conversion and N-frequency division described above. The above-mentioned problems in both working and standby systems caused by determinism
In order to eliminate phase mismatch between the 16-system and 16-system frequency-divided digital signal trains, the clock frequency dividers 2 and 7 adjust and set specific phases, respectively. Therefore, as a result, if we look at any of the same data in the data string (Fig. 4c) frequency-divided by the current system and the data string (Fig. 5c) frequency-divided by the backup system, the phases will all match. It's just that the bit sequences do not necessarily match.

4a, b and c show four digital signal sequences D ₁ , D ₂ , D ₃ and D ₄ input to the buffer memory 6 in the current system.
, clock signal CLK, and clock frequency divider circuit 7
The clock signal φ ₁ (φ ₂ , φ ₃ ,...φ ₁₆
) and clock signals φ ₁ , φ ₂ , φ ₃ , ..., φ ₁₆
1 series/16 series digital signal strings (D ₁₁ , D ₂₁ ,
D ₃₁ ,...,D ₄₄ ) is an example. Also, Figure 5a,
FIGS. 4b and 4c show examples of digital signal sequences corresponding to FIGS. 4a, b and c in the backup system.

On the other hand, in response to line switching from the active system to the protection system, a predetermined signal selection control signal C
is input to the signal string selection control circuit 17. now,
If the four digital signal sequences in the working system and the backup system have different bit arrangements, for example, the bit arrangements in the working system and the backup system would be as shown in FIGS. 3c and d, respectively. Therefore, in the case where one system and 16 series of digital signal strings after frequency division by 4 in each of the working and standby systems are shown in Fig. 4c and Fig. 5c, respectively, In the standby system, one system of 16 systems of digital signal sequences is selected from the signal selection circuit 3 via the selection control signal _C1 sent from the signal sequence selection control circuit 17, and the corresponding buffer It is sent to the memory 5 and stored at a predetermined address. Also, the selection control signal
A clock signal corresponding to one system/16 systems of digital signal strings is selected from _the clock selection circuit 4 via C1 and sent to the signal switching circuit 15. In addition, in response to switching from the current system to the standby system, the digital signal string of the current system that serves as a reference is transferred to the buffer memory 1 as is.
Sent to 0.

In the signal switching circuit 15, the clock signal corresponding to the current system is first selected and output, and sent to the phase comparator circuit 11. In the clock frequency divider circuit 13, the output signal of the voltage controlled oscillator 12 is frequency-divided by four and sent to the phase comparison circuit 11. circuit 15
A phase synchronization system is formed using the clock signal selectively outputted from the clock signal as a reference signal. The clock frequency divider circuit 13 outputs 16 series of clock signals whose frequency is divided by 4 and has a time phase difference of 1/16 bits from each other, and is sent to the buffer memories 5 and 10, respectively. The bit selection signal is sent to the parallel/serial conversion circuit 18. Also,
A clock signal corresponding to the oscillation output of the voltage controlled oscillation circuit 12 is also sent to the parallel/serial conversion circuit 18.

In the buffer memories 5 and 10, the 16 series of digital signal sequences stored therein are read out via the 16 series of clock signals inputted from the aforementioned clock frequency divider circuit 13, and the corresponding bit comparison circuits are read out. 14 and signal switching circuit 15
sent to. In the bit comparison circuit 14, the bit information of the 16 series of digital signal strings read out and input from the buffer memories 5 and 10 are compared, and bit error information indicating whether each bit matches or mismatches is outputted. The signal is input to the bit error measurement circuit 16. Bit error measurement circuit 16
In the system, the bit error information is counted and a level signal J indicating whether the digital signal strings between the working and backup systems match or differ is outputted using a predetermined reference count value as a criterion, and is sent to the signal string selection control circuit 17. Sent. In the signal string selection control circuit 17, a logical operation is performed on the signal selection control C described above and the level signal J, a selection control signal _C1 is generated, and the corresponding signal string selection circuit 3 and clock selection circuit 4 are generated. sent to.

As mentioned above, if there is a difference in the bit arrangement of the digital signal strings in the working system and the backup system, the signal string selection circuit 3 selects one system in the backup system via the selection control signal _C1 . Sixteen digital signal sequences are selected, and at the same time, the clock selection circuit 4 selects clock signals corresponding to the selected sixteen digital signal sequences. The digital signal train of the selected backup system is sent via the buffer memory 5 to the bit comparison circuit 14 and the signal switching circuit 15, and the clock signal is sent to the signal switching circuit 15. On the other hand, on the current system side, the digital signal train is stored in the buffer memory 1.
0 to the bit comparison circuit 14 and the signal switching circuit 15, and the clock signal is sent to the signal switching circuit 15.

Through the above-described operation procedure, the level signal J indicating the match/mismatch of the digital signal strings outputted from the bit error measuring circuit 16 is outputted as a level signal corresponding to the match and sent to the signal string selection control circuit 17.
Also, the bit error measurement circuit 16
The signal switching circuit 15 is controlled by a predetermined line switching signal S input to the signal switching circuit 15 via the coincidence determination signal L output from the signal switching circuit 15.
Instead of the 16 digital signal sequences of the active system sent from the buffer memory 10, the backup system signals sent from the buffer memory 5 are
Sixteen digital signal sequences are selected, and among the clock signals sent from clock selection circuits 4 and 9, the clock signal corresponding to the backup system is selected and output. The selected clock signal is used as a reference signal for a phase synchronization system formed by a phase comparator circuit 11, a voltage controlled oscillator 12, and a clock frequency divider circuit 13.

The 16 series of digital signal series selected and switched by the signal switching circuit 15 are input to the parallel/serial conversion circuit 18, and the 16 series of digital signal series are inputted to the parallel/serial converter circuit 18, and the 16 series of digital signal series are inputted to the parallel/serial converter circuit 18. The signal strings are output as four digital signal strings D ₁ , D ₂ , D ₃ and D ₄ , and the clock signal sent from the voltage controlled oscillation circuit 12 is outputted as four digital signal strings D ₁ , D _{2 .} ,D ₃
and output as a clock signal CLK corresponding to _D4 .

As is clear from the above explanation, line switching between the active system and the protection system is performed in the signal switching circuit 15 when the 16 digital signal sequences in both systems match, so the line is momentarily disconnected. It runs smoothly in a completely hitless state without any additional effort. Moreover, in the above case, the phase comparator circuit 11,
Voltage controlled oscillator circuit 12 and clock frequency divider circuit 1
A clock signal corresponding to the standby system is generated through a phase synchronization system consisting of 3, and both are outputted from the parallel/serial conversion circuit 18 as described above. In the above description, the case where the line is switched from the active system to the backup system has been described, but the operation is exactly the same when the line is switched from the backup system to the active system and restored. Furthermore, it goes without saying that the number of digital signal sequences input to the line switching circuit of the present invention is not limited to the four sequences in the above embodiment.

(Effects of the Invention) As described above in detail, the present invention provides for transmitting M-sequence digital signal sequences in each of the working and standby systems in a digital wireless transmission line that divides digital multiplexed signals into M-sequences and transmits them. By dividing the frequency by N and adjusting the bits, line switching can be performed without momentary interruption, and there is an effect that momentary interruption caused by line switching can be completely eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of a digital wireless transmission line to which the invention is applied, and FIGS. d and e are explanatory diagrams for dividing digital multiplexed signals into series, and FIG. 4 a, b and c are
FIGS. 5a, b, and c are explanatory diagrams of the frequency division effect in the active system. FIG. 6 is a block diagram showing the main parts of an example of a conventional digital wireless transmission line. It is. In the figure, 1, 5, 6, 10...
Memory, 2, 7, 13...clock frequency divider circuit,
3, 8... Signal string selection circuit, 4, 9... Clock selection circuit, 11... Phase comparison circuit, 12... Voltage controlled oscillator, 14... Bit comparison circuit, 15...
Signal switching circuit, 16... Bit error measuring circuit, 1
7... Signal string selection control circuit, 18... Parallel/serial conversion circuit, 19-1 to 19-k, 31-1 to 31
-k...Branch circuit, 20-1 to 20-k, 29-
1~29-k, 32-1~32-k, 43-1~
43-k...Switching circuit, 21, 33...Pilot generation circuit, 22, 22-1 to 22-k, 28,
28-1 ~ 28-k, 34, 34-1 ~ 34-
k, 42, 42-1 to 42-k... code conversion circuit, 23, 23-1 to 23-k, 35, 35-1
~35-k...Transmission signal processing circuit, 24, 24-
1 to 24-k, 38, 38-1 to 38-k...frame synchronization circuit, 25, 25-1 to 25-k, 4
1, 41-1 to 41-k...reception signal processing circuit,
26... Signal supply circuit, 27-1 to 27-k...
Line switching circuit, 30, 44... Pilot detection circuit, 39... Received signal distribution circuit, 40-1 to 40
-k...Synchronization switching circuit.

Claims (1)

[Scope of Claims] 1 M (1
In a digital radio transmission line that divides and transmits the M-sequence digital signal sequences into (larger integer) sequences, each of the M-series digital signal sequences sent to the receiving terminal station via the current system is frequency-divided by N (an integer larger than 1). and a working system frequency dividing means for outputting (M×N) digital signal sequences defined by a predetermined phase, and a predetermined switching means on the transmitting end station side.
The M-sequence digital signal strings sent to the receiving terminal station via the backup system are each
Divide the frequency and specify the specified phase (M×N)
A standby system frequency dividing means for outputting (M×N) series of digital signal sequences; and (M×N) series/(M×N) series digital signals outputted from the working system and the standby system frequency dividing means. Signal string selection means for selecting and outputting one (M×N) series of digital signal strings from among the signal strings via a predetermined selection control signal; and output from the signal string selection means. The bit information of the (M×N) series of digital signal strings of the working system and the protection system is based on the bit information of the digital signal string of either the working or protection system that is to be deselected by line switching. A bit comparison means that compares and collates and generates and outputs the selection control signal depending on whether there is a mismatch in the bit information, and corresponds to either the current or standby system to be selected by line switching. phase synchronization means for forming a time reference signal for the current system and the standby system via a predetermined switching control signal; A signal switching means that performs a signal switching operation between the (M×N) series of digital signal streams of the current system and the standby system at the time when the information matches; and (M×N) series output from the signal switching means. By converting the digital signal string from parallel to serial, M
A line switching circuit comprising: parallel/serial conversion means for outputting a series of digital multiplexed signals;