JPH0354934A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain accurate phase synchronism by detecting zero crossing points generated between continuous zero signals in a pseudo ternary signal and inputting the detected zero crossing point to a PLL circuit. CONSTITUTION:The information of a ternary filter signal (b) is generated in a binary signal (f) only at '0' timing. On the other hand, an edge signal (h) is generated only at a change point '1' '0' or '0' '0' in the information of the signal (b). When the binary signal (f) is slightly delayed and the delayed signal (f) is used as a gate signal, a trigger signal (i) is generated only at a change point '0' '0' in the information of the signal (b). The PLL circuit 9 executes phase synchronism based upon the trigger signal (i) and reproduces a retiming clock signal. Thus, accurate phase synchronism can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized circuit, and more particularly to a phase synchronized circuit that reproduces a clock signal synchronized with a received pseudo ternary signal.

[Prior Art] Conventionally, this type of circuit has been used in terminal equipment (TE) such as telephones and facsimiles in ISDNjJ2. That is, this phase synchronization circuit receives a pseudo ternary signal (AMI
This circuit reproduces the retiming clock signal based on the retiming clock signal. Here, the AMI signal is a signal that constitutes a frame signal exchanged between the TE and NT, and is a bibolar signal whose polarity is inverted to positive or negative each time the binary information is zero.

FIG. 5 is a diagram explaining the AMI signal.

In the figure, no signal (0 level) represents information "1", and a positive polarity pulse or negative polarity pulse represents information ゜゜O''.

FIG. 6 is an operation timing chart of a conventional phase synchronization circuit. Conventionally, by comparing the 3-value input pulse signal with the threshold level PTh for positive polarity and the threshold level NTh for negative polarity, the portion where the 3-value input pulse signal exceeds these threshold levels PTh and NTh is extracted. 3-value - 2-value conversion is performed, and phase-lock droop (PLL) is applied to each edge portion of the resulting binary signal.
It was generating a trigger signal to the circuit.

[Problems to be Solved by the Invention] However, in this case, it is not possible to accurately detect the zero-crossing point of the ternary input pulse signal, which poses a problem in obtaining accurate phase synchronization. Furthermore, if the ternary input pulse signal becomes dull due to attenuation or the like, the error in detecting the zero-crossing point also increases.

The present invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is to provide a phase-locked circuit that provides accurate phase synchronization.

[Means and Effects for Solving the Problems J In order to achieve the above object, the phase-locked circuit of the present invention
In a phase synchronized circuit that reproduces a clock signal synchronized with a value signal, a zero cross point occurring between consecutive zero signals of the pseudo ternary signal is detected and inputted to a PLL circuit.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of the phase locked circuit according to the embodiment;
The figure is an operation timing chart of the phase locked circuit according to the embodiment. In the figure, l is a filter circuit, and the input 3
Noise, etc. carried during line transmission is removed from the value input pulse signal (frame signal) (2), and a ternary filter signal (2) is output. 2 is a comparator circuit which outputs a level 1 signal ◎ whose level is inverted at a signal level change point from "1" to "0" or from "0" to "O" in the input ternary filter signal ■.

FIG. 3 is a circuit diagram of the comparator circuit 2 of the embodiment, and FIG. 4 is an operation timing chart of the comparator circuit 2 of the embodiment. In FIG. 3, the output (level 1 signal) (2) of the comparator (CMP) is fed back to a predetermined voltage Vx to give the level 1 threshold (LITh) a hysteresis characteristic. As a result, as shown in Fig. 4, the comparator (CMP) is kept in a state insensitive to noise etc. during the section where the ternary filter signal ■ is at the potential level of information "l", and the ternary filter signal ■ is at the potential level of information "l". Even if it is a little unstable, malfunctions can be avoided. Also, the output level 1 signal @ is the information “1” → “O” or “0” in the ternary filter signal ■.
→ Invert the level only at the “0” change point, and
The level is not inverted at the change point of the information "O'" to "1" in the value filter signal (2).

Returning to FIGS. 1 and 2, 5 is an edge detection circuit which outputs an edge signal O having a predetermined pulse width at each edge portion of the level 1 signal ◎.

On the other hand, 3 is a comparator circuit, which compares the ternary filter signal ■ with the threshold signal PTh.
A positive polarity pulse signal in the value filter signal (■) is extracted and a positive polarity signal (■) is output. 4 is also a comparator circuit, which has a ternary filter signal ■ and a threshold signal N.
By comparing Th, a negative pulse signal in the ternary filter signal (2) is extracted and a negative polarity signal (2) is output. 6 is a binary conversion circuit which performs a logical NOR operation on the positive polarity signal ■ and the negative polarity signal ◎ and outputs a binary signal ■. Reference numeral 7 denotes a delay circuit, which delays the binary signal (2) by, for example, approximately half the pulse width of l-bit information and outputs a delayed signal 0. and,
8 is a gate circuit which outputs a trigger signal by extracting the edge signal 0 in the section where the delayed signal 2 is at the logic O level.

In other words, the binary signal ■ has the information of the ternary filter signal ■ "0".
It only occurs at the timing of On the other hand, the edge signal ■ is the information “1” in the ternary filter signal ■ → “o”
Or, it only occurs at the change point of "O゜゛→゜"O." Therefore, if the binary signal O is delayed a little and used as a gate signal, the trigger signal This will occur only at the "one" ON change point.

Reference numeral 9 denotes a phase lock loop (PLL) circuit, which performs phase synchronization based on the trigger signal (2) and regenerates the retiming clock signal.

[Effects of the Invention] As described above, according to the present invention, the phase deviation of the retiming clock signal with respect to the ternary input pulse signal can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram of the phase-locked circuit of the embodiment, Fig. 2 is an operation timing chart of the phase-locked circuit of the embodiment, Fig. 3 is a circuit diagram of the converter circuit 2 of the embodiment, and Fig. 4 is the embodiment. FIG. 5 is a diagram for explaining the AMI signal, and FIG. 6 is an operation timing chart of the conventional phase locked circuit. In the figure, 1... filter circuit, 2-4... converter circuit, 5... edge detection circuit, 6... binary conversion circuit, 7... delay circuit, 8... gate circuit, 9...
It is a phase locked loop (PLL) circuit.

Claims (1)

[Claims] In a phase-locked circuit that regenerates a clock signal synchronized with a received pseudo-ternary signal, a zero-crossing point occurring between consecutive zero signals of the pseudo-ternary signal is detected and input to a PLL circuit. A phase-locked circuit characterized by: