JPS63302638A - Phase locked loop circuit for terminal equipment - Google Patents

Abstract

PURPOSE:To stabilize a retiming clock by impressing on a PLL either a change point from a space signal to positive polarity or negative polarity mark signals, or a change point which changes between both mark signals. CONSTITUTION:If a reception AMI signal is inputted to a comparator circuit 1, it outputs a binary signal. An edge detection circuit 2 detects the rise of the signal and outputs an edge signal to a gate circuit 4. A delay circuit 3 delays the binary signal from the comparator circuit 1 by 1/2 pulse and outputs it to the gate circuit 4. The gate circuit 4 outputs a trigger signal in an optional signal change point to the PLL5 based on both input signals, and the PLL5 executes phase synchronization and outputs a retiming clock signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a phase locked circuit for a terminal device.

[Conventional technology] For example, the phase synchronization circuit of a conventional terminal device is as follows.

It is used in the Integrated Services Digital Network (ISDN) and regenerates a retiming clock based on an AMI signal from a network termination device.

Here, the AMI signal is a bipolar code whose polarity is reversed to positive or negative for each binary upper sign zero signal, and an example thereof is shown in FIG.

The 100% AMI signal shown in FIG. 2 has a binary value of 1.0. l, 0. Olo, 1 signal is shown and this 2
When the value data is rewritten to a 100% AMI signal, it becomes as shown in FIG. In other words, for binary "1", AM
The I signal becomes a space signal, and binary "0" data is displayed as a positive polarity mark signal or a negative polarity mark signal of the AMI signal. And binary “0”
When there are two series, the negative polarity mark signal is switched to the positive polarity mark signal, and if the binary "O" continues, the positive polarity mark signal is switched to the negative polarity mark signal, and this signal is returned green.

In the phase synchronization circuit of a conventional terminal device, a phase comparator receives an AMI signal via a transmission line, and the level of the received AMI signal is 0 to 1 l, 0 to 0, and 0 to 0 (positive polarity mark signal to negative polarity mark signal or vice versa)
A retiming clock signal is generated based on each change point of .

By the way, the AMI signal that has passed through the transmission path is attenuated on the way, and the change point in the attenuated received AMI signal is as follows.
The point of change between levels 0 and 1 is different from the point of change between levels 0 and 0. This state is shown in FIG. FIG. 3 is a diagram showing an example of an eye pattern of a received AMI signal.

In this way, jitter occurs when the change points are different. An example in which this shifter occurs is shown in FIG.

FIG. 4 shows an example of jitter that occurs when slicing at a pulse amplitude of 172.

[Problems to be Solved by the Invention] The conventional device described above has a problem in that the retiming clock becomes unstable.

[Means for Solving the Problems] The present invention provides a change point from a space signal to a positive polarity mark signal or a negative polarity mark signal, and a change between the positive polarity mark signal and the negative polarity mark signal. Among the points,
Only one of the changing points is applied to the PLL.

[Operation] The present invention provides a method for detecting either one of a change point from a space signal to a positive polarity mark signal or a negative polarity mark signal, and a change point between the positive polarity mark signal and the negative polarity mark signal. Since only the change point of 2 is applied to the PLL, the retiming clock is stabilized.

[Example] FIG. 1 is a block diagram illustrating the principle of the invention.

This block diagram shows a comparator circuit 1, an edge detection circuit 2, a delay circuit 3, a gate circuit 4, and a PLL (
phase-locked logic) 5.

The comparator circuit 1 is a comparator that converts the received AMI signal into a binary signal.The edge detection circuit 2 is a comparator that converts the received AMI signal into a binary signal.
This circuit detects the rising edge of the binary signal output by the comparator circuit l. The delay circuit 3 is a circuit that delays the binary signal output from the comparator circuit 1 by half a pulse.

The gate circuit 4 calculates A based on the edge signal output from the edge detection circuit 2 and the delay pulse output from the delay circuit 3.
Only one of the points where the MI signal changes from the space signal to the positive polarity mark signal or the negative polarity mark signal, and the changing point between the positive polarity mark signal and the negative polarity mark signal. This is a circuit that applies the voltage to the PLL5.

The PLL 5 is a circuit that creates its own clock and also creates other timing clocks based on the received AMI signal.

FIG. 6 is a diagram showing a specific example of the edge detection circuit 2,
FIG. 7 is a diagram showing a specific example of the delay circuit 3, and FIG. 8 is a diagram showing a specific example of the gate circuit 4.

Next, the operation of the above embodiment will be explained.

FIG. 5 is a diagram showing output signals of each circuit in the above embodiment.

When the received AMI signal shown in FIG. 5 (1) is input to the comparator circuit 1, the comparator circuit 1
) Outputs the binary signal shown in The edge detection circuit 2 detects the rising edge of the binary signal and detects the rising edge of the binary signal as shown in FIG.
Output the edge signal shown in 3). On the other hand, the delay circuit 3 converts the binary signal output from the comparator circuit 1 into 1/
After delaying by two pulses, a delayed binary signal shown in FIG. 5 (4) is output.

Based on the edge signal output from the edge circuit 2 and the delayed binary signal output from the delay circuit 3, the gate circuit 4
Trigger signal at any signal change point (Fig. 5 (5),
(6)) is output.

The PLL 5 performs phase synchronization based on the trigger signal output from the gate circuit 4 and reproduces the retiming clock.

The signal shown in FIG. 5 (5) is a trigger signal created by ANDing the signal obtained by inverting the delayed binary signal and the edge signal, and is used in the exclusive OR circuit in the gate circuit shown in FIG. This is a signal generated when the signal change selection signal applied to the signal change selection signal is set to "1". On the other hand, the trigger signal shown in FIG. 5(6) is a trigger signal obtained by ANDing the edge signal and the delayed binary signal, and is applied to the exclusive OR circuit in the gate circuit shown in FIG. This is a trigger signal that is generated when the signal change selection signal is set to "0".

Then, the trigger signal shown in FIG. 5(1) and the trigger signal shown in FIG.
), the jitter shown in FIG. 4 will not occur if only one of the trigger signals is used.

Note that the trigger signal shown in FIG. 5 (5) uses the point of change of the AMI signal from the space signal to the positive polarity mark signal or negative polarity mark signal as the trigger signal,
If you look at it as a binary value.

The point of change at which the trigger signal switches to a "0" signal is used as the trigger signal. On the other hand, the trigger signal shown in FIG. 5 (6) uses the point of change between the positive polarity mark signal and the negative polarity mark signal of the AMI signal as the trigger signal, and in terms of two signals, The point of change at which the "0" signal switches to the "0" signal is used as a trigger signal.

[Effects of the Invention] According to the present invention, there is an effect that the retiming clock is stabilized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the principle of the invention. FIG. 2 is a diagram showing an example of an AMI signal. FIG. 3 is a diagram showing an example of an eye pattern of a received AMI signal. FIG. 4 is a diagram illustrating an example of jitter that occurs due to differences in the adopted change points. FIG. 5 is a diagram showing output signals of each circuit shown in FIG. 1. FIG. 6 is a diagram showing an example of the edge detection circuit in FIG. 1. FIG. 7 is a diagram showing an example of the delay circuit in FIG. 1. FIG. 8 is a diagram showing an example of the gate circuit in FIG. 1. l... Comparator circuit, 2... Edge detection circuit, 3... Delay circuit, 4... Gate circuit, 5... PLL. Patent applicant Canon Co., Ltd. Agent Arata Yokubo - Figure 5 Output signal 2 of Xlr each day (Jk---010001 Torigai number

Claims (1)

[Claims] In a phase synchronization circuit of a terminal device that regenerates a clock synchronized with a received AMI signal, 1. A phase synchronization circuit for a terminal device, characterized in that only one of the change points that change between the sex mark signal and the sex mark signal is applied to the PLL.