JPH0354869A - Semiconductor non-volatile memory - Google Patents

Abstract

PURPOSE:To assure low voltage and high speed operations by lowering the concentration of a channel region surface by doping a P or N type impurity into a channel region controlled by a floating gate electrode. CONSTITUTION:First and second impurity regions 8, 9 are formed by doping a P or N type impurity into a channel region being the surface of a substrate 1 located between a source region 2 and a drain region 3. When boron is employed as the impurity into the region 8 and arsenic as that into the region 9, the thinner concentration N type impurity region 9 can be formed on the inside of the denser P type impurity region 8 because the diffusion coefficient of the arsenic is smaller than that of the boron. Accordingly, threshold voltage after irradiation with ultraviolet ray can be lowered to assure high speed and low voltage operations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used in electronic equipment such as computers.

[1 Summary of the Invention] The present invention achieves low voltage operation by doping a channel region controlled by a floating gate electrode with P-type and N-type impurities in an ultraviolet-erasable floating gate type semiconductor nonvolatile memory. This enables high-speed operation.

[Conventional technology]

Conventionally, as shown in FIG. 2, an N-type source region 2 and a drain region 3 are provided on the surface of a P-type semiconductor substrate 1, and a channel region on the semiconductor substrate surface between the source region 2 and the drain region 3 is formed. Floating gate electrode 5 covered with an insulating film on top
An ultraviolet erasable semiconductor nonvolatile memory is known. For example, M. Wada et al.
”Li+IIiting Factors for Pr
programming EPROM of Reduce
d Dimensionsin IEDM Dig. T
ech. PaperS, pp38-41 (1980
) is disclosed.

[Problem to be solved by the invention]

However, conventional semiconductor non-volatile memory has
As shown in FIG. 2, since an impurity region 8 with a higher concentration than the substrate is formed on the surface of the substrate 1, the threshold {l! The f voltage is as high as approximately 1.5V, so it has the disadvantage that it is difficult to operate in a low voltage range.

Therefore, in order to solve these conventional drawbacks, the present invention is characterized by providing a semiconductor nonvolatile memory that operates at low voltage and at high speed while maintaining the program characteristics and isolation state.

[Means to solve the problem]

In order to solve the above five problems, the present invention provides a thinly-concentrated impurity region containing an impurity of the opposite conductivity type inside a highly-concentrated impurity region for obtaining product characteristics and isolation characteristics between cells. By lowering the dark value voltage after ultraviolet erasure to about 0.7 square meters, low-voltage operation and high-speed operation were realized.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

The case of an N-type ultraviolet evaporation type semiconductor nonvolatile memory will be explained. FIG. 1 is a sectional view of a first embodiment of the invention. An impurity region 8 having a higher concentration than the substrate 1 is formed on the surface of a P-type silicon substrate 1. Furthermore, impurity l7 region 8
A region 9 is doped with a lightly concentrated N-type impurity inside the region 9 . A floating gate electrode 5 is provided on the surfaces of impurity regions 8 and 9 with a gate oxide film 4 interposed therebetween.
A control gate electrode 7 is formed on the control gate insulating film 6 via a control gate insulating film 6. Further, on the substrate surface below the floating gate z-pole 5, an N′ type source region 2 and a drain region 3 are provided at intervals. Here, the control gate electrode 7 is connected to the floating gate electrode 5 via the control gate insulating film 6.
The potential of the floating gate electrode 5 can be indirectly controlled by applying a voltage to the control gate electrode 7. First, a reading method for a floating gate type semiconductor nonvolatile memory as shown in FIG. 1 will be explained. Control gate electrode 7
Information can be read by detecting the impedance of the channel region, which is the surface of the semiconductor substrate 1 between the source region 2 and the drain region 3, while a constant voltage is applied to the channel region. That is, when a large number of electrons are injected into the floating gate electrode 5, the impedance is high, and conversely, when no electrons are injected into the floating gate electrode 5, such as after erasure of ultraviolet rays, the impedance becomes low. Therefore, since the impedance changes depending on whether or not electrons are injected into the floating gate electrode 5, information can be read out. Since this information corresponds to the amount of electrons in the floating gate electrode 5, it is hardly emitted during normal operation or storage conditions. When changing information, electrons in the floating gate electrode 5 are emitted to the substrate by irradiation with ultraviolet light (ultraviolet erasure), and then,
This is done by injecting (programming) electrons into the floating gate electrode 5 by applying a voltage to each electrode in accordance with the information to be programmed. A method for injecting, that is, programming, these electrons into the floating gate electrode 5 will be described in detail.

The source region 2 is set to the same potential as the substrate 1, a voltage of 4 to 10 V is applied to the drain region 3, and a voltage of 4 to 10 V is applied to the control gate electrode 7.
When a high voltage of ~14 V is applied, a channel current flows between the source and drain regions, a part of which becomes hot electrons and is injected into the floating gate electrode 5. Memory cells that are not desired to be implanted will not be implanted if either the drain region 3 or the control gate 7H pole 7 is set to the same potential as the substrate.

By providing the P-type heavily doped region 8 on the surface of the substrate 1, hot electrons are more likely to be generated, and the programming characteristics can be improved.

FIG. 3 is a sectional view in the channel width direction of the semiconductor nonvolatile memory of the present invention. When memory cells are arranged in an array, it is necessary to separate each memory cell. That is, the third
As shown in the figure, for example, the drain region 3A of memory cell A and the drain region 3B of memory cell B are field oxidized It! 210+ minute ilift eM area 20
Therefore, electrical isolation is required. When electrons are injected into the floating gate electrode 5, a high voltage is applied to the control gate electrode 7 and the drain region 3, but separation that can withstand the application of the high voltage is required. For example, about 1
When electron injection is performed by applying a voltage of 2.5V, the isolation region 20 must be formed to withstand this voltage of 12.5V. In the present invention, as shown in FIG.
The dark value voltage of the separation region 20 can be made high by forming the separation region 20 in a self-aligned manner with respect to the region (referring to the region other than the region) or by making the separation region 20 sufficiently overlap the high concentration region 8. , it maintains a separation property of 61.

When using approximately 12.5V for programming, the amount of ions to be implanted into the high concentration region 8 is 2XIO”atoms/
Doping of cj or more is required. By increasing this doping amount, separation characteristics can be improved.

Furthermore, in the semiconductor nonvolatile memory of the present invention, in order to enable low voltage operation, an N-type dopant is provided inside impurity region 8 instead of reducing the concentration of impurity region 8. Due to this region 9, the concentration on the surface of the channel region is low, and the dark value voltage after UV irradiation is about 0.
It can be set to about 7V. This N-type dopant can be introduced in the same step as the P-type highly impurity region 8.

That is, the active region can be formed by double ion implantation of N-type and P-type doped bands without increasing the number of photo steps. However, it is necessary to use an element with a smaller diffusion constant than the P-type dopant for the N-type dopant so that the region 9 can be formed inside the region 8.

For example, if arsenic is used as the N-type dopant and boron is used as the P-type dopant, a lightly doped ♂■ impurity region 9 can be provided inside the heavily doped P-type region 8, as shown in FIG.

As described above, even if the region 9 is formed to lower the dark value voltage, the isolation between each memory cell as shown in FIG. 3 is sufficient. That is, this is because the amount of overlap between the P-type high concentration impurity region 8 and the field oxide film 10 is sufficient.

Specifically, the ion implantation dose for separation is 2XI
Region 8 is shaped with boron of O"ato+*s/1 or more, and region 9 is shaped by ion implantation of arsenic smaller than the amount of boron implanted, so that it operates in a low voltage region with good isolation characteristics and programming characteristics. Memory can be realized.Ion implantation of boron and arsenic can be performed by continuous ion implantation in the same photo process, so there is no cost increase due to an increase in the photo process.In addition, effectively, N-type and P-type dopant The fact that the electrode is formed in a self-aligned manner with respect to the separation region also improves the separation characteristics.

FIG. 4 is a sectional view of a second embodiment of the semiconductor nonvolatile memory of the present invention. The semiconductor nonvolatile memory of the present invention includes:
It goes without saying that the method is limited to silicon substrates, but can also be applied to semiconductor regions provided within the substrate. Also, g
The t-film can also be formed on the semiconductor surface. In FIG. 4, a floating gate electrode 5 is provided on the surface of a P-type silicon substrate l via a first gate insulating film 4, and a layer gap of 8M is formed above the floating gate electrode 5.
A control gate electrode 7 is formed through the film 6 and the second gate insulating film 14, and an N°-shaped electrode is formed on the surface of the base 1 in a self-aligned manner with respect to the floating gate electrode 5 and the control gate electrode 7. A source region 2 and a drain region 3 are formed. In addition, a P-type first impurity region 8 having a higher concentration than the semiconductor substrate 1 is formed in the channel region, which is the surface of the substrate 1 between the source region 2 and the drain region 3. A second layer containing a large amount of N-type impurity on the surface of impurity region 8
The impurity region 9 is clearly visible. Generally, the surface concentration of the first impurity region 9 is higher than the surface concentration of the second impurity region 10.
is electrically P type.

The first and second impurity regions can also be doped by ion implantation. Figure 5 shows the concentration distribution. That is, it shows the impurity distribution from the surface of the group 1 along the line AA' in FIG. This is a diagram in which boron is used as the impurity in the first impurity region 8 and arsenic is used as the impurity in the second impurity region 9. Even if boron and arsenic are introduced in the same process, the diffusion coefficient of arsenic is smaller than that of boron, so the distribution of arsenic falls inside the boron region as shown in FIG. Therefore, the electrical P on the surface of the channel region
The type impurity concentration has a low value due to the distribution of N-type arsenic. The first impurity region 8 is used in order to satisfy the programming characteristics of the semiconductor nonvolatile memory of the present invention as in the first embodiment, and to increase the dark value voltage of the field between memory cells. This is to electrically isolate a plurality of memory cells. The first impurity region 8 is made to easily generate hot electrons during programming by introducing P-type impurities of around 10'' atoms/cj into the surface of the substrate 1.The second impurity region 9
is the memory threshold {II! This is an area for lowering the voltage.

The control gate electrode 7 has strong capacitive coupling with the floating gate electrode 5. Therefore, by applying a voltage to the control gate electrode 7, the potential of the floating gate electrode 5 can be indirectly changed. First, a reading method of the semiconductor nonvolatile memory shown in FIG. 4 will be explained.

In a memory array in which a plurality of memory cells are integrated, in a cell from which information is to be read, that is, a selected memory cell, the source region 2 and drain Information can be read out depending on the conductance of the channel region between the region 3 and the region 3. That is, if the state is the same as after erasing the ultraviolet rays, the channel conductance is large; on the other hand, if a large number of electrons are injected into the floating gate electrode 5 due to programming, the channel conductance is small. The channel conductance is divided into a first channel region controlled by the control gate electrode 7 via the second gate insulating film 14 and a second channel region controlled by the potential of the floating gate voltage ViA5 via the first gate insulating film 4. This is the value of two channel regions connected in series. Since the conductance of the second channel region changes depending on the amount of electrons injected into the floating gate electrode 5, a constant voltage is applied to the control gate electrode 7, so that the distance between the source region 2 and the drain region 3 increases. The channel inductance changes, and information can be read out based on the amount of change.

In the semiconductor nonvolatile memory of FIG. 4 according to the second embodiment of the present invention, the first channel region is directly controlled by the voltage of the control gate electrode 7, and the first channel region is controlled by the potential of the floating gate electrode 5. The second channel region is connected in series with the second channel region. Therefore, even if the dark voltage of the second channel region after ultraviolet erasure is set sufficiently low, if the dark voltage of the first channel region is set to the enhanced level, the leakage current of unselected memory cells will be reduced. It can be made low enough. Furthermore, even if the voltage applied to the drain region 3 during readout increases the potential of the floating gate electrode 5 and increases the channel conductance of the second channel region, the channel conductance of the lth channel region is reduced. By setting this, off-leakage current of unselected memory cells can be prevented. moreover,
In the memory according to the second embodiment of the present invention, by grounding the drain region 3 and applying the NH voltage to the source region 2 via a load, the functionality can be improved by reading out the magnitude of the channel conductance. Can achieve high memory.

That is, since the floating gate electrode 5 is not structurally connected to the source region 2, erroneous writing (soft writing) during reading does not occur. Therefore, the channel length can be made shorter than that of conventional memory cells, and the source region 2
A high voltage close to the power supply voltage can be applied to the Therefore, it is possible to increase the channel conductance of the memory after erasing it with ultraviolet light, making it possible to achieve high-speed readout. Next, a memory programming method according to a second embodiment of the present invention will be described. In the case of a memory in which electrons are injected into the floating gate electrode 5, approximately 4 to
A 7V higher voltage is applied to the drain region 3. Further, a high voltage of about 12V is applied to the control gate electrode 7.
Due to this voltage application to the drain region 3 and the control gate electrode 7, a large channel current of about 1 mA flows in the channel region, hot electrons are generated near the drain region 3, and a part of them is injected into the floating gate electrode 5. be done. Since no voltage is applied to the control gate electrode 7 in the unselected memory cells, writing is not performed. In addition, even in the selected memory cell, in a memory cell in which electrons are not injected into the floating gate electrode 5, even if a high voltage is applied to the control gate electrode 7, writing can be performed by grounding the voltage of the drain region 3. Not done. That is, electrons are injected into the floating gate electrode 5 only when a voltage is applied to both the drain region 3 and the control gate electrode 7. The memory shown in FIG. 4 has a structure in which soft writes are less likely to occur, so that the channel length can be shortened. Therefore, writing can be performed in a very short time. In addition, in the write-unselected memory cell, even if a high voltage is applied to the drain region 3, since the control gate electrode 7 is grounded, the conductance of the first channel region is sufficiently small, and therefore the non-i ! It is possible to prevent off-leakage of memory cells.

Also, in order to lower the dark value voltage on the surface of the channel region,
Although the second impurity region 9 is formed of arsenic, the programming efficiency is not deteriorated by this impurity region 9. The surface potential for generating hot electrons near the drain region 3 formed during writing is hardly affected by arsenic doping. The second impurity region 9 made of arsenic has a small diffusion coefficient, so it is
This is because, as shown in the figure, it is very visible on the surface.

In order to lower the dark voltage of the channel region, instead of forming the second impurity region 9, the first impurity region 9 is added. If the concentration of the iIT region 8 is lowered, the shape of the surface potential for generating hot electrons becomes gentle, resulting in poor programming efficiency. The shape of the second impurity region 9 allows the programming efficiency of the memory to be maintained and the dark value voltage of the memory to be lowered.

Next, a method of erasing the memory shown in FIG. 4 will be explained. Erasing is performed by irradiating the memory with ultraviolet light.

The electrons injected into the floating gate electrode 5 are excited by ultraviolet light and returned to the substrate 1, where they are erased.
Figure 6 shows the arsenic (A!) dark value voltage of the memory after ultraviolet erasure.
It is a figure showing the injection amount dependence of (l). As shown in FIG. 6, by implanting arsenic, it is divided into region 8, where the dark value decreases significantly at the boundary of the 5×10'' implantation amount, and region B, where the dark value decreases small.Memory of the second embodiment The dark value voltage of is the larger dark value of either the first channel region or the second channel region.If the second impurity region 9 of arsenic is not formed, that is, the ion implantation amount is zero. The dark value voltage after ultraviolet erasure in the case of is equal to the dark value voltage of the second channel region, which is the higher dark value voltage.As the amount of arsenic implanted into the second impurity region 9 increases, No.l
The magnitudes of the dark value voltages of the channel region and the second channel region are reversed. That is, as the amount of arsenic implanted increases, the region shifts from region 8 to region B. Region A corresponds to the dark value voltage of the second channel region, and region B corresponds to the dark value voltage of the first channel region. In region B, the method for reducing the dependence of the dark voltage of the first channel region on the arsenic implantation amount is as follows:
The capacitance per unit area of the second gate insulating film 14 is
This can be achieved by increasing the capacitance per unit area of the gate insulating film 4. By increasing the capacitance per unit area of the gate insulating film, the contribution of arsenic implantation to the dark voltage can be reduced. In the method of lowering the concentration of the first impurity region 8 without forming the second impurity region 9 in order to lower the dark value voltage of the memory, the dark value voltage of the second channel region is always higher than the second impurity region 9. The dark value voltage of the channel region 1 is higher than that of the channel region 1. The dark voltage of the second channel region is generally 70%, rather than 100%, due to the repulsive coupling between the control gate electrode 7 and the floating gate electrode 5.
It becomes high because of the capacitive coupling. However, in the memory of the second embodiment of the present invention, depending on the shape of the second impurity region 9, the dark value voltage of the first channel region is
can be higher than the dark value voltage of the channel region. The dark voltage of the first channel region can be made higher than the dark voltage of the second channel region by changing the impurity concentration.

FIG. 7 is a sectional view of a semiconductor nonvolatile memory according to a third embodiment of the present invention. A P-type third impurity region 21 is formed in the first channel region in a self-aligned manner using the floating gate electrode 5 as a mask. Since the P-type impurity is formed in a direction that cancels the impurity in the second impurity region 9 containing N-type impurity, the rA value voltage of the first channel region can be increased. In the semiconductor nonvolatile memory shown in FIG. 4 as well, if the second gate insulating film is formed using a thermal oxide film after removing the first gate insulating film 4, a part of the second impurity region 9 will be removed from the second gate insulating film. Therefore, the concentration of arsenic in the first channel region can be lowered. Therefore, the dark value voltage of the first channel region is higher than the dark value voltage of the second channel region. As explained above, in the memories of the second and third embodiments, the dark value voltage after erasure by ultraviolet rays can be lowered to about 0.5V by implanting arsenic. Since the dark value voltage of this memory is the dark value voltage of the first channel eI region, it is stable regardless of the voltage of the drain region 2, and off-leak current can be reduced. Since the dark value voltage can be lowered to about 0.5V, the memory can be operated up to about 1V as the electric tA voltage. Furthermore, since the dark voltage can be lowered, the drain current can be increased, and high-speed operation can be easily achieved.

[Effects of the Invention] As explained above, the present invention provides dopants of the same conductivity type as the substrate doped on the surface of the semiconductor substrate in a self-aligned manner with respect to the isolation region, and This is an ultraviolet erase type floating gate type semiconductor non-volatile memory that has a low dow band.By lowering its threshold 4fi voltage to 0.5 to 1.0μ, it can achieve low This has the effect of facilitating operation in a voltage range and high speed operation.

[Brief explanation of drawings]

1 is a sectional view in the channel length direction of a semiconductor nonvolatile memory according to a first embodiment of the present invention, FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory, and FIG. 3 is a sectional view of a semiconductor nonvolatile memory according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor non-volatile memory including the drain S region in an array state in the channel width direction of the non-volatile memory; FIG. 4 is a cross-sectional view of a second embodiment of the semiconductor non-volatile memory according to the present invention; The figure shows the impurity distribution diagram of the channel region along the line A-A' of the semiconductor nonvolatile memory in Figure 4, and
The figure shows the arsenic ion implantation dependence of the dark voltage of the semiconductor nonvolatile memory of the second embodiment, and FIG. 7 is a cross-sectional view of the third embodiment of the semiconducting nonvolatile memory of the present invention. be. 1... Semiconductor substrate 2... Source region 3... Drain region 5... Floating gate electrode 7... Control gate electrode or higher

Claims (1)

[Claims] a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region and having a higher concentration than the first semiconductor region; a source region and a drain region of a conductivity type opposite to the first conductivity type provided at intervals on the surface portion of the second semiconductor region; and the first source region and drain region provided inside the second semiconductor region.
a third semiconductor region containing impurities of conductivity type and opposite conductivity type; a floating gate electrode provided on the third semiconductor region via a first insulating film; and a second insulating film on the floating gate electrode. A semiconductor nonvolatile memory consisting of a control gate electrode provided through a film.