JPH0354461B2 - - Google Patents
Info
- Publication number
- JPH0354461B2 JPH0354461B2 JP57030292A JP3029282A JPH0354461B2 JP H0354461 B2 JPH0354461 B2 JP H0354461B2 JP 57030292 A JP57030292 A JP 57030292A JP 3029282 A JP3029282 A JP 3029282A JP H0354461 B2 JPH0354461 B2 JP H0354461B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- active layer
- opening
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 23
- 150000001875 compounds Chemical class 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 239000007789 gas Substances 0.000 description 11
- 238000003631 wet chemical etching Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 230000007935 neutral effect Effects 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004925 denaturation Methods 0.000 description 2
- 230000036425 denaturation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はドライエツチング法を用いた化合物半
導体の微細加工方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for microfabrication of compound semiconductors using a dry etching method.
(2) 技術の背景
半導体素子の高集積化及び素子特性の向上を計
る為に半導体の微細加工技術が必要不可欠となつ
ている。化合物半導体の加工法として従来よりウ
エツト化学エツチング法が用いられているが、ウ
エツト化学エツチング法では等方的にエツチング
が進行する為、例えばリセス構造を有する化合物
半導体FETを製作する場合には、ゲート直下の
リセス形成工程の際、マスク下部までエツチング
が進む為、マスクパターン幅より広い加工が施さ
れ、精度の良い微細パターンが得られない。従つ
て、このウエツト化学エツチング法により横方向
へのくい込みが、前記リセス構造のFET素子で
は、ソース抵抗Rsの増大を導き、相互コンダク
タンスgmの低下を招く。(2) Background of technology Semiconductor microfabrication technology has become essential in order to increase the integration of semiconductor devices and improve device characteristics. Wet chemical etching has traditionally been used as a processing method for compound semiconductors, but since etching progresses isotropically in wet chemical etching, for example, when manufacturing a compound semiconductor FET with a recessed structure, the gate During the recess formation process directly below, etching progresses to the bottom of the mask, resulting in a process that is wider than the mask pattern width, making it impossible to obtain a fine pattern with high precision. Therefore, in the FET device having the recessed structure, the lateral penetration caused by this wet chemical etching method leads to an increase in the source resistance Rs and a decrease in the mutual conductance gm.
一方、ウエツト化学エツチング法に換わる技術
としてドライエツチング法が検討されているが、
ドライエツチング技術の一つであるプラズマエツ
チング法では選択性等は良好であるが、ウエツト
化学エツチングと同様、化学的反応のみを利用す
る為、等方的にエツチングが進み、前記と同様な
サイドエツチングが生じる。 On the other hand, dry etching is being considered as an alternative to wet chemical etching.
Plasma etching, which is one of the dry etching techniques, has good selectivity, but like wet chemical etching, it uses only chemical reactions, so etching proceeds isotropically, resulting in side etching similar to the above. occurs.
また、不活性ガスを用いるイオンエツチング法
では、物理的スパツタリング効果を利用する為、
イオン衝撃により化合物半導体表面のダメージが
大きいばかりでなく、エツチング速度の選択性が
非常に少なく且つエツチングレートも遅い。ま
た、レジストの硬化による変性が生じる等の原因
から加工性及び素子特性に大きく影響を及ぼす。 In addition, in the ion etching method using inert gas, the physical sputtering effect is used.
Not only does the ion bombardment cause significant damage to the surface of the compound semiconductor, but also the selectivity of the etching rate is very low and the etching rate is slow. In addition, processability and device characteristics are greatly affected due to causes such as denaturation due to curing of the resist.
そこで、最近化学的反応性に富み且つイオン性
の特徴を有する反応性イオンエツチング法がガリ
ウム・ヒ素（GaAs）等の化合物半導体に対して
も有力な微細加工技術として注目されつつある。 Therefore, reactive ion etching, which is rich in chemical reactivity and has ionic characteristics, has recently been attracting attention as a powerful microfabrication technique for compound semiconductors such as gallium arsenide (GaAs).
(3) 従来技術と問題点
次に、従来技術の問題点を図面を用いて説明す
る。第１図はリセス形成工程を施す前のFETの
概略断面である。同図に於いて、１は半絶縁性
GaAs基板、２はｎ型GaAs能動層、３は絶縁膜、
４はレジスト、５，６はソース・ドレイン電極を
それぞれ示している。第２図は従来のウエツト化
学エツチング法を用いて能動層２にパターンをエ
ツチングした時の前記第１図に示されたFETの
一部拡大図である。(3) Prior art and problems Next, problems with the prior art will be explained using drawings. FIG. 1 is a schematic cross-section of the FET before the recess forming process is performed. In the same figure, 1 is semi-insulating
GaAs substrate, 2 is n-type GaAs active layer, 3 is insulating film,
Reference numeral 4 indicates a resist, and 5 and 6 indicate source and drain electrodes, respectively. FIG. 2 is an enlarged view of a portion of the FET shown in FIG. 1 after a pattern has been etched into the active layer 2 using a conventional wet chemical etching method.
能動層２上には、パターニングされた開口部７
の幅がd1を有する絶縁膜３を更に開口部７に当た
る領域にパターニングされた開口部の幅d2がd1よ
り小さい（d1＜d2）開口部８を有するレジスト４
が前記絶縁膜３上に配置されている。ここで、絶
縁層３及びレジスト４によつて形成される層の断
面形状はオーバーハング状になつているが、これ
は後の工程でゲート電極を形成する際のリフトオ
フ法に利用する。 On the active layer 2, a patterned opening 7 is formed.
A resist 4 having an opening 8 whose width d 2 is smaller than d 1 ( d 1 < d 2 ) is further patterned in the region corresponding to the opening 7.
is arranged on the insulating film 3. Here, the cross-sectional shape of the layer formed by the insulating layer 3 and the resist 4 has an overhanging shape, which is utilized in a lift-off method when forming a gate electrode in a later step.
従来より上記構成から成る能動層２にレジスト
４に設けられた開口部８のパターンをエツチング
する際、水酸化カリウム（KOH）と過酸化水素
（H2O2）の混合溶液等を用いてウエツト化学エツ
チングを施していた。しかしながらウエツト化学
エツチング法では、パターンニングマスクとして
レジスト４よりも絶縁膜３が働き、且つ等方的に
エツチングが進行する為、能動層２でのエツチン
グの深さｔに対するパターンの幅ｄはｄd1＋2t
となる。従つて能動層２に形成されるパターン幅
ｄはレジスト４の開口部８の幅d2によつて決定す
ることはできないという問題点があつた。 Conventionally, when etching the pattern of the openings 8 provided in the resist 4 in the active layer 2 having the above-mentioned structure, a wet etching process was performed using a mixed solution of potassium hydroxide (KOH) and hydrogen peroxide (H 2 O 2 ). It had been chemically etched. However, in the wet chemical etching method, the insulating film 3 acts as a patterning mask rather than the resist 4, and the etching progresses isotropically, so the width d of the pattern relative to the etching depth t in the active layer 2 is dd 1 +2t
becomes. Therefore, there was a problem that the width d of the pattern formed in the active layer 2 could not be determined by the width d 2 of the opening 8 of the resist 4.
(4) 発明の目的
本発明の目的は、化合物半導体基板、若しくは
化合物半導体層（この後、化合物半導体基体と略
す）上に、開口部を有する絶縁膜が配置され該絶
縁膜上の前記開口部に当たる領域に前記開口部の
幅より小さい開口部を有するレジスト膜が配置さ
れた構造から成る半導体層に、前記レジスト膜を
マスクとして前記レジスト膜に設けられた開口部
のパターンを前記化合物半導体基体にエツチング
する際、前記レジスト膜の開口部が前記化合物半
導体基体でのパターン幅を精度良く規定すること
ができるエツチング方法を提供することにある。(4) Object of the Invention An object of the invention is to provide an insulating film having an opening on a compound semiconductor substrate or a compound semiconductor layer (hereinafter abbreviated as a compound semiconductor substrate), the opening on the insulating film. A pattern of openings provided in the resist film is formed on the compound semiconductor substrate using the resist film as a mask. An object of the present invention is to provide an etching method in which the opening of the resist film can accurately define the pattern width on the compound semiconductor substrate during etching.
(5) 発明の構成
本発明は、化合物半導体基板上に形成された化
合物半導体からなる能動層と、該能動層上にゲー
トリセス形成予定領域を挟んで対向配置されたソ
ース及びドレイン電極を有する化合物半導体装置
にゲート電極を形成する方法であつて、該能動層
表面に該能動層とは異なる材料から成る第１の
膜、第２の膜及び第３の膜を順次積層する工程
と、前記第３の膜の該ゲートリセス形成予定領域
対応する部分に該ゲートリセスの幅と略等しい幅
の第１の開口部を形成する工程と、該第３の膜を
マスクとして前記第２の膜をエツチングし、該第
１の開口部より大きな開口幅を有する第２の開口
部を形成する工程と、前記第１の膜より前記能動
層のエツチング速度が速いエツチングガスを用い
て反応性イオンエツチングにより前記第１の開口
部のパターンを前記能動層にパターニングする工
程を有することを特徴としている。(5) Structure of the Invention The present invention provides a compound semiconductor having an active layer made of a compound semiconductor formed on a compound semiconductor substrate, and a source and a drain electrode disposed on the active layer to face each other across a region where a gate recess is to be formed. A method for forming a gate electrode in a device, the method comprising: sequentially laminating a first film, a second film, and a third film made of a material different from the active layer on the surface of the active layer; forming a first opening having a width substantially equal to the width of the gate recess in a portion of the film corresponding to the region where the gate recess is to be formed; etching the second film using the third film as a mask; forming a second opening having a larger opening width than the first opening; and etching the first film by reactive ion etching using an etching gas that etches the active layer faster than the first film. The method is characterized in that it includes a step of patterning the active layer with a pattern of openings.
(6) 発明の実施例
本発明を本発明の一実施例を用いて詳述する。
第３図は前記第１図のFETを本発明の一実施例
の方法を用いてエツチングした時の一部拡大図で
ある。第１図で説明した部分と同部分は同記号で
指示してある。(6) Embodiment of the invention The present invention will be described in detail using an embodiment of the invention.
FIG. 3 is a partially enlarged view of the FET shown in FIG. 1 etched using the method of one embodiment of the present invention. The same parts as those explained in FIG. 1 are indicated by the same symbols.
本発明によれば、まず能動層２表面を酸素を含
む雰囲気中に一定時間さらすか或いは自然酸化し
て膜厚20〜30〔Å〕の酸化膜９を形成し、該酸化
膜９上にCVD法により膜厚0.5〔μｍ〕の二酸化
シリコン（SiO2）膜３を堆積し、更にSiO2膜３
上にフオトレジスト、例えばAZ1350J（商品名）
４を膜厚0.6〔μｍ〕塗布する。しかる後、フオト
レジスト４をパターニングして開口部の幅d2が
1.5〔μｍ〕となるような開口部８を形成する。次
に該フオトレジスト４をマスクとしてSiO2膜３
のみをフツ化水素（HF）溶液でウエツト化学エ
ツチングして前記レジスト４に形成した開口部８
下に開口部７を形成する。このとき、開口部７の
幅d1はd2よりも大きい５〔μｍ〕となるようにす
る。 According to the present invention, first, the surface of the active layer 2 is exposed to an oxygen-containing atmosphere for a certain period of time or is naturally oxidized to form an oxide film 9 with a thickness of 20 to 30 [Å], and then CVD is performed on the oxide film 9. A silicon dioxide (SiO 2 ) film 3 with a thickness of 0.5 [μm] is deposited by a method, and then a SiO 2 film 3 is deposited.
Photoresist on top, e.g. AZ1350J (product name)
4 to a thickness of 0.6 [μm]. After that, the photoresist 4 is patterned so that the opening width d 2 is
An opening 8 having a diameter of 1.5 [μm] is formed. Next, using the photoresist 4 as a mask, the SiO 2 film 3 is
Openings 8 are formed in the resist 4 by wet chemical etching with a hydrogen fluoride (HF) solution.
An opening 7 is formed at the bottom. At this time, the width d 1 of the opening 7 is set to 5 [μm], which is larger than d 2 .
この後、平行平板電極型ドライエツチング装置
を用いて、フロン１２（CCl2F2）とヘリウム
（He）との混合ガス（分圧比Pccl2F2／PHe＝
0.25〜２）を導入し、ガス圧１〜５〔Pa〕、パワー
密度0.2〜0.5〔Ｗ／cm2〕の条件でSiO2膜３及びレ
ジスト４が設けられた能動層２を反応性イオンエ
ツチングによつて３分間エツチング処理する。 After that, using a parallel plate electrode type dry etching device, a mixed gas of Freon 12 (CCl 2 F 2 ) and helium (He) (partial pressure ratio Pccl 2 F 2 /PHe=
0.25 to 2) and reactive ion etching of the active layer 2 provided with the SiO 2 film 3 and the resist 4 under the conditions of a gas pressure of 1 to 5 [Pa] and a power density of 0.2 to 0.5 [W/ cm 2 ]. Etch for 3 minutes.
このエツチング処理の際、化学的に活性なフツ
素Ｆ及び塩素Clイオン１０はプラズマと試料側電
極との間に発生する自己バイアス電圧に加速され
る為、試料表面に対して垂直方向の運転が生じ、
これより著しい異方性のエツチングが進行する。 During this etching process, the chemically active fluorine F and chlorine Cl ions 10 are accelerated by the self-bias voltage generated between the plasma and the sample-side electrode, so they cannot be driven in the direction perpendicular to the sample surface. arise,
From this point on, marked anisotropic etching progresses.
一方、活性化されなかつた中性のＦ、Cl等の反
応性中性粒子１１は自己バイアスの影響を受け
ず、等方的運動を行なう為、横方向への拡がりを
もちSiO2膜３に設けられた開口部７の幅d1の領
域まで進入する。しかし能動層２表面は酸化膜９
に被覆され且つエツチングガスによる能動層２と
酸化膜９の選択エツチング比が著しく異なる為、
中性粒子１１によるd1領域での能動層２のエツチ
ング進行は遮蔽される。 On the other hand, reactive neutral particles 11 such as neutral F and Cl that have not been activated are not affected by self-bias and move isotropically, so they spread in the lateral direction and are attached to the SiO 2 film 3. It enters into the area of width d 1 of the opening 7 provided. However, the surface of the active layer 2 is an oxide film 9.
Because the selective etching ratio of the active layer 2 and the oxide film 9 by the etching gas is significantly different,
The progress of etching of the active layer 2 in the d 1 region by the neutral particles 11 is blocked.
このような上記の効果から、能動層２でのエツ
チング幅ｄは、レジスト４の開口部８の幅d2で規
定される領域のみのエツチングが進み、該幅ｄは
ｄd2即ちｄはほぼ1.5〔μｍ〕となる。尚、幅d2
に対応した酸化膜９のエツチングはＦイオン若し
くはClイオン等による物理的スパツタリング効果
により除去されたものである。 Because of the above-mentioned effects, the etching width d in the active layer 2 progresses only in the region defined by the width d2 of the opening 8 of the resist 4, and the width d is dd2 , that is, d is approximately 1.5. [μm]. Furthermore, the width d 2
The etching of the oxide film 9 corresponding to the above was removed by a physical sputtering effect using F ions, Cl ions, or the like.
本実施例ではエツチングガスとしてCCl2F2ガ
スを用いたが、塩素Cl若しくは臭素Brを含んだ
ガスを使用しても同様な効果が得られる。また、
前記ガスと反応性イオンエツチング法と組み合わ
せることにより自然酸化膜及びプラズマグロウン
酸化膜に対する選択エツチング比は50〜100倍程
度と大きいことが実験より確認されており、中性
粒子による選択エツチング比は前記の値に比べよ
り著しくなると考えられる。尚、本実施例ではエ
ツチングマスクとして酸化膜９を用いたが窒化膜
を用いても同様な効果が得られる。 Although CCl 2 F 2 gas was used as the etching gas in this embodiment, the same effect can be obtained by using a gas containing chlorine Cl or bromine Br. Also,
It has been confirmed through experiments that the selective etching ratio for natural oxide films and plasma-grown oxide films is as high as 50 to 100 times by combining the above gas with the reactive ion etching method. This is considered to be more significant than the value of . In this embodiment, the oxide film 9 is used as an etching mask, but the same effect can be obtained by using a nitride film.
また、反応性イオンによる異方性エツチングは
比較的低い自己バイアス電圧である80〜90V程度
で且つ高いガス圧４〜5Paの実験下に於いても
GaAsの垂直なエツチング特性が得られているこ
とにより、反応性イオンによるサイドエツチング
が非常に少ないことが確認された。GaAsの表面
ダメージも後方散乱測定により、イオンエツチン
グ法に比べ著しく少ないことが示された。更にフ
オトレジスト及びSiO2膜などの絶縁膜に対する
GaAsの選択比は各々約15倍、約40倍と良好であ
り、且つレジストの変性もほとんどないことが確
認され、本発明の反応性イオンエツチングに対す
るマクク材として有効であることが示された。 Furthermore, anisotropic etching by reactive ions is possible even under experiments with a relatively low self-bias voltage of about 80 to 90 V and a high gas pressure of 4 to 5 Pa.
It was confirmed that side etching caused by reactive ions is extremely low due to the vertical etching characteristics of GaAs. Backscattering measurements showed that GaAs surface damage was significantly less than that achieved by ion etching. Furthermore, for insulating films such as photoresist and SiO 2 film,
It was confirmed that the selectivity ratio of GaAs was good at about 15 times and about 40 times, respectively, and there was almost no denaturation of the resist, indicating that it is effective as a masking material for the reactive ion etching of the present invention.
次に前記実施例の応用を簡単に述べることにす
る。 Next, the application of the above embodiment will be briefly described.
AlxGa1−xAs（ｘ＝0.1〜0.5）層上にGaAs層を
形成し、前記実施例と同様な方法でGaAs層をエ
ツチングすると、CCl2F2を含んだガスでは
AlGaAsはGaAsと比較して強い選択性を持つて
いる為、AlxGa1−xAs層の表面でほぼエツチン
グが停止するプロフアイルが得られた。AlxGa1
−xAs（ｘ＝0.1以上）に対するGaAsの選択比は
30倍以上である。従つてAlxGa1−xAs層は
CCl2F2を含んだガスを用いてGaAs層をエツチン
グする際のストツパーの役目を果すことができ
る。 When a GaAs layer is formed on the AlxGa 1 -xAs (x = 0.1 to 0.5) layer and the GaAs layer is etched in the same manner as in the previous example, the gas containing CCl 2 F 2 etches.
Since AlGaAs has strong selectivity compared to GaAs, a profile was obtained in which etching almost stopped at the surface of the AlxGa 1 -xAs layer. AlxGa 1
The selection ratio of GaAs to −xAs (x=0.1 or more) is
It is more than 30 times. Therefore, the AlxGa 1 −xAs layer is
It can serve as a stopper when etching a GaAs layer using a gas containing CCl 2 F 2 .
(6) 発明の効果
本発明によれば化合物半導体基体上に開口部を
有する絶縁膜が配設され、該絶縁膜上の前記開口
部に当たる領域に前記開口部の幅より小さい開口
部を有するレジスト膜が配設された構造から成る
半導体層を前記レジスト膜をマスクとして前記レ
ジスト膜に設けられた開口部のパターンを前記化
合物半導体基体にエツチングする際、前記レジス
ト膜の開口部が前記化合物半導体基体でのパター
ン幅を精度良く規定できるという効果がある。(6) Effects of the Invention According to the present invention, an insulating film having an opening is disposed on a compound semiconductor substrate, and a resist having an opening smaller than the width of the opening in a region corresponding to the opening on the insulating film. When a pattern of openings provided in the resist film is etched into the compound semiconductor substrate using the resist film as a mask for etching a semiconductor layer having a structure in which a film is provided, the openings in the resist film are etched into the compound semiconductor substrate. This has the effect that the pattern width can be defined with high accuracy.
尚、本発明はリセス構造を有するFETを製造
する時のみに限定するものではない。 Note that the present invention is not limited to manufacturing FETs having a recessed structure.
第１図はリセス形成工程を施す前のFETの概
略断面図、第２図は従来のウエツト化学エツチン
グ法を用いて能動層にパターンをエツチングした
時の前記第１図に示されたFETの一部拡大図、
第３図は前記第１図のFETを本発明の一実施例
の方法を用いてエツチングした時の一部拡大図で
ある。
２……ｎ型GaAs能動層、３……絶縁膜、４…
…レジスト、９……酸化膜。
Figure 1 is a schematic cross-sectional view of the FET before the recess formation process, and Figure 2 is a cross-sectional view of the FET shown in Figure 1 after a pattern has been etched into the active layer using the conventional wet chemical etching method. Enlarged view of part,
FIG. 3 is a partially enlarged view of the FET shown in FIG. 1 etched using the method of one embodiment of the present invention. 2... n-type GaAs active layer, 3... insulating film, 4...
...Resist, 9...Oxide film.
Claims (1)
体からなる能動層と、該能動層上にゲートリセス
形成予定領域を挟んで対向配置されたソース及び
ドレイン電極を有する化合物半導体装置にゲート
電極を形成する方法であつて、 該能動層表面に該能動層とは異なる材料から成
る第１の膜、第２の膜及び第３の膜を順次積層す
る工程と、 前記第３の膜の該ゲートリセス形成予定領域に
対応する部分に該ゲートリセスの幅と略等しい幅
の第１の開口部を形成する工程と、 該第３の膜をマスクとして前記第２の膜をエツ
チングし、該第１の開口部より大きな開口幅を有
する第２の開口部を形成する工程と、 前記第１の膜より前記能動層のエツチング速度
が速いエツチングガスを用いて反応性イオンエツ
チングにより前記第１の開口部のパターンを前記
能動層にパターニングする工程を有することを特
徴とする化合物半導体装置の製造方法。[Scope of Claims] 1. A compound semiconductor device having an active layer made of a compound semiconductor formed on a compound semiconductor substrate, and a source and a drain electrode arranged oppositely on the active layer with a region where a gate recess is to be formed sandwiched therebetween. A method of forming an electrode, the method comprising: sequentially laminating a first film, a second film, and a third film made of a material different from the active layer on the surface of the active layer; forming a first opening having a width substantially equal to the width of the gate recess in a portion corresponding to the region where the gate recess is to be formed; etching the second film using the third film as a mask; forming a second opening having an opening width larger than that of the opening; and etching the first opening by reactive ion etching using an etching gas that etches the active layer faster than the first film. 1. A method for manufacturing a compound semiconductor device, comprising the step of patterning the active layer with a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3029282A JPS58147122A (en) | 1982-02-26 | 1982-02-26 | Dry etching method for compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3029282A JPS58147122A (en) | 1982-02-26 | 1982-02-26 | Dry etching method for compound semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58147122A JPS58147122A (en) | 1983-09-01 |
| JPH0354461B2 true JPH0354461B2 (en) | 1991-08-20 |
Family
ID=12299648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3029282A Granted JPS58147122A (en) | 1982-02-26 | 1982-02-26 | Dry etching method for compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147122A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4595454A (en) * | 1984-06-15 | 1986-06-17 | At&T Bell Laboratories | Fabrication of grooved semiconductor devices |
| JPH0212817A (en) * | 1988-06-29 | 1990-01-17 | Nec Corp | Dry etching method |
| JP2953958B2 (en) * | 1994-09-01 | 1999-09-27 | 日本電気株式会社 | Dry etching method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52117554A (en) * | 1976-03-30 | 1977-10-03 | Toshiba Corp | Manufacturing method of semiconductor device |
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
| JPS5737835A (en) * | 1980-08-19 | 1982-03-02 | Nec Corp | Manufacture of semiconductor device |
-
1982
- 1982-02-26 JP JP3029282A patent/JPS58147122A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52117554A (en) * | 1976-03-30 | 1977-10-03 | Toshiba Corp | Manufacturing method of semiconductor device |
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
| JPS5737835A (en) * | 1980-08-19 | 1982-03-02 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58147122A (en) | 1983-09-01 |
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