JPH0353602A - Amplifier - Google Patents

Abstract

PURPOSE:To improve the power efficiency by controlling variably a DC voltage of a power supply supplied to a power amplifier element being a component of the amplifier in response to the amplitude of an input signal to be amplified so as to minimize the power loss in the power amplifier element. CONSTITUTION:A digital arithmetic processing unit 2 detects a peak of an input music signal subject to PCM coding for a prescribed period and extracts the envelope voltage, and its envelope voltage signal 14 is given to a voltage limit circuit 5, which uses load impedance identification signals 7a, 7b to vary a maximum voltage of DC voltages 10a, 10b applied to a power amplifier element 8. An error amplifier 12 detects a difference between the DC voltage 10a applied to the power amplifier element 8 and a reference voltage obtained from the envelope voltage and a pulse width control circuit 11 controls a pulse width based on the difference to control the DC voltage of the output voltages 10a, 10b of a switching power supply 10 thereby activating the power amplifier element 8 at a low loss. Thus, the power efficiency is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention 11 relates to an amplifier device that performs digital/analog conversion of a PCM encoded input signal, then amplifies the power and outputs it to a load. It is possible to minimize power loss in the power amplification element by variably controlling the DC voltage as a power source supplied to the power amplification element constituting the amplifier according to the amplitude value of the input signal to be amplified. The present invention relates to such an amplifying device. [Prior Art] As described in Japanese Unexamined Patent Publication No. 51-75862, a conventional amplifier device detects the peak value of a delay element using an input analog signal, and controls the magnitude of the DC voltage applied to the amplifier element. Was. [Problems to be Solved by the Invention] The above-mentioned conventional technology has problems with deterioration of audio characteristics, delay elements, frequency characteristics of peak value detection circuits, delay time management methods, and peak value detection when the load is a speaker. row k
In order to provide a delay time, consideration must be given to the fact that the amplitude of the delayed music signal does not match the output level of the peak value detection circuit for music signals whose amplitude changes over time. Great work is being done. In addition, as a power source to be applied to the power amplification element when the load impedance changes, (7) [fi voltage level has been considered.
stomach.

As a result, the audio characteristics deteriorate, and depending on the variations in the elements and the reproduction frequency, there is a problem that the reproduced waveform may become saturated at the power amplification element stage. Furthermore, depending on the load impedance, higher efficiency (lower loss in the power increasing 41i element) may not be achieved. Alternatively, there was a problem of saturation even though a small amount of power was applied. The purpose of the present invention is to
The input of the music signal to the amplification device is delayed, and during that time, a DC voltage as a power source corresponding to the signal waveform of the music signal is supplied to the amplification device. Good smoothness (no saturation etc.)
The delay time can be easily managed to enable amplification of the music signal, and the ohm value (
An object of the present invention is to provide such an amplifying device that can deal with the difference in load impedance and enable efficient and smooth amplification of music signals.

[Means to solve the problem]

Due to the above-mentioned discrepancies, in the present invention, in an amplifier device that performs digital/analog conversion of a PCM encoded input signal, then amplifies the power and outputs it to the load, a power amplification element that supplies the amplified output to the load is provided. And the power increase is 4L! A DC power supply I & which supplies power to the elements, and a PC
The M-encoded input signal is taken in, the maximum amplitude value for each certain section of the signal waveform is detected, and the signal is converted into an analog quantity via the first digital/analog converter. M. outputs it as a maximum value detection signal via the volume, writes the captured PCM-encoded input signal into memory, a processor for delaying the amount by a predetermined period of time, converting it into an analog quantity via a second digital/analog converter, and further inputting it to the power amplification element via a second volume; a voltage limit circuit that receives a maximum value detection signal from a pI1 volume and limits and outputs the maximum voltage;
and a power supply control device that controls the DC power supply device that supplies power to the power amplification element so that power loss in the power amplification element is minimized in accordance with the output signal from the nuclear voltage limit circuit. 1 In the amplifying device, the processing device takes in the PCM-encoded input signal and detects the maximum amplitude value for each certain section of the signal waveform. In both cases, the PCM-encoded input signal is written into the memory and held for a period equivalent to the delay time given by reading it out, and further, if a larger amplitude value is detected within the certain period, it is held immediately. The processing equipment that was

Furthermore, in the amplifying device, the first port IJ. - The volume and the second volume are made to be volumes that are interlocked with each other.

Further, in the above amplifier device, the voltage limit circuit comprises a voltage limit circuit that varies the maximum voltage to be limited according to the impedance of the load.

[Effect]

By processing the audio signal by PCM encoding, there is no deterioration of characteristics during the process of arithmetic processing. Furthermore, variations in delay time in the read/write memory (memory device fil) can be suppressed by adjusting the oscillation accuracy of the crystal, and it is difficult for some elements to malfunction. In addition, since the digital arithmetic unit (processing unit) extracts the envelope line of the music signal (maximum value detection in a certain section), the timing of the peak time and retention time do not match, causing a saturation state in the power amplification element. In addition, since the volume control volume is varied in conjunction with the digital-to-analog converted music signal and the envelope line, the level of the music signal input to the electric amplification element and without compromising the correlation with the applied DC voltage.
DC voltage can be controlled.

In addition, the maximum voltage that can be taken by the envelope wire can be varied according to the load impedance (impedance of the power output), reducing power efficiency due to load impedance and saturation in the power amplification element when using small currents. prevent.

As an alternative to the method of varying the volume adjustment volume in conjunction with the music signal and the envelope line, the position of the volume adjustment polygon is detected, and the amplification corresponding to that position is digitally processed to match the music signal. One possible method is to multiply the envelope line. As an alternative to the circuit that switches the maximum voltage taken by the envelope, a possible method would be to input load impedance information to a digital processing unit and multiply it by the music signal and the envelope. [Example] Hereinafter, an example of the present invention will be described with reference to FIG. The music signal is PCM encoded, and the digital arithmetic logic system fIL
2 is input to input section 1. The digital arithmetic processing unit 2 reads and writes music signals into a storage device (hereinafter referred to as RAM).
(hereinafter abbreviated as DAC) 3 and reads data from an address corresponding to a predetermined delay time, that is, after giving a predetermined delay time, it is output to a digital-to-analog converter (hereinafter abbreviated as DAC) 4g. On the other hand, the digital processing unit 2 detects the peak value of a certain section of the PCM-encoded input music signal, extracts the envelope voltage, and outputs it to the DAC 4b. The volume p4 adjustment volume 6 is configured to vary the music signal and the envelope voltage in conjunction with each other. The power amplification element 8 drives a load (for example, a speaker) 9. Power amplification element 8
The DC voltage applied as a power source is 10 (1.10A
It is. On the other hand, the envelope voltage signal 14 passes through the voltage limit circuit 5, and the load impedance identification signals 7a, 74
Accordingly, the DC voltage 1 applied to the oven amplification element 8 (for example, depending on the ohm value of the speaker as the load 9 used)
0iijVariable the maximum voltage of OA. The error amplifier 12 detects the difference between the DC voltage 1oα applied to the power amplification element 8 and the reference voltage obtained from the envelope voltage, and the pulse width control circuit 11 controls the pulse width based on the difference. The output voltage 10a. 1(
By controlling the DC voltage of 16, it is possible to operate the power amplifying element 8 with low loss.

The relationship between the envelope voltage signal 14 and the DC voltage 10m applied to the power amplification element 8 is shown in FIG. The maximum output voltage of the voltage limit circuit 5 is varied by the load impedance identification signal 76.7b, thereby preventing the power efficiency from deteriorating or becoming saturated due to the load impedance. Also,
The relationship between the voltage waveform 13 of the music signal applied to the load 9 and the DC voltage 104.10A applied to the power amplification element 8 is shown in FIG.

In order to simplify the circuitry, the digital arithmetic processing unit 2 is configured to vary the DC voltage 10a + 104 at the absolute value of the PCX-encoded input signal 1. First, at time to, the digital arithmetic processing device 2
detects the peak value, 4 (value before At delay), and DAC4b
Output to . The error amplifier 12 uses a reference signal having a peak value A to generate a DC voltage of 10 g.
In order to increase the current by 10A, the pulse width of the pulse width control circuit 11 is varied. The switching power supply 10 varies the voltage based on the pulse width. Next, the music signal is delayed by a predetermined delay time At, and the music signal is delayed by a predetermined delay time At. A is output to the DAC 4G as a music signal. Digital calculation salt treatment equipment 2
detects the peak value A before jt delay at time t0, and then returns to time t. After detecting the peak value A after Ijt delay at +(th-t,), the first zero cross is detected. Note that this t is given by writing to and reading from the RAM 5. After that, time to +( ta −
t a ) to detect the next peak value B between time t. In this embodiment, time 1. The DC voltage 10a + 1OA due to the peak value A is maintained until time 1, and the DC voltage 10a * 10b due to the peak value B is maintained from time 1.
It is held for a time At. However, the peak value 1B takes 4t
If a signal 1 \ greater than B is input while holding the peak value, k
Ru.

According to this embodiment, since delays and calculations are performed on PCM encoded music signals, the deterioration in audio performance is determined by I) the performance of the AC4m alone;
Even with the current commercially available DACs, sufficiently satisfactory performance can be obtained. The delay time 4t can be managed by the digital arithmetic processing unit 2, and by controlling the address of the RAM 5, the DC voltage 10g. 4t can be changed arbitrarily according to the rise characteristics of 10A, and the position of the peak value of the music signal can be managed by address, so the DC voltage 1
Since the start-up timing and fall-down timing of 0α and 10b can be reliably controlled, saturation of the music signal at the power amplification stage can be prevented. In addition, the envelope line signal can also be varied in conjunction with the volume adjustment volume 6, so no matter how the volume is varied, the envelope mw pressure signal can be varied in synchronization with the volume of the music signal. possible, DC voltage 10
α. This may cause an error in the control of 10t. In addition, by providing the voltage limiter circuit 5, the maximum DC voltage 1 that satisfies the maximum rated output (according to the ohm value of the speaker (load 9)) is determined by the load impedance identification signals 7a and 7k.
0ae10A can be set, preventing deterioration of power efficiency at low load impedance and saturation at high load impedance. In this embodiment, the load impedance classification signal 7a. We have prepared two types of 7k, but of course it is possible to increase the number depending on the specifications (ohm value of the speaker).

According to this embodiment, the conventional DC voltage of 10 g. ±10A
VCC, load 9 as RL, regeneration scar number 13 as rPth
e, DC voltage 1oα. according to the invention. 1oh from Figure 2, if it is ±[ai/p+b''J, then the loss of the conventional power amplification element is, and the loss of the power amplification element according to this embodiment is.The above two equations are It is shown in Fig. 4. From Fig. 4, the improvement effect of this embodiment is clear.Generally, the thermal design of an electric amplifier element is performed using a tone burst wave for the signal at the maximum rated output. Although this is done with a 1/1o output, it is possible to obtain very effective fx results compared to conventional methods.

〔Effect of the invention〕

According to the present invention, it is possible to manage the delay time and detect the peak value (maximum value of the signal waveform) using digital arithmetic processing, so that the DC voltage applied to the voltage amplification element can be can be controlled optimally with respect to the level of the reproduced signal, improving power efficiency. Also, the volume of sea bream is well adjusted. - Since the envelope can be variably controlled in conjunction with the system, it is possible to easily supply a DC voltage that corresponds to fluctuations in the volume adjustment polynomial. Since the voltage level can be varied, power efficiency is often degraded by load impedance.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. FIG. 2 is a circuit block diagram of an embodiment of the present invention.
FIG. 3 is a characteristic diagram showing the relationship between the envelope voltage and the DC voltage applied to the power amplifier dI4A element. FIG. 4 is a waveform diagram showing the waveform of the reproduction signal and the DC voltage applied to the power amplifying element. FIG. 3 is a characteristic diagram showing the relationship between the output voltage and the loss of the power amplifying element in the conventional method. 1... PCM-encoded music signal 2...-Digital processing unit 3...・・・・・・・・・RA
M4α, 4A... DAC 6... Volume adjustment volume 8... Power amplification element 15.
・・・・・・・・・Voltage limit circuit 7α, 7b・
...1B LVJ with load impedance identification signal

Claims (1)

[Claims] 1. An amplifier device that performs digital/analog conversion on a PCM-encoded input signal, amplifies power, and outputs the amplified output to a load, comprising: a power amplification element that supplies an amplified output to the load; A DC power supply device that supplies power to the amplification element, and a first digital/
After converting to an analog quantity via an analog converter, the first
The PCM-encoded input signal is outputted as a maximum value detection signal through the volume of the input signal, and the PCM-encoded input signal is delayed for a predetermined period of time by writing and reading the input signal into the memory, and then outputting it as a maximum value detection signal through the second digital/analog converter. a processing device that converts it into an analog quantity and further inputs it to the power amplification element via a second volume; and a voltage limit that receives the maximum value detection signal from the first volume and limits the maximum voltage and outputs it. circuit, and a power supply control device that controls the DC power supply device that supplies power to the power amplification element so that power loss in the power amplification element is minimized according to an output signal from the voltage limit circuit. An amplifying device characterized by: 2. In the amplifier device according to claim 1, when the processing device takes in the PCX-encoded input signal and detects the maximum amplitude value for each certain section of the signal waveform,
The maximum amplitude value is held at least for a period equivalent to the delay time given by writing and reading the PCM-encoded input signal into the memory, and if an even larger amplitude value is detected within the certain interval, the maximum amplitude value is held immediately. An amplifying device comprising a processing device configured to hold the amplifying device. 3. The amplification device according to claim 1, wherein the first volume and the second volume are volumes that interlock with each other. 4. The amplifier device according to claim 1, wherein the voltage limit circuit comprises a voltage limit circuit that varies the maximum voltage to be limited according to the impedance of the load.