GB2119189A - Gain control arrangement - Google Patents

Gain control arrangement Download PDF

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Publication number
GB2119189A
GB2119189A GB08304397A GB8304397A GB2119189A GB 2119189 A GB2119189 A GB 2119189A GB 08304397 A GB08304397 A GB 08304397A GB 8304397 A GB8304397 A GB 8304397A GB 2119189 A GB2119189 A GB 2119189A
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United Kingdom
Prior art keywords
signal
means
digital signal
gain control
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08304397A
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GB2119189B (en
GB8304397D0 (en
Inventor
Tsuneo Furuya
Katsuaki Tsurushima
Hirohito Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
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Sony Corp
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Filing date
Publication date
Priority to JP2483082A priority Critical patent/JPS58142614A/en
Application filed by Sony Corp filed Critical Sony Corp
Publication of GB8304397D0 publication Critical patent/GB8304397D0/en
Publication of GB2119189A publication Critical patent/GB2119189A/en
Application granted granted Critical
Publication of GB2119189B publication Critical patent/GB2119189B/en
Application status is Expired legal-status Critical

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Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H03G3/3026Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being discontinuously variable, e.g. controlled by switching
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10527Audio or video recording; Data buffering arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/24Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3089Control of digital or coded signals

Abstract

A gain control arrangement is used for reproducing digital signals obtained by analog-to-digital conversion of analog audio signals, such as on reproduction from a digital audio disc (1). The digital signal SD2 obtained is delayed by a circuit (4). Utilizing the delay time, the components of the reconverted analog signal SA which exceed a predetermined level are suppressed in response to a signal Sp from a peak value detector (6) which functions to control the gain of an amplifier (8). <IMAGE>

Description

SPECIFICATION Gain control devices This invention relates to gain control devices, and more particularly to gain control devices suitable for use when reproducing a digital signal obtained by analog-to-digital (A/D) conversion of an analog audio signal.

A digital audio disc (DAD) has a low signalto-noise ratio and a wide dynamic range as compared with conventional analog audio discs such as long-playing record (LP) discs.

When a comparison is made between a conventional LP disc and a DAD, an LP disc has a maximum dynamic range of about 70 dB, as may be seen from the broken line in Fig. 1 of the accompanying drawings, and this maximum dynamic range can only be obtained in an intermediate frequency range around 1 kHz. The dynamic range of the LP disc decreases to 40 dB in the high and low frequency ranges. In contrast to this, a DAD has a wide dynamic range, as may be seen from the alternate long and short dashed line in Fig. 1.

However, when signals are reproduced from a DAD having such a wide dynamic range and are amplified in a conventional audio system for reproduction by a loudspeaker, extra power is applied to the loudspeaker, which may result in damage to the loudspeaker.

Thus, when signals having peak levels higher than those of conventional cases are supplied to a power amplifier, and when the volume control is set to the same level position as in the conventional cases, the input signal waveforms are clipped in a complex manner resulting in reproduction distortion. The clipped waves include strong high-frequency components and these may cause damage to a loudspeaker, particularly to a tweeter.

According to the present there is provided a gain control device comprising: detecting means for detecting a predetermined value from data of a digital signal obtained by conversion of an analog signal; delaying means for delaying the digital signal; converting means for converting the digital signal from said delaying means into an analog signal; and gain controlling means for controlling a gain of the analog signal from said converting means in accordance with a detection signal from said detecting means.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a view showing the differences in the dynamic range of a DAD and an LP disc; Figure 2 is a block diagram of a first embodiment of gain control device according to the invention; Figure 3A and 3B show waveforms of a reproduced signal in which components exceeding a predetermined level are not suppressed, and of reproduced signals in which such components are suppressed; Figure 4 is a block diagram of a second embodiment of gain control device according to the invention; Figure 5 is a view showing details of a peak detector in the second embodiment; Figure 6 is a block diagram of a third embodiment of gain control device according to the invention;; Figure 7 is a view showing the details of a delay line and a digital gain control circuit in the third embodiment; and Figure 8 is a circuit diagram showing a modification of the digital gain control circuit of Fig. 7.

In the first embodiment shown in Fig. 2, digital signals obtained by A/D conversion of analog audio signals are modulated in accordance with the "Non Return to Zero-i" (NRZ 1) method and are recorded on a DAD 1.

Such digital signals may be obtained by sampling analog audio signals at a predetermined frequency, quantizing the samples and converting them to 1 6-bit data words, and then encoding the data words in accordance with the "Cross Interleave Reed Solomon Code" (CIRC) and "Eight to Fourteen Modulation" (EFM) methods.

Encoding in accordance with the CIRC method is performed to correct most of the high-density errors such as scratches on a disc.

The EFM method is a modulation method in which sixteen bits are divided into more and less significant 8-bit groups, respectively, and each group of eight bits is converted into a 1 4-bit pattern. Modulation in accordance with the EFM method is performed so that digital signals may be recorded with the minimum amount of waveform distortion and so that DC components may not be included in the recorded signals.

The digital signals recorded on the DAD 1 are read out by an optical pick-up or the like and are supplied to an EFM demodulator 2.

Using the clock and sync signals extracted and separated respectively from the input signal, the EFM demodulator 2 performs EFM demodulation by reconverting each 14-bit pattern into the original 8-bit group, and recombining the more and less significant 8-bit groups to obtain the original 1 6-bit data word.

A digital signal SD1 thus obtained is supplied to a memory/operation circuit 3 including a random access memory (RAM).

The memory/operation circuit 3 performs the following operations: (A) To write and store the digital signal SD1 in the RAM or to read it out from the RAM, and to control the RAM.

(B) To detect and correct errors in 1 6-bit words in accordance with the CIRC method.

(C) To interpolate, a "Bad" data word which has not been corrected in accordance with CIRC method, with a correct "Good" data word.

(The timings of read/write operations of the digital signal SD1 in or from the RAM are controlled in accordance with clock pulses from a clock generator 5.) A digital signal SD2 is then obtained from the memory/operation circuit 3. The digital signal SD2 is a 1 6-bit data word which has been corrected for errors and which has been interpolated. The digital signal SD2 thus obtained is supplied to a delay line 4. The delay line 4 delays the input digital signal SD2 to a time point after detection of the peak value at a peak detector 6. During this time delay, an amplifier 8 acting as an analog gain controlling means can control the gain in accordance with peak detection result by the peak detector 6.

In response to the clock pulses from the clock generator 5, the delay line 4 sequentially shifts the 1 6-bit data word or the digital signal SD2 in a series circuit of latch registers.

Alternatively, delayed read-out may be performed from the RAM by a modulo-M address counter which operates in accordance with clock pulses from the clock generator 5.

Time delay of the input signal which will not cause any distortion in the output may be performed if the frequency of the clock pulses supplied to the delay line 4 from the clock generator 5 is an integral multiple of the sampling frequency.

A digital signal a SD3 from the delay line 4 is supplied to a digital-to-analog (D/A) converter 7 to be reconverted into the analog audio signal. An analog audio signal SA thus obtained is produced from an output terminal 9 through the amplifier 8. A loudspeaker is connected to the output terminal 9 through a pre-amplifier and a power amplifier (not shown).

Meanwhile, the digital signal SD2 from the memory/operation circuit 3 is also supplied to the peak detector 6.

The peak detector 6 detects the peak value of the digital signal SD2 to see if the peak value exceeds a predetermined level to cause undesirable clipping. On the basis of the data of the digital signal SD2, the peak detector 6 detects the slope of the audio signal or the like thereby to detect the peak value of the component exceeding the predetermined level.

A detection signal SP from the peak detector 6 is supplied to the amplifier 8 to decrease the gain of the amplifier 8. Thus, the peak component of an analog audio signal SA from the D/A converter 7 is suppressed.

If the data sampling frequency is set at 44.1 kHz and the delay time of the delay line 4 is set to be: 1 /44.1 kHz X 4 which is approximately 90 microseconds the gain of the amplifier 8 is controlled so that the peak component is suppressed before the audio signal components in the high frequency range of about 10kHz abruptly increase in level. Since the pulse width of a pulse having a high frequency of 1 0kHz is 100 microseconds, the peak value is detected before this pulse reaches the amplifier 8. The peak component of the pulse is suppressed by the detection signal SP from the peak detector 6. The detection signal SP may, for example, be supplied to an electronic volume control or the like having a good response time characteristic to perform gain control of the audio signal.The electronic volume control may control the feedback amount of the amplifier 8 or the like. A mechanical volume control may also be used where it is possible.

The above will now be described with reference to the waveforms shown in Figs. 3A and 3B, wherein Fig. 3A shows the waveform of the signal in which the peak component is not suppressed, and Fig. 3B shows the waveform of the signal in which the peak component is suppressed from the time of a weak signal before the peak component is received. In this manner, an abrupt level change is prevented so providing smooth peak component suppression, and thereby allowing production of sounds of good quality.

The gain of the amplifier 8 which has been controlled in this manner by an electronic or mechanical volume control can either gradually be restored to the original value or be left unchanged. However, the latter is preferable to reduce distortion along the time base.

In the second embodiment shown in Fig. 4, a digital signal S'D2 prior to interpolation at an interpolator 10 of a memory/operation circuit 3' is supplied to a peak detector 6' for peak detection. The interpolator 10 serves to interpolate the data word which has not been corrected in accordance with the CIRC method. The digital signal S'D2 is a digital signal which includes a flag "Good" for the data word which has been corrected and a flag "Bad" for the data word which has not been corrected. The digital signal S'D2 with such a flag is supplied to the interpolator 10.

The interpolator 10 discriminates between the "Good" and "Bad" flags, and interpolates the data with the flag "Bad" with the data with the flag "Good". Meanwhile, the peak detec tor 6' detects the peak value of the audio signal on the basis of the data word including a flag "Good" of the digital signal S'D2. More specifically, the peak detector 6' selects the data with flag "Good" and produces a detection signal SP similar to that obtained in the first embodiment described above. In this second embodiment, the peak value of the digital signal is detected before the digital signal is interpolated. Therefore, while the interpolator 10 performs interpolation, a desired time delay from the time point of peak detection is obtained.Therefore, the interpolator 10 also serves as a delay line and the second embodiment does not require a delay line unlike the first embodiment.

An output signal S'D3 from the interpolator 10 is supplied to a D/A converter 7 and an audio analog signal SA therefrom is supplied to an amplifier 8.

In a digital signal, a certain bit corresponds to the peak value of the analog audio signal, and a level exceeding a certain level does not exist in the digital signal. Therefore, if the volume level which has been decreased in accordance with the gain control in first and second embodiment is left unchanged, one setting operation of the volume level against the peak value prevents clipping afterwards.

In this sense, the gain control device also serves as an automatic volume level setter.

In the third embodiment shown in Fig. 6, gain control is performed in a digital manner.

A digital signal SD3 which has been delayed by a delay line 4 is supplied to a gain control circuit 11. The digital gain control circuit 11 performs gain control in accordance with a detection signal SP from a peak detector 6. A digital signal which has been gain-controlled by the digital gain control circuit 11 is supplied to a D/A converter 7.

Fig. 7 shows an example of a circuit configuration of the delay line 4 and the digital gain control circuit 11. The delay line 4 consists of n stages R1 to Rn of a shift register. Shift clocks of the data sampling frequency, for example, 44.1 kHz are supplied to the respective shift register stages R1 to Rn so as to receive and produce the 1 6-bit data word or the digital signal SD2 in a parallel manner. The delay time of the delay line 4 is determined by the number n of shift register stages, which is set, for example, to be 100.

A digital signal SD3 from the delay line 4 is supplied to the digital gain control circuit 11 comprising a logic circuit A.

The logic circuit A can be switched between one mode in which the signal SD3 from the delay line 4 is supplied to the amplifier 8 without modification and the other mode in which the signal SD3 is shifted by one bit towards the least significant bits (LSB) to add the most significant bit (MSB) of "0" and is then supplied to the amplifier 8. A detection signal SP from the peak detector 6 is supplied to the logic circuit A through a terminal 12.

When the peak value of the audio signal is discriminated to exceed a predetermined level in accordance with the detection signal SP, the logic circuit A shifts the signal SD3 from the delay circuit 4 by one bit towards the LSB to add the MSB of "O". The output signal from the logic circuit A is supplied to an amplifier 8' through a D/A converter 7. In this case, the level of the signal SD3 is reduced to half. Generally stated, shift by m bits results in a reduction in level by 1 /2m.

Alternatively, the logic circuit A may be omitted. In this case, the final shift register stage Rn in the delay line 4 is controlled such that the storage contents therein are shifted towards the LSB by m bits to allow level reduction by 1 /2m.

Fig. 8 shows another example of the digital gain control circuit 11 which comprises a ROM 13. The ROM 13 stores a plurality of types of data conversion tables for attenuating the level of the digital signal SD3 (1 6-bit data word). The signal SD3 from the delay line 4 is supplied as an address signal to the ROM 13, while an address for selecting the data conversion table is supplied to the ROM 13 from a logic circuit B designated by reference numeral 14.

The logic circuit B receives a detection signal SP from a peak detector 6 as well as a detection signal representing the maximum power and a detection signal representing a volume level position from a power amplifier through terminals 1 5 and 16, respectively.

Since the clipping level of the reproduced waves changes in accordance with maximum power and the volume level position of the power amplifer used, the degree of level attenuation or gain control is adjusted in accordance with this clipping level. The detection signal representing the maximum power is supplied from a generator which generates a signal of a level corresponding to the maximum power of the power amplifier. The detection signal representing the volume level position is supplied from a potentiometer which is synchronous with volume level. In accordance with the data on the maximum power and the volume level position of the power amplifier thus obtained, the logic circuit B determines a data conversion table to be used.When the peak value of the audio signal is detected by the peak detector 6, the signal SD3 is attenuated in level in acordance with a predetermined ratio and is then supplied to the D/A converter 7 through a multiplexer 17.

However, when the signal SD2 does not exceed the predetermined level, it is supplied without modification from the ROM 13 to the D/A converter 7 through the multiplexer 17.

When the peak value of the audio signal is not detected, the signal need not be supplied to the ROM 13. Therefore, the multiplexer 17 is incorporated to allow selection between the signal SD2 from the delay line 4 and the signal SD2 which is attenuated in level and which is read out from the ROM 13. The multiplexer 17 is controlled by a signal from the peak detector 6 which is supplied through the logic circuit B.

Although the invention has been described with reference to reproduction system of a DAD, it is similarly applicable to various types of digital signal transmission systems.

Claims (12)

1. A gain control device comprising: detecting means for detecting a predetermined value from data of a digital signal obtained by conversion of an analog signal; delaying means for delaying the digital signal; converting means for converting the digital from said delaying means into an analog signal; and gain controlling means for controlling a gain of the analog signal from said converting means in accordance with a detection signal from said detecting means.
2. A device according to claim 1 wherein said gain controlling means comprises digital gain controlling means for controlling the digital signal from said delaying means.
3. A device according to claim 1 wherein said gain controlling means comprises analog gain controlling means for controlling the analog signal from said converting means.
4. A device according to claim 1 further comprising error detecting/correcting means for detecting and correcting an error of the digital signal.
5. A device according to claim 4 wherein said delay means also serves as an interpolating means for interpolating the digital signal which is not corrected by said error detecting/correcting means with a correct digital signal.
6. A device according to claim 5 wherein the digital signal from said error detecting/correcting signal includes a flag "Good" if the digital signal is corrected and a flag "Bad" if the digital signal is not corrected; and the detection signal from said detecting means is obtained on the basis of the digital signal including the flag "Good".
7. A gain control device substantially as hereinbefore described with reference to Fig.
2 of the accompanying drawings.
8. A gain control device substantially as hereinbefore described with reference to Fig.
4 of the accompanying drawings.
9. A gain control device substantially as hereinbefore described with reference to Figs.
4 and 5 of the accompanying drawings.
10. A gain control device substantially as hereinbefore described with reference to Fig.
6 of the accompanying drawings.
11. A gain control device substantially as hereinbefore described with reference to Figs.
6 and 7 of the accompanying drawings.
12. A gain control device substantially as hereinbefore described with reference to Figs.
6 and 8 of the accompanying drawings.
GB08304397A 1982-02-18 1983-02-17 Gain control arrangement Expired GB2119189B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2483082A JPS58142614A (en) 1982-02-18 1982-02-18 Gain controlling device

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GB8304397D0 GB8304397D0 (en) 1983-03-23
GB2119189A true GB2119189A (en) 1983-11-09
GB2119189B GB2119189B (en) 1985-08-14

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JP (1) JPS58142614A (en)
KR (1) KR910002980B1 (en)
CA (1) CA1214998A (en)
DE (1) DE3305662C2 (en)
FR (1) FR2521758B1 (en)
GB (1) GB2119189B (en)
NL (1) NL8300618A (en)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700362A (en) * 1983-10-07 1987-10-13 Dolby Laboratories Licensing Corporation A-D encoder and D-A decoder system
EP0911712A1 (en) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Corrected servo control signal in a servo control loop
EP0911713A2 (en) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Corrected servo control signal in a servo control loop
GB2378064A (en) * 2001-03-12 2003-01-29 Simoco Int Ltd A feed-forward signal level control arrangement with a delay in the signal path
WO2011143040A1 (en) * 2010-05-10 2011-11-17 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
US8687471B2 (en) 2010-05-10 2014-04-01 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
US9525940B1 (en) 2014-03-05 2016-12-20 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system
US9543975B1 (en) 2015-12-29 2017-01-10 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system with low-pass filter between paths
US9584911B2 (en) 2015-03-27 2017-02-28 Cirrus Logic, Inc. Multichip dynamic range enhancement (DRE) audio processing methods and apparatuses
US9596537B2 (en) 2014-09-11 2017-03-14 Cirrus Logic, Inc. Systems and methods for reduction of audio artifacts in an audio system with dynamic range enhancement
GB2544822A (en) * 2015-11-25 2017-05-31 Cirrus Logic Int Semiconductor Ltd Systems and methods for preventing distortion due to supply-based modulation index changes in an audio playback system
US9680488B2 (en) 2014-04-14 2017-06-13 Cirrus Logic, Inc. Switchable secondary playback path
US9762255B1 (en) 2016-09-19 2017-09-12 Cirrus Logic, Inc. Reconfiguring paths in a multiple path analog-to-digital converter
US9774342B1 (en) 2014-03-05 2017-09-26 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system
US9780800B1 (en) 2016-09-19 2017-10-03 Cirrus Logic, Inc. Matching paths in a multiple path analog-to-digital converter
US9813814B1 (en) 2016-08-23 2017-11-07 Cirrus Logic, Inc. Enhancing dynamic range based on spectral content of signal
US9831843B1 (en) 2013-09-05 2017-11-28 Cirrus Logic, Inc. Opportunistic playback state changes for audio devices
US9880802B2 (en) 2016-01-21 2018-01-30 Cirrus Logic, Inc. Systems and methods for reducing audio artifacts from switching between paths of a multi-path signal processing system
US9917557B1 (en) 2017-04-17 2018-03-13 Cirrus Logic, Inc. Calibration for amplifier with configurable final output stage
US9929703B1 (en) 2016-09-27 2018-03-27 Cirrus Logic, Inc. Amplifier with configurable final output stage
US9959856B2 (en) 2015-06-15 2018-05-01 Cirrus Logic, Inc. Systems and methods for reducing artifacts and improving performance of a multi-path analog-to-digital converter
US9967665B2 (en) 2016-10-05 2018-05-08 Cirrus Logic, Inc. Adaptation of dynamic range enhancement based on noise floor of signal
US9998826B2 (en) 2016-06-28 2018-06-12 Cirrus Logic, Inc. Optimization of performance and power in audio system
US10008992B1 (en) 2017-04-14 2018-06-26 Cirrus Logic, Inc. Switching in amplifier with configurable final output stage

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JPH0772971B2 (en) * 1988-10-05 1995-08-02 パイオニア株式会社 Play level setting of the disc player

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Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700362A (en) * 1983-10-07 1987-10-13 Dolby Laboratories Licensing Corporation A-D encoder and D-A decoder system
EP0911712A1 (en) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Corrected servo control signal in a servo control loop
EP0911713A2 (en) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Corrected servo control signal in a servo control loop
EP0911713A3 (en) * 1997-10-21 2000-04-12 Deutsche Thomson-Brandt Gmbh Corrected servo control signal in a servo control loop
US6445529B1 (en) 1997-10-21 2002-09-03 Thomson Licensing, S.A. Corrected servo control signal in a servo control loop
GB2378064A (en) * 2001-03-12 2003-01-29 Simoco Int Ltd A feed-forward signal level control arrangement with a delay in the signal path
WO2011143040A1 (en) * 2010-05-10 2011-11-17 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
CN102893334A (en) * 2010-05-10 2013-01-23 马维尔国际贸易有限公司 Method and apparatus for offset and gain correction
US8630155B2 (en) 2010-05-10 2014-01-14 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
US8687471B2 (en) 2010-05-10 2014-04-01 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
US9001631B2 (en) 2010-05-10 2015-04-07 Marvell World Trade Ltd. Method and apparatus for offset and gain correction
CN102893334B (en) * 2010-05-10 2016-04-13 马维尔国际贸易有限公司 Methods and apparatus for correction of offset and gain
US9831843B1 (en) 2013-09-05 2017-11-28 Cirrus Logic, Inc. Opportunistic playback state changes for audio devices
US9774342B1 (en) 2014-03-05 2017-09-26 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system
US9525940B1 (en) 2014-03-05 2016-12-20 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system
US9680488B2 (en) 2014-04-14 2017-06-13 Cirrus Logic, Inc. Switchable secondary playback path
US9596537B2 (en) 2014-09-11 2017-03-14 Cirrus Logic, Inc. Systems and methods for reduction of audio artifacts in an audio system with dynamic range enhancement
US9998823B2 (en) 2014-09-11 2018-06-12 Cirrus Logic, Inc. Systems and methods for reduction of audio artifacts in an audio system with dynamic range enhancement
US9584911B2 (en) 2015-03-27 2017-02-28 Cirrus Logic, Inc. Multichip dynamic range enhancement (DRE) audio processing methods and apparatuses
US9959856B2 (en) 2015-06-15 2018-05-01 Cirrus Logic, Inc. Systems and methods for reducing artifacts and improving performance of a multi-path analog-to-digital converter
US9955254B2 (en) 2015-11-25 2018-04-24 Cirrus Logic, Inc. Systems and methods for preventing distortion due to supply-based modulation index changes in an audio playback system
GB2544822A (en) * 2015-11-25 2017-05-31 Cirrus Logic Int Semiconductor Ltd Systems and methods for preventing distortion due to supply-based modulation index changes in an audio playback system
US9807504B2 (en) 2015-12-29 2017-10-31 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system with low-pass filter between paths
US9543975B1 (en) 2015-12-29 2017-01-10 Cirrus Logic, Inc. Multi-path analog front end and analog-to-digital converter for a signal processing system with low-pass filter between paths
US9880802B2 (en) 2016-01-21 2018-01-30 Cirrus Logic, Inc. Systems and methods for reducing audio artifacts from switching between paths of a multi-path signal processing system
US9998826B2 (en) 2016-06-28 2018-06-12 Cirrus Logic, Inc. Optimization of performance and power in audio system
US9813814B1 (en) 2016-08-23 2017-11-07 Cirrus Logic, Inc. Enhancing dynamic range based on spectral content of signal
US9780800B1 (en) 2016-09-19 2017-10-03 Cirrus Logic, Inc. Matching paths in a multiple path analog-to-digital converter
US9762255B1 (en) 2016-09-19 2017-09-12 Cirrus Logic, Inc. Reconfiguring paths in a multiple path analog-to-digital converter
US9929703B1 (en) 2016-09-27 2018-03-27 Cirrus Logic, Inc. Amplifier with configurable final output stage
US9967665B2 (en) 2016-10-05 2018-05-08 Cirrus Logic, Inc. Adaptation of dynamic range enhancement based on noise floor of signal
US10008992B1 (en) 2017-04-14 2018-06-26 Cirrus Logic, Inc. Switching in amplifier with configurable final output stage
US9917557B1 (en) 2017-04-17 2018-03-13 Cirrus Logic, Inc. Calibration for amplifier with configurable final output stage

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DE3305662A1 (en) 1983-09-08
KR840003937A (en) 1984-10-04
JPS58142614A (en) 1983-08-24
FR2521758A1 (en) 1983-08-19
KR910002980B1 (en) 1991-05-11
GB2119189B (en) 1985-08-14
GB8304397D0 (en) 1983-03-23
CA1214998A (en) 1986-12-09
DE3305662C2 (en) 1995-05-24
FR2521758B1 (en) 1985-02-08
NL8300618A (en) 1983-09-16
CA1214998A1 (en)

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