CA1214998A - Digitally processed gain control device - Google Patents
Digitally processed gain control deviceInfo
- Publication number
- CA1214998A CA1214998A CA000421039A CA421039A CA1214998A CA 1214998 A CA1214998 A CA 1214998A CA 000421039 A CA000421039 A CA 000421039A CA 421039 A CA421039 A CA 421039A CA 1214998 A CA1214998 A CA 1214998A
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- Prior art keywords
- signal
- digital signal
- gain control
- digital
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims abstract description 20
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 230000005236 sound signal Effects 0.000 abstract description 15
- 230000007423 decrease Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000005070 sampling Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 101710162371 Dihydroxy-acid dehydratase 1 Proteins 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 101100496106 Mus musculus Clec2f gene Proteins 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
- H03G3/3026—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being discontinuously variable, e.g. controlled by switching
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/24—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Control Of Amplification And Gain Control (AREA)
- Analogue/Digital Conversion (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A gain control device for reproducing digital signals obtained by A/D conversion of analog audio signals, the device comprising: a detector for detecting the appearance of a digital value exceeding a predetermined value from data of a digital signal obtained by conversion of an analog signal, a delay for delaying the digital signal, a convertor for converting the digital signal from the delay into an analog signal; and a gain control for controlling a gain of the analog signal from the convertor to as to decrease in accordance with a detection signal from the said detector.
A gain control device for reproducing digital signals obtained by A/D conversion of analog audio signals, the device comprising: a detector for detecting the appearance of a digital value exceeding a predetermined value from data of a digital signal obtained by conversion of an analog signal, a delay for delaying the digital signal, a convertor for converting the digital signal from the delay into an analog signal; and a gain control for controlling a gain of the analog signal from the convertor to as to decrease in accordance with a detection signal from the said detector.
Description
3~
B~CKGRC)UND ~F THE INV~NTION
Field of the Invention:
This invention relates to gain control devices, and more particularly to gain control devices suitable for use when reproducing a digital signal obtained by analog to-digital IA/D) conversion of an analoy audio signal.
A digital audio disc (~AD3 has a low signal-to-noise ratio and a wide dynamic range as compared with con-ventional analog audio discs such as long-playinq record (LjP) discs.
BRIEF DESC~IPTION OF THE DRAWIN~S
Fig. 1 is a view showing the differenc~s in the dynamic range of a DAD and an LPD;
Fig~ 2 is a block diagram of a gain control device according to the first embodiment of the present invention;
Figs. 3(a~ and 3(b) show waveforms of a reproduced signal in which components exceeding a predetermined level are not suppressed and of reproduced sl~nals in which such components are suppressed;
Fig. 4 is a block diagram of a gain control device according to the secona embodiment of the present invention;
~ ig. 5 is a view showing details o a configuration of a peak detector according to the second embodiment of the present invention;
Fig. 6 is a block diagram of a gain control device according to the third embodiment of the present invention;
Fig~ 7 is a view showing the details of a delay line and a digital gain control circuit accordiny to the third embodiment; and Fig. 8 is a circuit diagram showing a modification of the digital gain control circuit according to the third embodiment of the present invention.
When a comparison is made between a conventional LP disc and a DAD, an LP disc has a maximum dynamic range of about 7G dB, as may be seen from the broken line in Figure 1 of the accompanying drawings, and this maximum dynamic range can only be obtained in an intermediate frequency range around 1 kHz. The dynamic range of the LP disc decreases to 40 dB in the high and low frequency ranges. In contrast to this, a DA~ has a wide dynamic range, as may be seen from the alternate long and short dashed line in Figure 1.
However, when signals are reproduced from a DAD
having such a wide dynamic range and are amplified in a conventional audio system for reproduction by a loudspeaker, extra power is applied to the loudspeaker, which may result in damage to the loudspeaker. Thus, when signals having peak levels higher than those of conventional cases are supplied to a power amplifier, and when the volume control is set to the same level position as in the conven~ional cases, the input signal wave~orms are clipped in a complex manner resulting in reproduction distortion. The clipped waves include strong high-frequency components and these :"
~ - 2 -may cause damage to a loudspeaker, particularly to a tweeter.
OBJECTS AND SIJMMARY OF THE INVENTION
.. . . .
According to the present invention there is provided a gain control device comprising:
detector means for detecting a dlgi-tal value exceeding a predetermined value in data of a digital signal obtained by conversion of an analog signal;
delay means for delaying the digital signal;
converter means for converting the digital signal from said dela~ means into an output analog signal; and gain control means for decreasing the gain of -the output analog signal in accordance with a detection signal from said deteclor means.
DETAIL~D DESCRIPTION OF THE ~REFERRED EMBODIMENTS
. .
I'he preferred embodiments of the present invention will now be described with reference tO the accompanying drawings.
Fig. 2 is a block diagram of a gain control device according to the first embodiment of the present invention.
In the first embodiment shown in Figure 2, digital signals obtained by A/D conversion of analog audio signals are modulated in accordance with the "Non Return to ~ero-l"
(NRZ-l) method and are recorded on a DAD 1. Such digital signals may be obtained by sampling analog audio signals at a predetermined frequency, quantizing the samples and converting them to 16 bit data woxds, and then encoding the data words in accordance with the "Cross Interleave -,~
~ 3 ~ 36~
Reed Solomon Code" (CIRC) and "~ight to ~ourteen ~dulation (EFM) methods.
Encoding in accordance with the ClRC method is performed to correct most of a high density error such as a scratch on a disc.
The EFM method is a modulation method in which sixteen bits are divided into more and less significant 8-bit groups, respectively, and each group of eiyht bits is converted inlo a 14-bit pattern. Modulation in accordance with the EFM method is performed so that digital signals may be recorded with the minimum amount of waveform distortion and so that DC components ~ay not be included in the recorded signals.
The digital signals recorded on the DAD 1 are read out hy an optical pickup or the like and are supplied to an EFM demodulator 2. Using the clock and _ 4 -sync signals extracted and separated respectively from the input signal, the EFM demodulator 2 per~orms ~FM
demodulation by reconverting each la-bit pattern into the original 8-bit group, and recombining the more and less significant 8-bit groups to obtain the original 16-bit data word. A digital signal SDl thus obtained is supplied to a memory/operation circuit 3 having a RAM (Random Access Memory) and the like.
The memory/operation circuit 3 performs the following operations:
(A) To write and store the digital signal SDl in the RAM,or ~t~,read it D~t f~om the RAM,~and to control the RAM.
(B) To detect and correct errors in 16-bit words in accordance wi-th the CIRC method.
(C) To interpolate, a "Bad" data word which has not been corrected in accordance with the CIRC
method, with another correct "Good" data word.
(The timings of read/write operations of the digital signal SDl in or from the RAM are controlled in accordance with clock pulses from a clock generator 5.) A digital signal SD2 is then obtained ~rom the memory/operation circuit 3. The-digital signal SD2 is a 16-bit data word which has been corrected for errors and which has been interpolated. The digital signal SD2 thus obtained is supplied ~o a delay line 4.
The delay line 4 delays the input digital signal SD2 to a time point after detection of the peak value at a peak detector 6. During the time delayed in this manner, an amplifier 8 as an analog gain controlling means can con-trol the gain in accordance with the peak detection result by the peak detector 6.
In response to the clock pulses from the clock generator 5, the delay line 4 sequentially shifts the 16-bit data word or the digital signal SD2 in a series circuit of latch registers. Alternatively, delayed readout may be performed from the RA~ by a modulo-M address counter which operates in accordance with the clock pulses from the clock generator 5.
Time delay o~ the input signal which may not cause any distortion in the output may be performed if the frequency of the clock pulses supplied to the delay line ~ from the clock generator 5 is an integer multiple of the sampling frequency.
A digital signal SD3 from the delay line 4 is supplied to a D/A converter 7 to be reconverted into the analog audio signal. An analog audio signal SA
thus obtained is produced from an output terminal 9 through the amplifier 8. A speaker is connected to the output terminal 9 through a preamplifier and a power amplifier of the user~
Meanwhile, the digital signal SD2 from the memory/operation circuit 3 is also supplied to the peak detector 6.
The peak detector 6 detects the peak value of the digital signal SD2 to see if the peak value exceeds a predetermined level to cause undesirable cLipping.
On the basis of the data of the digital signal SD~, the peak detector 6 detects the slope of the audio signal or the like to -thereby delect -the peak value of the component exceeding the predetermined level.
A detection signal Sp from the peak detector 6 is supp]ied to the amplifier 8 to decreace the gain of the amplifier 8. Thus, the peak component of an analog audio signal SA from the D/A converter 7 is suppressed.
If the da-ta sampling frequency is set at 44.1 kHz and the delay time of the delay line 4 is set to be 1/44.1 kHz x 4 . 90 ~sec, the gain of the amplifier 8 is controlled so that the peak component is suppressed before the audio signal components in the high frequency range o about 10 kHz abruptly increase in level. Since the pulse width of a pulse having a high frequency of 10 kHz is 100 ~sec, the peak value is detected before this pulse reaches the amplifier 8.
The peak component of the pulse is suppressed by the detection signal Sp from the peak detector 6. The detection signal Sp may, for example, be supplied to an electronic volume control or the like having a good response time characteristic to perform gain control of the audio signal. The electronic volume control may control the feedback amount of the amplifier 8 or the like. A mechanical volume control may also be used where it is possible.
The above will now be described with reference to the waveforms shown in Figs. 3(a; and 3(~), wherein Fig. 3(a) shows the waveform of the signal in which the peak component is not suppressed, and Fig. 3(b) shows -the waveform of the signal in which -the peak component is suppressed from a timing of a weak signal before ~he peak componen~ is received. In this manner, an abrupt level change is prevented to providè smooth peak component suppression, thereby allowing production of sounds of good quality.
The gain of the amplifier 8 which has been controlled in his manner by an electronic or mechanical volume control can either gradually be restored to the original value or be left unchanged.
However, the latter is preferable considering distortion along the time base.
Fig. 4 shows a block diagram o a gain control device according to the second embodiment of the present invention. The same reference numerals in Fig. 2 denote the same parts as in Fig. 1, and a detailed description will be omitted.
According to the second embodiment, a digital signal S D2 prior to interpolation at an interpola-tor 10 of a memory operation circuit 3' is supplied to a peak detector 6' for peak detection. The interpolator 10 serves to interpolate the data word which has not been corrected in accordance with the CIRC method. The digital signal S D2 is a digital signal which includes a flag "Good" for the data word which has been corrected and a flag l'Badl' for the data word which has not been corrected. The diyital signal S D2 with such a flag is supplied to the interpola-tor 10. The interpolator 10 discriminates between the "Good" and "Bad" flags, and interpolates the data with the flag "Bad" with the data with the flag "Good".
_ ~ _ 3; ~
Meanwhil~, the peak detector 6' de-tects the peak value of the audio signal on the basis o~ the data word including a flag "Good" of the digital signal S D2.
More specifically, the peak detector 6' selects the data with the flag "Good" and produces a detection signal Sp similar to that obtained in the first embodiment described above. In this embodiment, the peak value of the digital signal is detected before the digital signal is interpolated. Therefore, while the interpolator 10 performs lnterpolation, a desired time delay from the time point o peak detection is obtained. Therefore, the interpolator 10 also serves as a delay line and the second embodiment does not require a delay line as in the first embodiment.
An output signal S'D3 from the interpolator 10 is supplied to a D/A converter 7 and an audio analog signal SA therefrom is supplied to an amplifier 8.
In a digital signal, a certain bit corresponds to the peak value of the analog audio signal, and a level exceeding a certain level does not exist in the digital signal. Therefore, if the volume level which has been decreased in accordance with the gain control in the first and second embodiment is left unchanged, one setting operation of the volume level against the peak value prevents clipping afterwards.
In this sense, the gain control device of the present invention also serves as an automatic vo]ume level setter.
Fig. 6 is a block diagram of a gain control circuit of the third embodiment of the present L L~ ,~3 ~
invention~ The same reference numerals in Fig. 2 denote the same parts and a detailed descrip~ion thereof will be omitted.
According to the third embodiment, gain control is performed in a digital manner. A digital signal SD3 which has been delayed by a delay line 4 is supplied to a gain control circuit 11. The digital gain control circuit 11 performs gain control in accordance with a detection signal Sp from a peak detector 6. A digital signal which has been gain-controlled by the digital gain control circuit 11 is supplied to a D/A con~erter 7.
Fig. 7 shows an example of a circuit configuration of the delay line 4 and the digital gain control circuit 11. The delay line 4 consists of n stages of shift registers Rl to Rn. Shift clocks of the data sampling frequency, for example, 44.1 kHz are supplied to the respective shift registers Rl to Rn so as to receive and produce the 16-bit data word or the digital signal SD2 in a parallel manner. The delay time of the delay line 4 is determined by the number n of shift registers, which is set, for example, to be 100. A digital signal SD3 from the delay line 4 is supplied to the digital gain control circuit 11 comprising a logic circuit A.
The logic circuit A can be switched between one mode in which the signal SD3 from the delay line 4 is supplied to the amplifier 8 without modification and the other mode in which the signal SD3 is shifted by one bit toward the LSB to add the MSB of "O" and is then supplied to the amplifier 8. A detection signal Sp from -the peak detector 6 is supplied to the logic circuit A through a terminal 12. When the peak value of the audio signal is discriminated to exceed a predetermined level in accordance with the detection signal Sp, the logic circuit A shifts the signal SD3 from the delay circuit 4 by one bit toward the LSB to add the MSB of "0". The output signal from the logic circuit A is supplied to an amplifier 8' through a D/A
converter 7. In this case, the level of the signal SD3 is reduced to half. Generally stated, shift by m bits results in a reduction in level by l/2m.
~ lternatively, the logic-circuit A may be omitted. In this case, the inal shift register Rn in the delay line 4 is controlled such that the storage contents therein are shifted to the LSB by m bits to allow level reduction by l/2m.
Fig. 8 shows anot~er example of the digital gain control circuit 11 which comprises a ROM 13. The ROM 13 stores a plurality of types of data conversion tables for attenuating the level of the digital signal SD3 (16-bit data word). The signal SD3 from the delay line 4 is supplied as an address signal to the ROM 13, while an address for selecting the data converslon table is supplied to the ROM 13 from a logic circuit B designated by reference numeral 14.
The logic circuit B receives a detection signal Sp from a peak detector 6 as well as a detection signal representing the maximum power and a detection signal representing a volume level position from a power ampllfier -throu~h terminals 15 and 16, respectively. Since the clipping level of the reproduced waves changes in accordance with the maximum power and the volume level position of the power amplifier used, the degree of level attenuation or gain control is adjusted in accordance with this clipping level. The detection signal representing the maximum power is supplied from a generator which generates a signal of a level corresponding to the maximum power of the power amplifier. The detection signal representing the volume level position is supplied from a potentiometer which is synchronous with the volume level. In accordance with the data on the maximum power and the volume level position of the power amplifier thus obtained, the logic circuit B determines a data conversion table to be used. When the peak value of the audio signal is detected by the peak detectcr 6, the signal SD3 is attenuated in level in accordance with a predetermined ratio and is then supplied to the D/A converter 7 through a multiplexer 17.
However, when the signal SD2 does not exceed the predetermined level, it is supplied without modification from the ~OM 13 to the D/A converter 7 through the multiplexer 17. When the pea~ value of the audio signal is not detected, the signal need not be supplied to the ROM 13. Therefore, the multiplexer 17 is incorporated to allow selection between the signal SD2 from the delay line ~ and the signal SD2 which is attenuated in level and which is read ou-t from the ROM 13. The multiplexer l7 is controlled by a signal from the peak detector 6 which is supplied through the logic circuit s.
Although the present inventlon has been descxibed with reference to a reproduction system of a DAD, the present invention is similarly applicable to various types of digital signal transmission systems~
B~CKGRC)UND ~F THE INV~NTION
Field of the Invention:
This invention relates to gain control devices, and more particularly to gain control devices suitable for use when reproducing a digital signal obtained by analog to-digital IA/D) conversion of an analoy audio signal.
A digital audio disc (~AD3 has a low signal-to-noise ratio and a wide dynamic range as compared with con-ventional analog audio discs such as long-playinq record (LjP) discs.
BRIEF DESC~IPTION OF THE DRAWIN~S
Fig. 1 is a view showing the differenc~s in the dynamic range of a DAD and an LPD;
Fig~ 2 is a block diagram of a gain control device according to the first embodiment of the present invention;
Figs. 3(a~ and 3(b) show waveforms of a reproduced signal in which components exceeding a predetermined level are not suppressed and of reproduced sl~nals in which such components are suppressed;
Fig. 4 is a block diagram of a gain control device according to the secona embodiment of the present invention;
~ ig. 5 is a view showing details o a configuration of a peak detector according to the second embodiment of the present invention;
Fig. 6 is a block diagram of a gain control device according to the third embodiment of the present invention;
Fig~ 7 is a view showing the details of a delay line and a digital gain control circuit accordiny to the third embodiment; and Fig. 8 is a circuit diagram showing a modification of the digital gain control circuit according to the third embodiment of the present invention.
When a comparison is made between a conventional LP disc and a DAD, an LP disc has a maximum dynamic range of about 7G dB, as may be seen from the broken line in Figure 1 of the accompanying drawings, and this maximum dynamic range can only be obtained in an intermediate frequency range around 1 kHz. The dynamic range of the LP disc decreases to 40 dB in the high and low frequency ranges. In contrast to this, a DA~ has a wide dynamic range, as may be seen from the alternate long and short dashed line in Figure 1.
However, when signals are reproduced from a DAD
having such a wide dynamic range and are amplified in a conventional audio system for reproduction by a loudspeaker, extra power is applied to the loudspeaker, which may result in damage to the loudspeaker. Thus, when signals having peak levels higher than those of conventional cases are supplied to a power amplifier, and when the volume control is set to the same level position as in the conven~ional cases, the input signal wave~orms are clipped in a complex manner resulting in reproduction distortion. The clipped waves include strong high-frequency components and these :"
~ - 2 -may cause damage to a loudspeaker, particularly to a tweeter.
OBJECTS AND SIJMMARY OF THE INVENTION
.. . . .
According to the present invention there is provided a gain control device comprising:
detector means for detecting a dlgi-tal value exceeding a predetermined value in data of a digital signal obtained by conversion of an analog signal;
delay means for delaying the digital signal;
converter means for converting the digital signal from said dela~ means into an output analog signal; and gain control means for decreasing the gain of -the output analog signal in accordance with a detection signal from said deteclor means.
DETAIL~D DESCRIPTION OF THE ~REFERRED EMBODIMENTS
. .
I'he preferred embodiments of the present invention will now be described with reference tO the accompanying drawings.
Fig. 2 is a block diagram of a gain control device according to the first embodiment of the present invention.
In the first embodiment shown in Figure 2, digital signals obtained by A/D conversion of analog audio signals are modulated in accordance with the "Non Return to ~ero-l"
(NRZ-l) method and are recorded on a DAD 1. Such digital signals may be obtained by sampling analog audio signals at a predetermined frequency, quantizing the samples and converting them to 16 bit data woxds, and then encoding the data words in accordance with the "Cross Interleave -,~
~ 3 ~ 36~
Reed Solomon Code" (CIRC) and "~ight to ~ourteen ~dulation (EFM) methods.
Encoding in accordance with the ClRC method is performed to correct most of a high density error such as a scratch on a disc.
The EFM method is a modulation method in which sixteen bits are divided into more and less significant 8-bit groups, respectively, and each group of eiyht bits is converted inlo a 14-bit pattern. Modulation in accordance with the EFM method is performed so that digital signals may be recorded with the minimum amount of waveform distortion and so that DC components ~ay not be included in the recorded signals.
The digital signals recorded on the DAD 1 are read out hy an optical pickup or the like and are supplied to an EFM demodulator 2. Using the clock and _ 4 -sync signals extracted and separated respectively from the input signal, the EFM demodulator 2 per~orms ~FM
demodulation by reconverting each la-bit pattern into the original 8-bit group, and recombining the more and less significant 8-bit groups to obtain the original 16-bit data word. A digital signal SDl thus obtained is supplied to a memory/operation circuit 3 having a RAM (Random Access Memory) and the like.
The memory/operation circuit 3 performs the following operations:
(A) To write and store the digital signal SDl in the RAM,or ~t~,read it D~t f~om the RAM,~and to control the RAM.
(B) To detect and correct errors in 16-bit words in accordance wi-th the CIRC method.
(C) To interpolate, a "Bad" data word which has not been corrected in accordance with the CIRC
method, with another correct "Good" data word.
(The timings of read/write operations of the digital signal SDl in or from the RAM are controlled in accordance with clock pulses from a clock generator 5.) A digital signal SD2 is then obtained ~rom the memory/operation circuit 3. The-digital signal SD2 is a 16-bit data word which has been corrected for errors and which has been interpolated. The digital signal SD2 thus obtained is supplied ~o a delay line 4.
The delay line 4 delays the input digital signal SD2 to a time point after detection of the peak value at a peak detector 6. During the time delayed in this manner, an amplifier 8 as an analog gain controlling means can con-trol the gain in accordance with the peak detection result by the peak detector 6.
In response to the clock pulses from the clock generator 5, the delay line 4 sequentially shifts the 16-bit data word or the digital signal SD2 in a series circuit of latch registers. Alternatively, delayed readout may be performed from the RA~ by a modulo-M address counter which operates in accordance with the clock pulses from the clock generator 5.
Time delay o~ the input signal which may not cause any distortion in the output may be performed if the frequency of the clock pulses supplied to the delay line ~ from the clock generator 5 is an integer multiple of the sampling frequency.
A digital signal SD3 from the delay line 4 is supplied to a D/A converter 7 to be reconverted into the analog audio signal. An analog audio signal SA
thus obtained is produced from an output terminal 9 through the amplifier 8. A speaker is connected to the output terminal 9 through a preamplifier and a power amplifier of the user~
Meanwhile, the digital signal SD2 from the memory/operation circuit 3 is also supplied to the peak detector 6.
The peak detector 6 detects the peak value of the digital signal SD2 to see if the peak value exceeds a predetermined level to cause undesirable cLipping.
On the basis of the data of the digital signal SD~, the peak detector 6 detects the slope of the audio signal or the like to -thereby delect -the peak value of the component exceeding the predetermined level.
A detection signal Sp from the peak detector 6 is supp]ied to the amplifier 8 to decreace the gain of the amplifier 8. Thus, the peak component of an analog audio signal SA from the D/A converter 7 is suppressed.
If the da-ta sampling frequency is set at 44.1 kHz and the delay time of the delay line 4 is set to be 1/44.1 kHz x 4 . 90 ~sec, the gain of the amplifier 8 is controlled so that the peak component is suppressed before the audio signal components in the high frequency range o about 10 kHz abruptly increase in level. Since the pulse width of a pulse having a high frequency of 10 kHz is 100 ~sec, the peak value is detected before this pulse reaches the amplifier 8.
The peak component of the pulse is suppressed by the detection signal Sp from the peak detector 6. The detection signal Sp may, for example, be supplied to an electronic volume control or the like having a good response time characteristic to perform gain control of the audio signal. The electronic volume control may control the feedback amount of the amplifier 8 or the like. A mechanical volume control may also be used where it is possible.
The above will now be described with reference to the waveforms shown in Figs. 3(a; and 3(~), wherein Fig. 3(a) shows the waveform of the signal in which the peak component is not suppressed, and Fig. 3(b) shows -the waveform of the signal in which -the peak component is suppressed from a timing of a weak signal before ~he peak componen~ is received. In this manner, an abrupt level change is prevented to providè smooth peak component suppression, thereby allowing production of sounds of good quality.
The gain of the amplifier 8 which has been controlled in his manner by an electronic or mechanical volume control can either gradually be restored to the original value or be left unchanged.
However, the latter is preferable considering distortion along the time base.
Fig. 4 shows a block diagram o a gain control device according to the second embodiment of the present invention. The same reference numerals in Fig. 2 denote the same parts as in Fig. 1, and a detailed description will be omitted.
According to the second embodiment, a digital signal S D2 prior to interpolation at an interpola-tor 10 of a memory operation circuit 3' is supplied to a peak detector 6' for peak detection. The interpolator 10 serves to interpolate the data word which has not been corrected in accordance with the CIRC method. The digital signal S D2 is a digital signal which includes a flag "Good" for the data word which has been corrected and a flag l'Badl' for the data word which has not been corrected. The diyital signal S D2 with such a flag is supplied to the interpola-tor 10. The interpolator 10 discriminates between the "Good" and "Bad" flags, and interpolates the data with the flag "Bad" with the data with the flag "Good".
_ ~ _ 3; ~
Meanwhil~, the peak detector 6' de-tects the peak value of the audio signal on the basis o~ the data word including a flag "Good" of the digital signal S D2.
More specifically, the peak detector 6' selects the data with the flag "Good" and produces a detection signal Sp similar to that obtained in the first embodiment described above. In this embodiment, the peak value of the digital signal is detected before the digital signal is interpolated. Therefore, while the interpolator 10 performs lnterpolation, a desired time delay from the time point o peak detection is obtained. Therefore, the interpolator 10 also serves as a delay line and the second embodiment does not require a delay line as in the first embodiment.
An output signal S'D3 from the interpolator 10 is supplied to a D/A converter 7 and an audio analog signal SA therefrom is supplied to an amplifier 8.
In a digital signal, a certain bit corresponds to the peak value of the analog audio signal, and a level exceeding a certain level does not exist in the digital signal. Therefore, if the volume level which has been decreased in accordance with the gain control in the first and second embodiment is left unchanged, one setting operation of the volume level against the peak value prevents clipping afterwards.
In this sense, the gain control device of the present invention also serves as an automatic vo]ume level setter.
Fig. 6 is a block diagram of a gain control circuit of the third embodiment of the present L L~ ,~3 ~
invention~ The same reference numerals in Fig. 2 denote the same parts and a detailed descrip~ion thereof will be omitted.
According to the third embodiment, gain control is performed in a digital manner. A digital signal SD3 which has been delayed by a delay line 4 is supplied to a gain control circuit 11. The digital gain control circuit 11 performs gain control in accordance with a detection signal Sp from a peak detector 6. A digital signal which has been gain-controlled by the digital gain control circuit 11 is supplied to a D/A con~erter 7.
Fig. 7 shows an example of a circuit configuration of the delay line 4 and the digital gain control circuit 11. The delay line 4 consists of n stages of shift registers Rl to Rn. Shift clocks of the data sampling frequency, for example, 44.1 kHz are supplied to the respective shift registers Rl to Rn so as to receive and produce the 16-bit data word or the digital signal SD2 in a parallel manner. The delay time of the delay line 4 is determined by the number n of shift registers, which is set, for example, to be 100. A digital signal SD3 from the delay line 4 is supplied to the digital gain control circuit 11 comprising a logic circuit A.
The logic circuit A can be switched between one mode in which the signal SD3 from the delay line 4 is supplied to the amplifier 8 without modification and the other mode in which the signal SD3 is shifted by one bit toward the LSB to add the MSB of "O" and is then supplied to the amplifier 8. A detection signal Sp from -the peak detector 6 is supplied to the logic circuit A through a terminal 12. When the peak value of the audio signal is discriminated to exceed a predetermined level in accordance with the detection signal Sp, the logic circuit A shifts the signal SD3 from the delay circuit 4 by one bit toward the LSB to add the MSB of "0". The output signal from the logic circuit A is supplied to an amplifier 8' through a D/A
converter 7. In this case, the level of the signal SD3 is reduced to half. Generally stated, shift by m bits results in a reduction in level by l/2m.
~ lternatively, the logic-circuit A may be omitted. In this case, the inal shift register Rn in the delay line 4 is controlled such that the storage contents therein are shifted to the LSB by m bits to allow level reduction by l/2m.
Fig. 8 shows anot~er example of the digital gain control circuit 11 which comprises a ROM 13. The ROM 13 stores a plurality of types of data conversion tables for attenuating the level of the digital signal SD3 (16-bit data word). The signal SD3 from the delay line 4 is supplied as an address signal to the ROM 13, while an address for selecting the data converslon table is supplied to the ROM 13 from a logic circuit B designated by reference numeral 14.
The logic circuit B receives a detection signal Sp from a peak detector 6 as well as a detection signal representing the maximum power and a detection signal representing a volume level position from a power ampllfier -throu~h terminals 15 and 16, respectively. Since the clipping level of the reproduced waves changes in accordance with the maximum power and the volume level position of the power amplifier used, the degree of level attenuation or gain control is adjusted in accordance with this clipping level. The detection signal representing the maximum power is supplied from a generator which generates a signal of a level corresponding to the maximum power of the power amplifier. The detection signal representing the volume level position is supplied from a potentiometer which is synchronous with the volume level. In accordance with the data on the maximum power and the volume level position of the power amplifier thus obtained, the logic circuit B determines a data conversion table to be used. When the peak value of the audio signal is detected by the peak detectcr 6, the signal SD3 is attenuated in level in accordance with a predetermined ratio and is then supplied to the D/A converter 7 through a multiplexer 17.
However, when the signal SD2 does not exceed the predetermined level, it is supplied without modification from the ~OM 13 to the D/A converter 7 through the multiplexer 17. When the pea~ value of the audio signal is not detected, the signal need not be supplied to the ROM 13. Therefore, the multiplexer 17 is incorporated to allow selection between the signal SD2 from the delay line ~ and the signal SD2 which is attenuated in level and which is read ou-t from the ROM 13. The multiplexer l7 is controlled by a signal from the peak detector 6 which is supplied through the logic circuit s.
Although the present inventlon has been descxibed with reference to a reproduction system of a DAD, the present invention is similarly applicable to various types of digital signal transmission systems~
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A gain control device comprising:
detector means for detecting a digital value exceeding a predetermined value in data of a digital signal obtained by conversion of an analog signal;
delay means for delaying the digital signal;
converter means for converting the digital signal from said delay means into an output analog signal; and gain control means for decreasing ihe gain of the output analog signal in accordance with a detection signal from said detector means.
detector means for detecting a digital value exceeding a predetermined value in data of a digital signal obtained by conversion of an analog signal;
delay means for delaying the digital signal;
converter means for converting the digital signal from said delay means into an output analog signal; and gain control means for decreasing ihe gain of the output analog signal in accordance with a detection signal from said detector means.
2. A device according to claim 1 wherein said gain control means comprises digital gain control means for controlling the digital signal from said delay means.
3. A device according to claim 1 wherein said gain control means comprises analog gain control means for controlling the output analog signal.
4. A device according to claim 1 further compris-ing error detector/corrector means for detecting and cor-recting an error of the digital signal.
5. A device according to claim 4 wherein said delay means also serves as an interpolator means for inter-polating a digital signal which is not corrected by said error detector/corrector means with a correct digital signal.
6. A device according to claim 5 wherein the digital signal from said error detector/corrector signal includes a flay "Good" if the digital signal is corrected and a flag "Bad" if the digital signal is not corrected;
and the detection signal from said detector means is obtain-ed on the basis of the digital signal including the flag "Good".
and the detection signal from said detector means is obtain-ed on the basis of the digital signal including the flag "Good".
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57024830A JPS58142614A (en) | 1982-02-18 | 1982-02-18 | Gain controlling device |
| JP24830/82 | 1982-02-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1214998A true CA1214998A (en) | 1986-12-09 |
Family
ID=12149105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000421039A Expired CA1214998A (en) | 1982-02-18 | 1983-02-07 | Digitally processed gain control device |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS58142614A (en) |
| KR (1) | KR910002980B1 (en) |
| CA (1) | CA1214998A (en) |
| DE (1) | DE3305662C2 (en) |
| FR (1) | FR2521758A1 (en) |
| GB (1) | GB2119189B (en) |
| NL (1) | NL8300618A (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4700362A (en) * | 1983-10-07 | 1987-10-13 | Dolby Laboratories Licensing Corporation | A-D encoder and D-A decoder system |
| JPH0772971B2 (en) * | 1988-10-05 | 1995-08-02 | パイオニア株式会社 | Disc player playback level setting method |
| EP0911712A1 (en) | 1997-10-21 | 1999-04-28 | Deutsche Thomson-Brandt Gmbh | Corrected servo control signal in a servo control loop |
| EP0911713B1 (en) * | 1997-10-21 | 2004-09-22 | Deutsche Thomson-Brandt Gmbh | Corrected servo control signal in a servo control loop |
| GB2378064A (en) * | 2001-03-12 | 2003-01-29 | Simoco Int Ltd | A feed-forward signal level control arrangement with a delay in the signal path |
| WO2011143040A1 (en) * | 2010-05-10 | 2011-11-17 | Marvell World Trade Ltd. | Method and apparatus for offset and gain correction |
| WO2013036401A1 (en) | 2011-09-08 | 2013-03-14 | Marvell World Trade, Ltd. | Method and apparatus for offset and gain correction |
| US9831843B1 (en) | 2013-09-05 | 2017-11-28 | Cirrus Logic, Inc. | Opportunistic playback state changes for audio devices |
| US9525940B1 (en) | 2014-03-05 | 2016-12-20 | Cirrus Logic, Inc. | Multi-path analog front end and analog-to-digital converter for a signal processing system |
| US9774342B1 (en) | 2014-03-05 | 2017-09-26 | Cirrus Logic, Inc. | Multi-path analog front end and analog-to-digital converter for a signal processing system |
| US9306588B2 (en) | 2014-04-14 | 2016-04-05 | Cirrus Logic, Inc. | Switchable secondary playback path |
| US10785568B2 (en) | 2014-06-26 | 2020-09-22 | Cirrus Logic, Inc. | Reducing audio artifacts in a system for enhancing dynamic range of audio signal path |
| US9596537B2 (en) | 2014-09-11 | 2017-03-14 | Cirrus Logic, Inc. | Systems and methods for reduction of audio artifacts in an audio system with dynamic range enhancement |
| US9503027B2 (en) | 2014-10-27 | 2016-11-22 | Cirrus Logic, Inc. | Systems and methods for dynamic range enhancement using an open-loop modulator in parallel with a closed-loop modulator |
| US9584911B2 (en) | 2015-03-27 | 2017-02-28 | Cirrus Logic, Inc. | Multichip dynamic range enhancement (DRE) audio processing methods and apparatuses |
| US9959856B2 (en) | 2015-06-15 | 2018-05-01 | Cirrus Logic, Inc. | Systems and methods for reducing artifacts and improving performance of a multi-path analog-to-digital converter |
| US9955254B2 (en) * | 2015-11-25 | 2018-04-24 | Cirrus Logic, Inc. | Systems and methods for preventing distortion due to supply-based modulation index changes in an audio playback system |
| US9543975B1 (en) | 2015-12-29 | 2017-01-10 | Cirrus Logic, Inc. | Multi-path analog front end and analog-to-digital converter for a signal processing system with low-pass filter between paths |
| US9880802B2 (en) | 2016-01-21 | 2018-01-30 | Cirrus Logic, Inc. | Systems and methods for reducing audio artifacts from switching between paths of a multi-path signal processing system |
| US9998826B2 (en) | 2016-06-28 | 2018-06-12 | Cirrus Logic, Inc. | Optimization of performance and power in audio system |
| US9813814B1 (en) | 2016-08-23 | 2017-11-07 | Cirrus Logic, Inc. | Enhancing dynamic range based on spectral content of signal |
| US9780800B1 (en) | 2016-09-19 | 2017-10-03 | Cirrus Logic, Inc. | Matching paths in a multiple path analog-to-digital converter |
| US9762255B1 (en) | 2016-09-19 | 2017-09-12 | Cirrus Logic, Inc. | Reconfiguring paths in a multiple path analog-to-digital converter |
| US9929703B1 (en) | 2016-09-27 | 2018-03-27 | Cirrus Logic, Inc. | Amplifier with configurable final output stage |
| US9967665B2 (en) | 2016-10-05 | 2018-05-08 | Cirrus Logic, Inc. | Adaptation of dynamic range enhancement based on noise floor of signal |
| US10321230B2 (en) | 2017-04-07 | 2019-06-11 | Cirrus Logic, Inc. | Switching in an audio system with multiple playback paths |
| US10008992B1 (en) | 2017-04-14 | 2018-06-26 | Cirrus Logic, Inc. | Switching in amplifier with configurable final output stage |
| US9917557B1 (en) | 2017-04-17 | 2018-03-13 | Cirrus Logic, Inc. | Calibration for amplifier with configurable final output stage |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3887875A (en) * | 1973-09-07 | 1975-06-03 | Ncr Co | Digital signal leveling device |
| AT347504B (en) * | 1975-04-18 | 1978-12-27 | Siemens Ag Oesterreich | DEVICE FOR AUTOMATIC VOLUME CONTROL |
| JPS5948447B2 (en) * | 1977-07-20 | 1984-11-27 | ソニー株式会社 | Gain compensation circuit for signal regenerator |
| GB1599401A (en) * | 1978-04-18 | 1981-09-30 | Nat Res Dev | Input signal level control for communications channels |
| US4233566A (en) * | 1978-10-23 | 1980-11-11 | Technical Audio Products Corporation | Distortion free power limiting and clipping prevention circuit |
| JPS56111311A (en) * | 1980-02-07 | 1981-09-03 | Nec Corp | Intermediate-frequency amplifying device with function of limiting input amplitude |
-
1982
- 1982-02-18 JP JP57024830A patent/JPS58142614A/en active Pending
-
1983
- 1983-02-07 CA CA000421039A patent/CA1214998A/en not_active Expired
- 1983-02-17 KR KR1019830000647A patent/KR910002980B1/en not_active IP Right Cessation
- 1983-02-17 GB GB08304397A patent/GB2119189B/en not_active Expired
- 1983-02-18 DE DE3305662A patent/DE3305662C2/en not_active Expired - Lifetime
- 1983-02-18 NL NL8300618A patent/NL8300618A/en active Search and Examination
- 1983-02-18 FR FR8302668A patent/FR2521758A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2521758B1 (en) | 1985-02-08 |
| FR2521758A1 (en) | 1983-08-19 |
| KR910002980B1 (en) | 1991-05-11 |
| GB2119189A (en) | 1983-11-09 |
| GB2119189B (en) | 1985-08-14 |
| DE3305662C2 (en) | 1995-05-24 |
| GB8304397D0 (en) | 1983-03-23 |
| NL8300618A (en) | 1983-09-16 |
| DE3305662A1 (en) | 1983-09-08 |
| KR840003937A (en) | 1984-10-04 |
| JPS58142614A (en) | 1983-08-24 |
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