JPH0353041U - - Google Patents

Info

Publication number
JPH0353041U
JPH0353041U JP11322789U JP11322789U JPH0353041U JP H0353041 U JPH0353041 U JP H0353041U JP 11322789 U JP11322789 U JP 11322789U JP 11322789 U JP11322789 U JP 11322789U JP H0353041 U JPH0353041 U JP H0353041U
Authority
JP
Japan
Prior art keywords
generation means
generates
count value
width modulated
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11322789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11322789U priority Critical patent/JPH0353041U/ja
Publication of JPH0353041U publication Critical patent/JPH0353041U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の構成を示す構成図
、第2図は第1図に示した装置の動作状態におけ
る各部の信号波形を示すタイムチヤート、第3図
はD/A変換器の他の構成例の構成を示す構成図
である。 1……カウンタ値生成手段、2……付加パルス
生成手段、3……比較手段、4……PWM出力手
段、5……8ビツトカウンタ、6……2ビツトカ
ウンタ、7……8ビツト比較器、8……2ビツト
比較器、9……論理ゲート、10……論理ゲート
、11……Dフリツプフロツプ、12……ローパ
スフイルタ、13……10ビツトカウンタ、14
……10ビツト比較器。
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a time chart showing signal waveforms of various parts in the operating state of the device shown in Fig. 1, and Fig. 3 is a D/A converter. It is a block diagram which shows the structure of another example of a structure. 1...Counter value generation means, 2...Additional pulse generation means, 3...Comparison means, 4...PWM output means, 5...8 bit counter, 6...2 bit counter, 7...8 bit comparator , 8... 2-bit comparator, 9... logic gate, 10... logic gate, 11... D flip-flop, 12... low pass filter, 13... 10 bit counter, 14
...10-bit comparator.

Claims (1)

【実用新案登録請求の範囲】 デイジタル信号に応じてパルス幅変調された信
号を生成し、このパルス幅変調された信号をロー
パスフイルタを通過さることによりアナログ信号
に変換するD/A変換器において、 分割された複数のPWM周期に応じたカウント
値を生成するカウント値生成手段1と、 入力デイジタルデータとカウント値生成手段1
で生成されたカウント値とを比較する比較手段2
と、 付加パルスを生成する付加パルス生成手段3と
、 比較手段2の比較出力と付加パルス生成手段3
で生成されたパルスとを合成してパルス幅変調出
力を生成するPWM出力手段4と、 分割されたPWM周期に応じたカツトオフ周波
数に設定され、PWM出力手段4のパルス幅変調
出力をフイルタリングするローパスフイルタ12
とを有することを特徴とするD/A変換器。
[Claims for Utility Model Registration] In a D/A converter that generates a pulse width modulated signal in response to a digital signal and converts this pulse width modulated signal into an analog signal by passing it through a low-pass filter, Count value generation means 1 that generates count values according to a plurality of divided PWM cycles; and input digital data and count value generation means 1.
Comparison means 2 for comparing the count value generated by
, Additional pulse generation means 3 that generates additional pulses, Comparison output of comparison means 2 and additional pulse generation means 3
a PWM output means 4 which synthesizes the pulses generated by the PWM output means 4 to generate a pulse width modulated output; Low pass filter 12
A D/A converter comprising:
JP11322789U 1989-09-27 1989-09-27 Pending JPH0353041U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11322789U JPH0353041U (en) 1989-09-27 1989-09-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11322789U JPH0353041U (en) 1989-09-27 1989-09-27

Publications (1)

Publication Number Publication Date
JPH0353041U true JPH0353041U (en) 1991-05-22

Family

ID=31661646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11322789U Pending JPH0353041U (en) 1989-09-27 1989-09-27

Country Status (1)

Country Link
JP (1) JPH0353041U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56136028A (en) * 1980-03-27 1981-10-23 Toshiba Corp D-a converter
JPS63310221A (en) * 1987-06-12 1988-12-19 Hitachi Ltd D/a converting circuit
JPS6436118A (en) * 1987-07-31 1989-02-07 Mazda Motor Digital pulse width modulator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56136028A (en) * 1980-03-27 1981-10-23 Toshiba Corp D-a converter
JPS63310221A (en) * 1987-06-12 1988-12-19 Hitachi Ltd D/a converting circuit
JPS6436118A (en) * 1987-07-31 1989-02-07 Mazda Motor Digital pulse width modulator

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