JPH0352329A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To facilitate the phase adjustment and to improve the phase error signal detection accuracy by using a DC level converter to vary the DC level, thereby adjusting the phase of the pulse. CONSTITUTION:The phase of a prescribed signal outputted from a reference oscillator 1 is compared with the phase of a variable frequency signal outputted from a variable frequency oscillator 4 and the variable frequency oscillator 4 is controlled so as to phase-lock the variable frequency signal outputted from the variable frequency oscillator 4 with a prescribed signal outputted from the reference oscillator 1 based on the phase comparison output from the phase comparator 2. Then a DC level is varied with a DC level converter 8 to adjust the phase of the pulse. Thus, the phase adjustment of the position error signal detection pulse is attained without losing the stability of the circuit, and the position error signal detection accuracy is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked loop circuit for controlling a gate pulse signal used in a recording disk device.

[Prior Art] FIG. 3 is a block diagram showing the configuration of a conventional phase-locked loop circuit described in, for example, Japanese Patent Publication No. 63-49936. In the figure, (1) is a recording disk. The reference oscillator (2) is connected to the output side of the reference oscillator (1) and is frequency-divided by the output of the reference oscillator (1). This is a phase comparator that compares the output of the device (5).

In addition, (3) is a loop filter that is connected to the output side of the phase comparator (2) and makes a low pass, and (4) is a voltage control consisting of a motor for rotating the recording disk that is connected to the output side of the loop filter (3). oscillator, (5) is a voltage controlled oscillator (
This is a frequency divider that is connected to the output side of the voltage controlled oscillator (4) and divides the output pulse of the voltage controlled oscillator (4).

Further, the phase comparator (2), as shown in FIG. 4, is composed of a mono-staple multi-byte break (6) and a D-type flip-flop (7).

Next, the operation will be explained.

The servo information recorded on the recording disk is read by the head, and the head outputs it as a servo signal.
The servo signal is pulsed by a pulsing circuit (not shown) and output from the reference oscillator (1).

Then, the servo information signal (100) outputted from the reference oscillator (1) is inputted to the phase comparator (2), and the monostable multivibrator (6) and D type flip-flop (7) of the phase comparator (2) are input to the phase comparator (2). is input.

The monostable multivibrator (6) is driven by the rising edge of the input servo information signal (100) and outputs a high level signal (1 0 1) for the time set by the time constant setting section (Fig. 5). reference).

Note that the time set by the time constant setting section is shorter than the interval of the servo information signal (1 0 0) and is shorter than the interval of the voltage controlled oscillator (4
) generally takes 60% or more of the interval of the servo information signal (1 0 0).

Further, the D type flip-flop (7) is driven by the rising edge of the input servo information signal (1 0 0) and outputs a high level signal (1 0 2 b), and the signal (102b) is The D-type flip-flop reset signal (103b) whose frequency is divided by the frequency divider (5) from the output signal from the voltage controlled oscillator (4) changes to Low level at the rising edge (see FIG. 5).

Then, these signals (101), (102b) are compared in phase, but in this case, the phase comparison means that these signals (1 0 1) . (1 02
b) The output of the voltage controlled oscillator (4) is divided by the frequency divider (5) so that the area of the High level part is the same.
Type flip-flop reset signal (1 0 3 b
) controls the phase of

However, the D type flip-flop reset signal (1
03b) is the input servo information signal (1
0 0) and is output at 60% or more of the time.

At this time, a gate pulse (
104b) is the D type flip-flop reset signal (
103b) Generated in reverse synchronization with the rising edge,
This position error signal detection gate pulse (104b) operates most stably at high and low pulses.
The servo information signal (1 0 0
), but due to constraints due to the time constant of the monostable multiviprator (6), the phase may be shifted.

[Issue 21 to be solved by the invention Since the conventional phase-lock droop circuit is configured as described above, the servo information signal of the gate pulse for position error signal detection is changed by changing the time constant for the stability of the circuit. However, there was a problem in that it was difficult to adjust the phase for the position error signal, and the accuracy of detecting the position error signal deteriorated.

This invention was developed to solve the above-mentioned problems, and it is a phase-locked device with high position error signal detection accuracy that can adjust the phase of the position error signal detection pulse without impairing the stability of the circuit. The purpose is to obtain a lube circuit.

[Means for Solving the Problems] A phased loop circuit according to the present invention includes a reference oscillator that outputs a predetermined signal, a variable frequency oscillator that outputs a variable frequency signal, and a predetermined signal output from the reference oscillator. This device includes a phase comparator that compares the phase of a variable frequency signal output from a variable frequency oscillator, and a DC level converter provided in the phase comparator that can arbitrarily set the DC level.

[Effect]

The phase-locked droop circuit in this invention compares the phases of a predetermined signal output from a reference oscillator and a variable frequency signal output from a variable frequency oscillator, and based on the phase comparison output from the phase comparator, outputs a variable frequency oscillator. The variable frequency oscillator is controlled so that the phase of the variable frequency signal output from the reference oscillator is synchronized with the predetermined signal output from the reference oscillator, and the phase of the pulse is adjusted by changing the DC level using the DC level converter.

[Example code] Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a phase comparator (2) according to the present invention. In the figure, (6) is a monostable multi-bye break, and (7) is a D type arranged in parallel with the monostable multi-bye break. The flip-flop (8) is a DC level converter which is connected to the output side of the D-type flip-flop (7) and can arbitrarily set the DC level.

Next, the operation of this embodiment will be explained.

The servo information recorded on the recording disk is read by the head, and the head outputs it as a servo signal.
The servo signal is pulsed by a pulsing circuit (not shown) and output from the reference oscillator (1).

Then, the servo information signal (1 0 0) output from the reference oscillator (1) is input to the phase comparator (2), and the monostable multivibrator (6
) and a D-type flip-flop (7).

The monostable multi-by-break (6) is driven by the rising edge of the input servo information signal (1 0 0) and outputs a high level signal (1 0 1) for the time set in the time constant setting section (1 0 1). (See Figure 2).

Note that the time set by the time constant setting section is shorter than the interval of the servo information signal (100), and in order to stably output the output frequency of the voltage controlled oscillator (4), the servo information signal (100) is shorter than the interval of the servo information signal (100).
0 0) time is taken more than 60% of the interval.

Further, the D type flip-prop (7) is driven by the rising edge of the input servo information signal (1 0 0) and outputs a high level signal (1 0 2 a).

Then, the signal (1 0 2 a) is input to the DC level converter (8), and the High level portion of the pulse is converted into a signal (1
0 5) is output.

This signal (105) is then transmitted to the voltage controlled oscillator (4
) is changed to Low level by the rising edge of the D-type flip-flop reset signal (103a), which is obtained by dividing the output signal from the D-type flip-flop reset signal (103a) by the frequency divider (5) (see FIG. 2).

And these signals (1 0 1), (1 0
5) are compared in phase; in this case, the phase comparison is in other words, these signals (101), (105
D type flip-flop reset signal (1 0 3 a) in which the output of the voltage controlled oscillator (4) is divided by the frequency divider (5) so that the areas of the high level parts of ) are the same.
control the phase of

Output signal of monostable multivibrator (6) (
The High portion of 101) has a constant DC level and time width, and always shows a constant area.

On the other hand, the output signal (10
In 5), the DC level can be set arbitrarily, and the time width is inversely proportional to the set level (°).

Therefore, the D type flip-flop reset signal (1
The position error signal detection gate pulse (1 0 4 a) inverted and synchronized with 0 3 a) can operate most stably, and the servo information signal (1 0 0) is located by shortening the time axis by arbitrarily increasing the DC level of the High portion of the output signal (105) of the DC level converter (8),
This is achieved by adjusting the D-type flip-flop preset signal (103a) to be located at the center between the pulses of 0).

In addition, although the above-mentioned example was explained using a digital type DC level converter (8), it is not limited to this.
An analog circuit type using an integrating circuit, a differentiating circuit, etc. may also be used.

[Effects of the Invention] As explained above, according to the present invention, the phase of the pulse can be adjusted by changing the DC level using the DC level converter, so that the phase adjustment is facilitated and the position error is reduced. This has the effect of increasing signal detection accuracy and obtaining high reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a phase comparator according to an embodiment of the invention, FIG. 2 is a timing chart of the invention, FIG. 3 is a block diagram showing the configuration of a phase-locked loop circuit, and FIG. is a block diagram showing the configuration of a conventional phase comparator, and FIG. 5 is a conventional timing chart. In the figure, (1) is the reference oscillator, (2) is the phase comparator, and (4) is the reference oscillator.
) is a variable frequency oscillator, (6) is a monostable multivibrator, (7) is a D-type flip-flop, (
8) is a DC level converter. Note that the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A reference oscillator that outputs a predetermined signal, a variable frequency oscillator that outputs a variable frequency signal, and a phase comparator that compares the phases of the predetermined signal output from the reference oscillator and the variable frequency signal output from the variable frequency oscillator. a phase-locked loop circuit that controls the variable frequency oscillator so that the variable frequency signal output from the variable frequency oscillator is phase-synchronized with a predetermined signal output from the reference oscillator based on the phase comparison output from the phase comparator. The phase comparator is provided with a DC level converter capable of arbitrarily setting the DC level, and the phase of the pulse can be adjusted by changing the DC level with the DC level converter. Locked loop circuit.