JPH0351115B2 - - Google Patents

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Publication number
JPH0351115B2
JPH0351115B2 JP57213302A JP21330282A JPH0351115B2 JP H0351115 B2 JPH0351115 B2 JP H0351115B2 JP 57213302 A JP57213302 A JP 57213302A JP 21330282 A JP21330282 A JP 21330282A JP H0351115 B2 JPH0351115 B2 JP H0351115B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
layer
semiconductor
carrier concentration
forbidden band
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57213302A
Other languages
Japanese (ja)
Other versions
JPS59104178A (en
Inventor
Kazuo Sakai
Juichi Matsushima
Shigeyuki Akiba
Katsuyuki Uko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP57213302A priority Critical patent/JPS59104178A/en
Priority to GB08332597A priority patent/GB2132016B/en
Publication of JPS59104178A publication Critical patent/JPS59104178A/en
Priority to US06/806,746 priority patent/US4682196A/en
Publication of JPH0351115B2 publication Critical patent/JPH0351115B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明はn−i−p−i−n構造(p−i−n
−i−p構造に対しても、同様に適用可能である
が、簡単のためn−I−p−i−n構造で説明す
る)の受光素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides an n-i-p-i-n structure (p-i-n
Although the present invention is similarly applicable to the -i-p structure, the present invention relates to a light-receiving element of the n-i-p-i-n structure for simplicity.

n−i−p−i−n素子は、n−i−n構造の
i層中に100Å前後の薄いp層を形成したもので、
多数キヤリヤが主に伝導に関与する素子であるた
めに高速素子として期待されており、又最近では
この構造を利用した3端子素子も提案されてい
る。
The n-i-p-i-n element has a thin p-layer of around 100 Å formed in the i-layer of the n-i-n structure.
Since the majority carrier is an element mainly involved in conduction, it is expected to be a high-speed element, and recently, three-terminal elements using this structure have also been proposed.

更に、この素子は過剰雑音のない高感度光検出
素子として使用することも可能であり、その応用
範囲は広い。
Furthermore, this element can also be used as a highly sensitive photodetector element without excessive noise, and its range of applications is wide.

はじめに、n−i−p−i−n素子の動作を説
明する。第1図はGaAsを用いた従来のn−i−
p−i−n素子の熱平衡状態及び電圧Vを印加し
た時のバンド構造を示したものであり、φBOは2
つのn層の間のポテンシヤル障壁の高さを表す。
電圧V印加した時に流れる電流の密度Jは熱電子
放出の式によつてあらわされ、 J=A*T2exp(−qφBO/kT) {exp(qα2V/kT)−exp(−qα1V/kT)} (1) となる。ここは、A*は実効的なリチヤードソン
定数、Tは絶対温度、kはボルツマン定数、qは
電子素量であり、α1,α2を2つのi層の厚さとし
た時、α1=d1/(d1+d2)、α2=d2/(d1+d2
で与えられる。d1≠d2とすれば、電圧−電流特性
に非対称性が現れる。このため、通常のpn接合
ダイオードのように、順方向、逆方向といつた呼
び方ができる。
First, the operation of the n-i-p-i-n element will be explained. Figure 1 shows a conventional n-i-
This shows the thermal equilibrium state of the pin element and the band structure when voltage V is applied, and φ BO is 2
represents the height of the potential barrier between two n layers.
The density J of the current that flows when voltage V is applied is expressed by the thermionic emission formula, J=A * T 2 exp (-qφ BO /kT) {exp (qα 2 V/kT) − exp (-qα 1 V/kT)} (1). Here, A * is the effective Richardson constant, T is the absolute temperature, k is the Boltzmann constant, q is the elementary quantity of electrons, and when α 1 and α 2 are the thicknesses of the two i layers, α 1 = d 1 / (d 1 + d 2 ), α 2 = d 2 / (d 1 + d 2 )
is given by If d 1 ≠ d 2 , asymmetry appears in the voltage-current characteristics. For this reason, like a normal pn junction diode, it can be called forward direction or reverse direction.

次に、このn−i−p−i−n素子を受光素子
に適用した場合の動作について説明する。
Next, the operation when this n-i-p-i-n element is applied to a light receiving element will be explained.

光照射が無い場合、この受光素子に正孔は注入
されないので、受光素子の応答速度は極めて速
く、超高速素子として期待されている。一方、光
照射を行つた場合、光励起された少数キヤリアで
ある正孔はp層の部分に集まる。これはポテンシ
ヤル障壁φBOの値を小さくするように働くため、
素子を流れる電子電流は増加する。即ち、光照射
により光電流が流れるわけであるが、この時の感
度については約700A/W、利得にして約1000倍
もの値も報告されている。一方、応答速度につい
ても50〜500psの値が報告されており、高利得高
速受光素子として大いに期待される。
When there is no light irradiation, no holes are injected into the light receiving element, so the response speed of the light receiving element is extremely fast, and it is expected to be an ultra-high-speed element. On the other hand, when light irradiation is performed, holes that are photoexcited minority carriers gather in the p-layer. This works to reduce the value of the potential barrier φ BO , so
The electron current flowing through the element increases. That is, a photocurrent flows due to light irradiation, and it has been reported that the sensitivity at this time is about 700 A/W, and the gain is about 1000 times as high. On the other hand, response speed values of 50 to 500 ps have been reported, and there are great expectations as a high-gain, high-speed light-receiving device.

しかしながら、従来の構造では、例えばGaAs
を用いたn−i−p−i−n受光素子の場合、約
0.6eV前後の障壁高さのものが大部分であり、こ
の為、暗電流が比較的大きい傾向にあつた。ポテ
ンシヤル障壁φBOはポアソン方程式を解くこと
により得られ、 φBO=d1・d2/d1+d2・NA・XA/εS・q (2) で与えられる。ここで、NAはp層でのアクセプ
タ濃度、XAはp層の厚さ、εSは誘電率である。
φBOを大とするには、d1,d2(d1<d2)の差を大
きくしかつd1を大きくすること、NAを大きく
すること、XAを大きくするなどがあげられる。
しかし、d1を大きくすると正孔の寿命時間が長く
なり高速応答に悪影響があること、NAをあまり
大きくするのは結晶成長上問題であること、又p
層は障壁として働けばよいわけで、XAを大きく
すると高速応答性が失われること、などの問題が
あつた。
However, in conventional structures, e.g. GaAs
In the case of an n-i-p-i-n photodetector using
Most of them had a barrier height of around 0.6 eV, and therefore the dark current tended to be relatively large. The potential barrier φBO is obtained by solving Poisson's equation, and is given by φ BO =d 1 ·d 2 /d 1 +d 2 ·N A ·X AS ·q (2). Here, N A is the acceptor concentration in the p layer, X A is the thickness of the p layer, and ε S is the dielectric constant.
To increase φ BO , you can increase the difference between d 1 and d 2 (d 1 < d 2 ), increase d 1 , increase N A , and increase X A. .
However, if d1 is increased, the lifetime of the hole becomes longer and high-speed response is adversely affected.Increasing NA too much is problematic for crystal growth.
The layer only has to act as a barrier, and there were problems such as a loss of high-speed response when XA was increased.

本発明ではこうした問題を引き起こさずに、多
数キヤリア対するポテシヤル障壁を大きくするこ
とにより、暗電流の低減を実現しさらに光応答の
立ち下がり劣化をも防止しようとするものであ
る。
The present invention aims to reduce dark current and prevent fall degradation of photoresponse by increasing the potential barrier to majority carriers without causing such problems.

以下に本発明を詳細に説明する。 The present invention will be explained in detail below.

第2図は本発明によるメサ型n−i−p−i−
n受光素子の原理的構成を示す断面図であり、1
はn+−GaAs基板、2はn−GaAs層(n1018cm
-3、厚さ約1μm)、3はi−GaAs層(p1014cm
-3、厚さ約2μm)、4はp−G−Ga0.7Al0.3As層
(p1018cm-3、厚さ100Å)、5はi−GaAS層
(p1014cm-3、厚さ約1000Å)、6はn−GaAs
層(n1018cm-3、厚さ約1μm)、7,8は電極
である。この受光素子の熱平衡状態におけるバン
ド構造を第3図に示す。n層6から見たポテンシ
ヤル障壁の高さは、GaAsのみでn−i−p−i
−n構造を形成した場合に比べてほぼGaAsと
Ga0.7Al0.3Asとの間の伝導帯エネルギー単位の差
分ΔEcだけ大きくなる。禁制帯幅の差ΔEgはこの
場合〜0.4eVであり、ΔEc0.85ΔEgとすると、
ΔEC0.34eVとなる。他の条件が同じならば、
電流密度は(1)式でφBOをφBO+ΔEcとした値になる
わけで、ΔEc0.34eVの時室温では約10-6倍とな
り、大幅な暗電流の低減が実現できる。
FIG. 2 shows a mesa-type n-i-p-i-
FIG.
is n + -GaAs substrate, 2 is n-GaAs layer (n10 18 cm
-3 , thickness approximately 1 μm), 3 is i-GaAs layer (p10 14 cm
-3 , about 2 μm thick), 4 is a p-G-Ga 0.7 Al 0.3 As layer (p10 18 cm -3 , 100 Å thick), 5 is an i-GaAS layer (p 10 14 cm -3 , about 1000 Å thick) ), 6 is n-GaAs
The layer (n10 18 cm -3 , thickness approximately 1 μm), 7 and 8 are electrodes. FIG. 3 shows the band structure of this light-receiving element in a thermal equilibrium state. The height of the potential barrier seen from the n-layer 6 is n-i-p-i for GaAs only.
- Compared to the case where an n-structure is formed, it is almost as strong as GaAs.
Ga 0.7 Al 0.3 The difference in conduction band energy units between Ga 0.7 Al 0.3 As increases by ΔEc. The difference in forbidden band width ΔEg is ~0.4eV in this case, and assuming ΔEc0.85ΔEg,
ΔEC is 0.34eV. If other conditions are the same,
The current density is the value obtained by setting φ BO to φ BO + ΔEc in equation (1), and when ΔEc is 0.34 eV, it becomes approximately 10 -6 times at room temperature, and a significant reduction in dark current can be achieved.

〔実施例〕〔Example〕

第2図では、p層以外は全て同一組成の半導体
という構成とした。この構造では電子による暗電
流は減少するが、正孔による暗電流にはほとんど
影響を与えない。しかし、受孔素子として用いる
時には電子暗電流と正孔暗電流の比が利得に関係
するため、正孔暗電流の減少も必要となる。本発
明による実施例では正孔による暗電流も低減する
構造を示す。第4図はこの実施例の半導体受光素
子の断面図を示したもので、この素子は波長0.9
〜1.7μm帯の受光素子として設計されたものであ
る。10はn+−InP基板、11はn−InP層(n
1018cm-3、厚さ約2μm)、12はn−AlAs0.4
Sb0.6層(n1018cm-3、厚さ約100Å)、13はi
−In0.53Ga0.47As層(n1015cm-3、厚さ約1000
Å)、14はp−Als0.4Sb0.6層(p1018cm-3、厚
さ約100Å)、15はi−In0.53Ga0.47As層(n
1018cm-3、厚さ約1000Å)、16はn−InP層(n
1018cm-3、厚さ約1μm)、17,18は電極で
ある。ここでAlAs0.4Sb0.6の禁制帯幅は約1.9eV
であり、In0.53Ga0.47As、InPのそれよりも大き
い。第5図に、この受光素子の熱平衡状態におけ
るバンド構造を示す。p−AlAs0.4Sb0.6層14に
より、第2図の受光素子と同様にポテンシヤル障
壁が高くなり、電子による暗電流は大幅に低減さ
れる。一方、n−AlAs0.4Sb0.6層12を形成する
ことにより、n−InP層11で少数発生した正孔
が拡散して、i−In0.53Ga0.47As層13に注入さ
れるのを防止し、よつて正孔による暗電流を低減
している。即ち、2つのAlAs0.4Sb0.6層をn−i
−p−i−nの構造の中に形成することにより、
電子:正孔両方による暗電流を減少できる。更
に、この構造に0.9〜1.7μmの光を照射すると、
光は2つのi層でのみ吸収され、両側のn層では
ほとんど吸収されない。仮に両側の層で光吸収が
起こり、電子・正孔対が発生すると、ここではほ
とんど電界が無いため、主に拡散によつてi層ま
で移動することになり、従つてこの拡散によるキ
ヤリア移動が、受光素子としての光応答の立ち下
がりを劣化させることとなる。本発明により、光
吸収がi層部分のみで起こる構成にすることによ
り、こうした電流に起因する光応答の立ち下がり
劣化は防止できる。また、ごく少数発生したとし
ても、特に少数キヤリア(この場合正孔)の拡散
については、層12によつてi層への注入が妨げ
られるので、光応答の立ち下がり劣化を十分に防
止できる。即ち第4図のように構造にすることに
より、低暗電流で高速応答利得の受光素子が実現
できる。
In FIG. 2, all semiconductors except the p-layer have the same composition. This structure reduces the dark current caused by electrons, but has little effect on the dark current caused by holes. However, when used as a hole receiving element, since the ratio of electron dark current to hole dark current is related to gain, it is also necessary to reduce the hole dark current. Examples according to the present invention show a structure in which dark current due to holes is also reduced. FIG. 4 shows a cross-sectional view of the semiconductor photodetector of this example, and this device has a wavelength of 0.9.
It is designed as a light-receiving element in the ~1.7 μm band. 10 is an n + -InP substrate, 11 is an n-InP layer (n
10 18 cm -3 , thickness approximately 2 μm), 12 is n-AlAs 0.4
Sb 0.6 layer (n10 18 cm -3 , thickness about 100 Å), 13 is i
-In 0.53 Ga 0.47 As layer (n10 15 cm -3 , thickness approx. 1000
14 is a p-Als 0.4 Sb 0.6 layer (p10 18 cm -3 , about 100 Å thick), 15 is an i-In 0.53 Ga 0.47 As layer (n
10 18 cm -3 , thickness approximately 1000 Å), 16 is an n-InP layer (n
10 18 cm −3 and a thickness of approximately 1 μm), and 17 and 18 are electrodes. Here, the forbidden band width of AlAs 0.4 Sb 0.6 is approximately 1.9 eV
is larger than that of In 0.53 Ga 0.47 As and InP. FIG. 5 shows the band structure of this light receiving element in a thermal equilibrium state. The p-AlAs 0.4 Sb 0.6 layer 14 increases the potential barrier similarly to the light receiving element shown in FIG. 2, and the dark current due to electrons is significantly reduced. On the other hand, by forming the n-AlAs 0.4 Sb 0.6 layer 12, holes generated in a small number in the n-InP layer 11 are prevented from being diffused and injected into the i-In 0.53 Ga 0.47 As layer 13, Therefore, dark current due to holes is reduced. That is, two AlAs 0.4 Sb 0.6 layers are
-by forming in the structure of p-i-n,
Dark current caused by both electrons and holes can be reduced. Furthermore, when this structure is irradiated with light of 0.9 to 1.7 μm,
Light is absorbed only by the two i-layers, and is hardly absorbed by the n-layers on either side. If light absorption occurs in the layers on both sides and electron-hole pairs are generated, there is almost no electric field here, so they will mainly migrate to the i-layer by diffusion, and therefore the carrier movement due to this diffusion will be This results in deterioration of the falling edge of the optical response of the light receiving element. According to the present invention, by configuring the structure in which light absorption occurs only in the i-layer portion, it is possible to prevent such falling degradation of the photoresponse caused by current. Furthermore, even if a very small number of carriers are generated, the diffusion of minority carriers (holes in this case) in particular is prevented from being injected into the i-layer by the layer 12, so it is possible to sufficiently prevent the degradation of the photoresponse from falling. That is, by constructing the structure as shown in FIG. 4, a light-receiving element with low dark current and high-speed response gain can be realized.

以上の実施例の説明では、材料としてGaAs/
GaAlAs系とInP/InGaAs/AlAsSb系の2つの
組合せを用いたが、勿論他の半導体の組合わせ、
例えば、GaPSb、AlGaAsSb、AlInAsP、
AlPSb等々の半導体を組合せてもかまわない。
又、メサ型に限ることなく、プレーナ型の素子に
も適用可能であるし、更に、p−i−n−i−p
受光素子に用いても勿論かまわない。
In the explanation of the above embodiments, GaAs/
Two combinations of GaAlAs and InP/InGaAs/AlAsSb were used, but of course other semiconductor combinations,
For example, GaPSb, AlGaAsSb, AlInAsP,
Semiconductors such as AlPSb may be combined.
Furthermore, it is not limited to mesa type elements, but can also be applied to planar type elements.
Of course, it may be used as a light receiving element.

こうした構造は、結晶成長については分子線エ
ピタキシヤル成長法にて、他のプロセスについて
は従来技術にて十分作製可能である。
Such a structure can be sufficiently produced by molecular beam epitaxial growth for crystal growth and by conventional techniques for other processes.

以上詳細に説明したように、本発明によれば暗
電流が少なく、光応答の立ち下がり劣化を防止で
きるn−i−p−i−n受光素子が作製可能であ
り、超高速かつ高感度の受光素子へ広く応用が可
能である。
As explained in detail above, according to the present invention, it is possible to fabricate a n-i-p-i-n photodetector that has low dark current and can prevent fall degradation of photoresponse, and has ultra-high speed and high sensitivity. It can be widely applied to light receiving elements.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のn−i−p−i−n素子の(a)熱
平衡時及び(b)電圧Vを印加した時のバンド構造
図、第2図は本発明の原理を説明するための半導
体素子の断面図、第3図は第2図の本発明の半導
体素子の熱平衡時におけるバンド構造図、第4図
は本発明による実施例の断面図、第5図は第4図
の実施例の熱平衡時におけるバンド構造図をそれ
ぞれ示す。 1……n+−GaAs基板、2……n−GaAs層、
3……i−GaAs層、4……p−Ga0.7Al0.3As層、
5……i−GaAs層、6……n−GaAs層、7,
8……電極、10……n+−InP基板、11……n
−InP層、12……n−AlAs0.4Sb0.6層、13…
…i−In0.53Ga0.47As層、14……p−AlAs0.4
Sb0.6層、15……i−In0.53Ga0.47As層、16…
…n−InP層、17,18……電極。
Fig. 1 is a band structure diagram of a conventional n-i-p-i-n element (a) at thermal equilibrium and (b) when a voltage V is applied. Fig. 2 is a band structure diagram for explaining the principle of the present invention. 3 is a band structure diagram of the semiconductor device of the present invention shown in FIG. 2 at thermal equilibrium; FIG. 4 is a sectional view of an embodiment of the present invention; FIG. 5 is a diagram of the embodiment of the invention shown in FIG. 4. The band structure diagrams at thermal equilibrium are shown for each. 1...n + -GaAs substrate, 2...n-GaAs layer,
3...i-GaAs layer, 4...p-Ga 0.7 Al 0.3 As layer,
5...i-GaAs layer, 6...n-GaAs layer, 7,
8...electrode, 10...n + -InP substrate, 11...n
-InP layer, 12... n-AlAs 0.4 Sb 0.6 layer, 13...
...i-In 0.53 Ga 0.47 As layer, 14...p-AlAs 0.4
Sb 0.6 layer, 15...i-In 0.53 Ga 0.47 As layer, 16...
... n-InP layer, 17, 18... electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 キヤリア濃度1017cm-3以上の第1の半導体層
とキヤリア濃度1016cm-3以下の第2の半導体層と
キヤリア濃度1017cm-3以上で厚さ100Å程度の第
3の半導体層とキヤリア濃度1016cm-3以下の第4
の半導体層とキヤリア濃度1017cm-3以上の第5の
半導体層とが順次積層され、前記第1の半導体層
と前記第5の半導体層の伝導型は等しくかつ前記
第3の半導体層の伝導型は前記第5の半導体の伝
導型とは異なるように形成された半導体素子にお
いて、第3の半導体層の禁制帯幅の前記第2の半
導体層及び前記第4の半導体層の禁制帯幅よりも
大であり、前記第1の半導体層及び前記第5の半
導体層の禁制帯幅は前記第2の半導体層及び前記
第4の半導体層の禁制帯幅よりも大であり、さら
に前記第1の半導体層は禁制帯幅の異なる2層の
半導体層で構成されその2層の半導体層のうち禁
制帯幅が大きいかつ厚さ1000Å以下の半導体層が
前記第2の半導体層に接していることを特徴とす
る半導体受光素子。
1. A first semiconductor layer with a carrier concentration of 10 17 cm -3 or more, a second semiconductor layer with a carrier concentration of 10 16 cm -3 or less, and a third semiconductor layer with a carrier concentration of 10 17 cm -3 or more and a thickness of about 100 Å. and the fourth below the carrier concentration 10 16 cm -3
and a fifth semiconductor layer having a carrier concentration of 10 17 cm -3 or higher are sequentially stacked, and the conductivity types of the first semiconductor layer and the fifth semiconductor layer are the same, and the conductivity type of the third semiconductor layer is the same as that of the third semiconductor layer. In a semiconductor element formed to have a conductivity type different from the conductivity type of the fifth semiconductor, the forbidden band width of the second semiconductor layer and the fourth semiconductor layer is the same as that of the third semiconductor layer. , and the forbidden band widths of the first semiconductor layer and the fifth semiconductor layer are larger than the forbidden band widths of the second semiconductor layer and the fourth semiconductor layer, and The first semiconductor layer is composed of two semiconductor layers having different forbidden band widths, and of the two semiconductor layers, the semiconductor layer having a larger forbidden band width and a thickness of 1000 Å or less is in contact with the second semiconductor layer. A semiconductor light-receiving element characterized by:
JP57213302A 1982-12-07 1982-12-07 Semiconductor element Granted JPS59104178A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57213302A JPS59104178A (en) 1982-12-07 1982-12-07 Semiconductor element
GB08332597A GB2132016B (en) 1982-12-07 1983-12-07 A semiconductor device
US06/806,746 US4682196A (en) 1982-12-07 1985-12-09 Multi-layered semi-conductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57213302A JPS59104178A (en) 1982-12-07 1982-12-07 Semiconductor element

Publications (2)

Publication Number Publication Date
JPS59104178A JPS59104178A (en) 1984-06-15
JPH0351115B2 true JPH0351115B2 (en) 1991-08-05

Family

ID=16636873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57213302A Granted JPS59104178A (en) 1982-12-07 1982-12-07 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS59104178A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566482A (en) * 1979-06-27 1981-01-23 Fujitsu Ltd Light controled semiconductor light emitting element
JPS5610981A (en) * 1979-07-06 1981-02-03 Nec Corp Photodetector
JPS57183077A (en) * 1981-04-24 1982-11-11 Western Electric Co Photodetector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566482A (en) * 1979-06-27 1981-01-23 Fujitsu Ltd Light controled semiconductor light emitting element
JPS5610981A (en) * 1979-07-06 1981-02-03 Nec Corp Photodetector
JPS57183077A (en) * 1981-04-24 1982-11-11 Western Electric Co Photodetector

Also Published As

Publication number Publication date
JPS59104178A (en) 1984-06-15

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