JPS631079A - Semiconductor light-receiving element and manufacture thereof - Google Patents

Semiconductor light-receiving element and manufacture thereof

Info

Publication number
JPS631079A
JPS631079A JP61143000A JP14300086A JPS631079A JP S631079 A JPS631079 A JP S631079A JP 61143000 A JP61143000 A JP 61143000A JP 14300086 A JP14300086 A JP 14300086A JP S631079 A JPS631079 A JP S631079A
Authority
JP
Japan
Prior art keywords
layer
light
impurity concentration
semiconductor
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61143000A
Other languages
Japanese (ja)
Other versions
JP2708409B2 (en
Inventor
Ichiro Fujiwara
一郎 藤原
Hiroshi Matsuda
広志 松田
Kazuhiro Ito
和弘 伊藤
Kazuyuki Nagatsuma
一之 長妻
Hirobumi Ouchi
博文 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Publication date
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Publication of JPS631079A publication Critical patent/JPS631079A/en
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Publication of JP2708409B2 publication Critical patent/JP2708409B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/105Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type

Abstract

PURPOSE:To form a PIN photodiode having high performance by forming and growing a light absorption layer in low concentration onto a substrate in high impurity concentration, selectively introducing an impurity to shape a P-type region and depleting the whole regions by reverse bias voltage. CONSTITUTION:An N<->-InP buffer layer 2 in low concentration, an N<->-In GaAs light absorption layer 3 in low impurity concentration, an N-InP layer 4' functioning as a window layer and an N<->-InP layer 4'' in low concentration are grown continuously onto an N<+>-InP substrate 1 in high impurity concentration through a vapor growth technique. An impurity is introduced selectively, using an SiNx film formed through plasma CVD as a mask to shape a P-type region 5. The whole regions are depleted by predetermined reverse bias voltage because the impurity concentration of the region 3 is low at that time. When beams are projected to an element, incident beams are absorbed approximately in the region 3, and optical pumping carriers are col lected to a junction 10 by a drift field. Accordingly, optical pumping carriers are collected approximately without recombination.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体受光素子に係わり、特に低バイアス電圧
、ひいてはゼロバイアス電圧で感度を有し、暗電流の小
さいものに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor light-receiving device, and particularly to one that has sensitivity at a low bias voltage, or even zero bias voltage, and has a small dark current.

〔従来の技術〕[Conventional technology]

一般にホトダイオードでは、高感度で高速度応答を実現
するため、PIN型構造が採用される6本構造では、低
バイアス電圧で動作することが望ましいため、1層は高
抵抗化(高純度化)され、低い電圧で空乏層化するよう
に設計される。ところで、Inp系やGaSb系などの
化合物半導体を利用したホトダイオードでは、光を吸収
する1層に禁止帯幅(Ell )の狭い半導体を利用し
て感度を有する波長限界を長波長側に伸ばすと共に、選
択的な不純物の導入によって形成される接合を、禁止帯
幅(E# )の大きい物質内、あるいはそれを介して禁
止帯幅の小さい物質との界面近傍に形成して暗電流を小
さくする方策が取られている(特開昭53−16593
 ) 、ところが、この様に禁止帯幅の異なる物質から
なるヘテロ界面を持つと共に1両物質共に不純物濃度が
低い化合物半導体PIN型ホトダイオードでは、以下に
述べる様な問題がある。
In general, in photodiodes, in order to achieve high sensitivity and high speed response, it is desirable to operate with a low bias voltage in the 6-wire structure that uses a PIN type structure, so the first layer has a high resistance (high purity). , is designed to become a depletion layer at low voltage. By the way, in photodiodes using compound semiconductors such as Inp-based and GaSb-based, a semiconductor with a narrow bandgap (Ell) is used in one layer that absorbs light to extend the wavelength limit of sensitivity toward longer wavelengths. A measure to reduce dark current by forming a junction formed by selectively introducing impurities within a material with a large forbidden band width (E#) or near the interface with a material with a small forbidden band width through it. (Unexamined Japanese Patent Publication No. 53-16593)
) However, in a compound semiconductor PIN type photodiode having such a hetero-interface made of materials having different bandgap widths and in which both materials have low impurity concentrations, there are problems as described below.

低バイアス電圧で高速動作をするには、少なくとも1層
CEx小の物質)の不純物濃度を10taaw−’オー
ダ以下にし、全体が空乏層化するように設計される。従
来の手法では、逆方向の耐電圧を上げ、安定な動作を得
る目的から、接合が形成されるEwの大きい物質の不純
物濃度も1層と同じ程度に設計される。ところが、アプ
ライド フィジクス レター43.6 (1983年)
594頁から596頁(Appl、Phys、Lett
、43 、6 (1983)pp594〜596)にお
いて論じられているように、不純物′a度が10za■
−3になると極めて拡散速度が異常に速い拡散が起り、
接合の制御が困難になってくること、及びヘテロ界面の
格子の不整合に依存して界面に沿ったラテラル拡散が起
り、実質的な接合が大きくなってしまう問題が生じた。
In order to operate at high speed with a low bias voltage, the impurity concentration of at least one layer (substance with small CEx) is set to be on the order of 10 taaw-' or less, and the entire layer is designed to be a depletion layer. In the conventional method, the impurity concentration of a material with a large Ew with which a junction is formed is designed to be about the same as that of a single layer in order to increase the reverse dielectric strength and obtain stable operation. However, Applied Physics Letter 43.6 (1983)
Pages 594 to 596 (Appl, Phys, Lett
, 43, 6 (1983) pp594-596), when the impurity level is 10za
-3, diffusion occurs at an extremely fast diffusion rate.
Problems have arisen in that it becomes difficult to control the junction, and that lateral diffusion along the interface occurs depending on the lattice mismatch of the heterointerface, resulting in a substantial junction.

こうした現象は、接合が実質的に広がる結果として、素
子の容量を大きくして高速応答性を劣化させると共に、
暗電流を増大させS/N比の劣化を起す。また、拡散の
制御性が悪くなるため、接合がE□の小さい物質から離
れた所に形成された場合には、逆バイアス電圧を大きく
しないと空乏層は8層小の1層に届かず、感度は低下す
る。特に、ヘテロ界面を有する化合物半導体では、ヘテ
ロ層間でエネルギギャップがあること及びキャリアの寿
命が短いため、接合から伸びる空乏層が光吸収層となる
1層(8層小の物質)に届かない場合、感度は著しく低
下する。また、逆に接合がE、小の物質内深くに形成さ
れた場合には、化合物半導体の吸収係数は大きい(直接
遷移型電子構造が多い)ため、光励起されたキャリアの
一部は接合に到達する前に再結合を起し、感度を低下さ
せる。
These phenomena increase the capacitance of the device and degrade high-speed response as a result of the junction substantially widening.
This increases dark current and causes deterioration of the S/N ratio. In addition, because the controllability of diffusion deteriorates, if the junction is formed far from a material with a small E□, the depletion layer will not reach one of the eight layers unless the reverse bias voltage is increased. Sensitivity decreases. In particular, in compound semiconductors that have a hetero interface, there is an energy gap between the hetero layers and a short carrier lifetime, so if the depletion layer extending from the junction does not reach one layer (8 layers of material) that becomes the light absorption layer. , the sensitivity is significantly reduced. On the other hand, if the junction is formed deep within a substance with a small Recombination occurs before the reaction occurs, reducing sensitivity.

従って、低バイアス電圧で、高感度、高速応答の素子の
実現は困難になる。
Therefore, it becomes difficult to realize an element with low bias voltage, high sensitivity, and high speed response.

また、従来のInGaAs  PINホトダイオードに
おいてはトムソンC3FのPOULAINから行ったよ
うに不純物濃度の低いI n G a A s光吸収層
内に選択拡散技術を用いてpn接合を形成して、デバイ
スのバイアス電圧Oボルトでの動作を実現していた(エ
レクトロニクス レター 第21巻第441〜2頁、1
985年(ElactronicsLetters、 
VoQ、21(1985) 441〜442)参照)。
In addition, in conventional InGaAs PIN photodiodes, a pn junction is formed using selective diffusion technology in the InGaAs light absorption layer with a low impurity concentration, as was done with Thomson C3F's POULAIN, and the bias voltage of the device is (Electronics Letter Vol. 21, pp. 441-2, 1)
985 (Electronics Letters,
VoQ, 21 (1985) 441-442)).

さらに、窓層にInGaAsを用いた光知例としてはB
e1l研究所のF、Capasso らによるアバラン
シュホトダイオードが唯一の例であるにの場合、I n
GaAsとI n A Q A sとの価電子帯のエネ
ルギー差が0.2eVと小さいことを利用して、光励起
キャリアがアバランシェ増倍領域へ効果的に移動するこ
とを狙って、Pile−uρの軽減を目的としたもので
、暗電流低減に積極的に利用したものではなかった。
Furthermore, as an example of optical technology using InGaAs for the window layer, B
The only example is the avalanche photodiode by F. Capasso et al.
Taking advantage of the small energy difference of 0.2 eV in the valence band between GaAs and I n A Q A s, we aim to effectively move photoexcited carriers to the avalanche multiplication region by The purpose was to reduce dark current, and it was not actively used to reduce dark current.

また、近年1〜1.6μm帯の波長の光を利用した光通
信、情報処理技術の発展がめざましい。
Further, in recent years, optical communication and information processing technology using light with a wavelength in the 1 to 1.6 μm band has made remarkable progress.

この際の受光素子として、Inp+ InGaAsを主
体とした化合物半導体素子が期待されている。
As the light receiving element in this case, a compound semiconductor element mainly composed of Inp+ InGaAs is expected.

特に、半導体レーザの発掘状態をモニターする受光素子
としては、バイアス電圧なしで動作する。
In particular, as a light receiving element for monitoring the excavation state of a semiconductor laser, it operates without a bias voltage.

低暗電流、低容量の素子が望ましい、従来、このような
素子は、エレクトロニクス レター、21(1985年
)第441から442頁 (Electronics Latters 2上(1
985) pp441〜442)において論じられ、第
5図で示したようにInP基板上にInPとI n G
 a A sをダブルへテロ構造に成長させた後、上部
InP層上より、上部InPMを経て、I n G a
 A s層内までに不純物を拡散させて、I n G 
a A s層内にPN接合面に位置させることによって
得られることが知られていた。しかし、いかにして、再
現性良く、I n G a A s 77)の所定の位
置にPN接合を位置させるかについては配慮されていな
かった。
It is desirable to have an element with a low dark current and a low capacitance.
985) pp. 441-442) and shown in FIG.
After growing a A s into a double heterostructure, I n G a is grown from above the upper InP layer through the upper InPM.
By diffusing impurities into the A s layer, I n G
It was known that this could be obtained by locating the PN junction within the a As layer. However, no consideration was given to how to position the PN junction at a predetermined position in InGaAs 77) with good reproducibility.

さらに、不純物濃度の比較的低いInPMとI n G
 a A s層のへテロ接合に、垂直方向から不純物の
熱拡散が行われると、ヘテロ接合面に達した時、接合面
に沿った横方向拡散が発生する現象が存在した。このた
め、拡散マスクを用いた選択性熱拡散によるプレーナ型
PINホトダイオードでは、ヘテロ接合面での横方向拡
散による静電容量の増大、暗電流の増大が問題となって
いた。上記文献ではメサ型構造を採用して、この問題を
回避しているが、生産性の優れたプレーナ型での対応策
はこれまで知られていなかった。
Furthermore, InPM and InG with relatively low impurity concentrations
When thermal diffusion of impurities is performed in the vertical direction to the heterojunction of the aAs layer, there is a phenomenon in which lateral diffusion occurs along the junction surface when the impurity reaches the heterojunction surface. For this reason, planar PIN photodiodes based on selective thermal diffusion using a diffusion mask have had problems with increased capacitance and dark current due to lateral diffusion at the heterojunction surface. In the above-mentioned literature, a mesa type structure is adopted to avoid this problem, but a countermeasure for a planar type with excellent productivity has not been known so far.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は低不純物濃度の物質量のへテロ界面を考
慮した接合形成の制御及び界面に依存する望ましくない
拡散について配慮がされておらず。
The above-mentioned conventional technology does not take into account the control of junction formation in consideration of the hetero-interface of the amount of material with a low impurity concentration, nor the undesirable diffusion depending on the interface.

感度の低下、応答速度の劣化、適切な動作バイアス電圧
の変動など素子性能低下をきたす問題があった。
There have been problems with deterioration of element performance, such as a decrease in sensitivity, deterioration in response speed, and fluctuations in the appropriate operating bias voltage.

また、−般に不純物濃度がlXl0”cm−3まで低減
されると拡散速度が増大し、pn接合フロントの制御が
難しくなることが知られている選択拡散技術でpn接合
をI n G a A s光吸収層内に形成する場合、
I n G a A s層内の2層が厚くなること入射
光が吸収されてしまうため量子効率が低下する。上記従
来技術ではI n G a A s内での拡散フロント
の制御性が悪く、2層が厚くなり過ぎ量子効率が低下し
てしまう問題点があった。
In addition, it is known that when the impurity concentration is reduced to lXl0"cm-3, the diffusion rate increases, making it difficult to control the pn junction front. s When formed within the light absorption layer,
As the two layers in the InGaAs layer become thicker, incident light is absorbed, resulting in a decrease in quantum efficiency. The above-mentioned conventional technology has problems in that the controllability of the diffusion front within InGaAs is poor, and the two layers become too thick, resulting in a decrease in quantum efficiency.

さらに、従来の長波長ホトダイオードは、結晶の高純度
化が可能な気相成長法を用い、窓層/光吸収層としてI
 n P / I n G a A s構造を採用して
いた。しかし、I n G a A s層の成長からI
nPMの成長へ移るとき残留ヒ素ガスの影響で、I n
 G a A s層とInPMの間に組成が定まらない
変性層が生じ易いという問題点があった。この変性層は
発生電流として、ホトダイオードのr6電流を増大させ
る。
Furthermore, conventional long-wavelength photodiodes use a vapor phase growth method that allows for highly purified crystals, and use I as a window layer/light absorption layer.
It adopted an nP/InGaAs structure. However, from the growth of the I n Ga As layer, the I
When moving on to nPM growth, due to the influence of residual arsenic gas, I n
There was a problem in that a modified layer with an undefined composition was likely to be formed between the GaAs layer and the InPM. This modified layer increases the r6 current of the photodiode as a generated current.

また、上記従来技術においては、PN接合面の位置制御
性、ヘテロ接合面での横方向拡散の抑止について配慮さ
れておらず、I nGaAs層深くまでPN接合が達し
てしまうことにより起る量子効率の低下やヘテロ接合面
での接合面積の異常増加により起る静電容量、暗電流の
増大などの問題があった6 本発明の目的は、不純物濃度、界面層、主接合の位置を
配慮することによって、低バイアス電圧、ひいてはゼロ
バイアス電圧で、高感度、高速で、また暗電流の小さい
安定な半導体受光素子を実現することにある。
In addition, in the above-mentioned conventional technology, no consideration is given to the position controllability of the PN junction surface and the suppression of lateral diffusion at the heterojunction surface, and the quantum efficiency is reduced due to the PN junction reaching deep into the InGaAs layer. There have been problems such as an increase in capacitance and dark current caused by a decrease in the junction area and an abnormal increase in the junction area at the heterojunction surface.6 The purpose of the present invention is to consider the impurity concentration, the interface layer, and the position of the main junction. By doing so, the object is to realize a stable semiconductor light-receiving element with low bias voltage, or even zero bias voltage, high sensitivity, high speed, and low dark current.

C問題点を解決するための手段〕 上記目的は、第1〜4図によって示す様に、ホトダイオ
ードを構成する不純物濃度分布を工夫し。
Means for Solving Problem C] The above object is to devise the impurity concentration distribution constituting the photodiode, as shown in FIGS. 1 to 4.

それによって接合位置を制御し、高性能を達成する。This allows the joint position to be controlled and achieves high performance.

即ち、選択的に不純物を導入して接合が形成されるEg
の大きい物質4は、不純物濃度の小さい領域4′と不純
物濃度の比較的大きい薄い領域4′からなる。光吸収層
として作用する不純物濃度が小さく、かつElの小さい
物質3は領域4′と接している0本不純物濃度構造にお
いて、領域4′の表面から他方の導電形の不純物を導入
すると、接合は拡散係数の速い41領域を越え、拡散速
度の遅い不純物濃度の大きい領域4′内に形成される。
That is, Eg in which a junction is formed by selectively introducing impurities.
The material 4 with a high impurity concentration consists of a region 4' with a low impurity concentration and a thin region 4' with a relatively high impurity concentration. In a zero impurity concentration structure in which the material 3 with a low impurity concentration and low El that acts as a light absorption layer is in contact with the region 4', when an impurity of the other conductivity type is introduced from the surface of the region 4', the junction is formed. It is formed beyond the region 41, which has a fast diffusion coefficient, and within the region 4', which has a high impurity concentration and has a slow diffusion rate.

本状態において低バイアス電圧で動作するためには、少
なくとも拡散電位(built−in [圧)によって
、接合から伸びる空乏層は領域4′と3の境界に達して
いることが必要とされる。この場合には零バイアス電圧
で感度が得られ、外部印加電圧は領域3を空乏層化する
ために有効に使われる。
In order to operate at a low bias voltage in this state, it is necessary that the depletion layer extending from the junction reaches the boundary between regions 4' and 3, at least due to the built-in potential. In this case, sensitivity can be obtained with zero bias voltage, and the externally applied voltage is effectively used to make region 3 a depletion layer.

−方、空乏層が境界に達していない場合には、外部から
の印加電圧によって初めて空乏層が境界に伸びた時、領
域3内で発生した光励起キャリアは接合に集められ、光
電流に寄与するようになる。
- On the other hand, if the depletion layer does not reach the boundary, when the depletion layer first extends to the boundary due to an externally applied voltage, the photoexcited carriers generated in region 3 are collected at the junction and contribute to the photocurrent. It becomes like this.

InP系やG a A s系などの比較的Eオの大きい
化合物半導体の拡散電位は約1vと考えることができ、
拡散電位で少なくとも4aが空乏層化するには領域4′
の不純物濃度Nと厚さdの関係は次式で与えられる。
The diffusion potential of compound semiconductors with relatively large Eo, such as InP and GaAs, can be considered to be approximately 1V.
In order for at least 4a to become a depletion layer at the diffusion potential, the region 4'
The relationship between the impurity concentration N and the thickness d is given by the following equation.

E N−d2<□        ・・・・・・ (1)こ
こで、q:電子電荷素置、E:誘電率例えばInPの場
合には、上式は次の様になる。
E N-d2<□ (1) where q: electron charge element, E: dielectric constant For example, in the case of InP, the above equation becomes as follows.

N<1.4  X  1 0 五6/d2      
  ・・・・・・  (2)上述した文献や実験から、
接合位置の制御やヘテロ界面のラテラル拡散の防止には
、不純物濃度は少なくともI X 1018cxr−”
以上が効果的であることが分かった(これ以下の濃度で
は拡散などに対して顕著な効果がない)、このためには
、(2)式より厚さは約0.3μm以下であることが必
要となる。領域4′による接合の位置の制御精度を考え
ると厚さは0.1μmが必要となる。この場合、不純物
濃度は(2)式より約I X 1017tym−3以下
となる。こうした結果は実験的にも実証され、4′層ノ
不純物′a度ヲI X 101B−I X 1017個
−8,厚さが0.1〜0.3μmとすることが、適切で
あることが分かった。(1)式から分かる様に誘電率は
半導体間で大した違いはないため、本関係は他生導体に
も適用できる。
N<1.4 X 1 0 56/d2
(2) From the literature and experiments mentioned above,
In order to control the junction position and prevent lateral diffusion at the hetero interface, the impurity concentration should be at least I x 1018cxr-”
The above was found to be effective (concentrations below this have no significant effect on diffusion, etc.).For this purpose, the thickness must be approximately 0.3 μm or less from equation (2). It becomes necessary. Considering the accuracy of controlling the bonding position by the region 4', the thickness needs to be 0.1 μm. In this case, the impurity concentration will be approximately I x 1017 tym-3 or less from equation (2). These results have been experimentally verified, and it has been found that it is appropriate to set the impurity level in the 4' layer to 101B-1017 pieces-8 and a thickness of 0.1 to 0.3 μm. Do you get it. As can be seen from equation (1), there is not much difference in dielectric constant between semiconductors, so this relationship can also be applied to other conductors.

さらに、上記目的はI nGaAs光吸収層とInP窓
層の間にT nAQAs層を挿入し、InAl2As5
内にpn接合を形成することによっても達成される。
Furthermore, the above purpose is to insert a T nAQAs layer between the InGaAs light absorption layer and the InP window layer,
This can also be achieved by forming a pn junction within.

また、上記目的はI n G a A s光吸収層を比
較的不純物濃度の高い層と不純物9度の低い層の二層で
構成し、pn接合を比較的不純物濃度の高い光吸収層内
に形成することによって達成される。
In addition, the above purpose is to configure the InGaAs light absorption layer with two layers, a layer with a relatively high impurity concentration and a layer with a low impurity concentration, and to form a pn junction in the light absorption layer with a relatively high impurity concentration. This is achieved by forming.

また、上記目的は、上部InP層の下部に、不純物濃度
が若干高いInP層をもうけるとともに、I n G 
FI A s層上部に、不純物濃度が、比較的筋いI 
n G a A s !?4をもうけ、不純物拡散をこ
の不純物濃度が高いTnGaAs層上端または内部に形
成することによって達成される。
Further, the above purpose is to form an InP layer with a slightly higher impurity concentration below the upper InP layer, and to
The impurity concentration is relatively high on the top of the FIAs layer.
nGaas! ? 4, and by forming impurity diffusion at the top or inside the TnGaAs layer having a high impurity concentration.

〔作用〕[Effect]

第1図において、Exの大きい物質からなる比較的不純
物濃度の大きい領域4′は、pn接合の位置を4′内に
位置させるように動作する。また、4′内に接合が形成
されるため、領域4と領域3の間のへテロ界面に沿って
異常な拡散が防止できる。
In FIG. 1, a region 4' made of a material with a large Ex and having a relatively high impurity concentration operates to position the pn junction within the region 4'. Further, since a junction is formed within 4', abnormal diffusion can be prevented along the hetero interface between regions 4 and 3.

これら技術的手段により、接合の位置を安定に制御でき
るようになると共に、ヘテロ界面に沿う異常な拡散の広
がりを防止できるため、再現性良く特性の均一かつ優れ
たホトダイオードを得ることができる。
These technical means make it possible to stably control the position of the junction and prevent abnormal diffusion along the hetero interface, making it possible to obtain a photodiode with uniform and excellent characteristics with good reproducibility.

比較的不純物濃度が高いInGaAs層においては拡散
速度は遅く、I n G a A s層内に制御性よ<
pn接合を形成することができる。したがってp −I
 n G a A s層の厚さを薄くすることができる
ため、量子効率を低下させることなく、バイアス電圧O
■で動作可能となる。また、バイアス電圧を印加すると
空乏層は不純物濃度の低いI n G a A sへ伸
び、低バイアス電圧でも空乏層を大きく伸ばすことがで
きる。したがって、低バイアス電圧で容量を小さく抑え
ることが可能になり、CR時定数で制限される高速応答
も実現可能となる。
In the InGaAs layer, which has a relatively high impurity concentration, the diffusion rate is slow, and there is a controllability within the InGaAs layer.
A pn junction can be formed. Therefore p −I
Since the thickness of the nGaAs layer can be made thinner, the bias voltage O can be reduced without reducing the quantum efficiency.
■It becomes possible to operate. Further, when a bias voltage is applied, the depletion layer extends to InGaAs having a low impurity concentration, and the depletion layer can be greatly extended even with a low bias voltage. Therefore, it is possible to keep the capacitance small with a low bias voltage, and it is also possible to realize a high-speed response limited by the CR time constant.

気相成長法においては、InGaAs層の成長からI 
nAl2As#の成長に移るときに、ヒ素ガスを切らな
いため残留ヒ素ガスによる変性層は生じない、InAρ
A s 、Qの成長からInP層へ移るときには残留ヒ
素の影響は残るが、pn接合がInARAs層内に形成
されるためにInGaAs層 I n Pのへテロ界面
は、ホトダイオードとしての暗電流の劣化に影響を与え
ない、したがって。
In the vapor phase growth method, I
When moving on to the growth of nAl2As#, since the arsenic gas is not turned off, a modified layer due to residual arsenic gas does not occur.
When moving from the growth of A s and Q to the InP layer, the influence of residual arsenic remains, but since the pn junction is formed within the InARAs layer, the heterointerface of the InGaAs layer InP is affected by dark current degradation as a photodiode. therefore does not affect.

本発明では低暗電流のホトダイオードを実現できる。According to the present invention, a photodiode with low dark current can be realized.

また、結晶成長層の不純物濃度が低いため、容量は低く
抑えることができ、CR時定数で制御される高速応答も
実現できる。
Furthermore, since the impurity concentration of the crystal growth layer is low, the capacitance can be kept low, and high-speed response controlled by the CR time constant can also be realized.

また、半導体としてInP系を用いた場合、上部InP
層の下部にもうける不純物濃度が若干高いInP層は、
上部InP層とI n G a A s層間での界面で
のストレスなどに由来する横方向異常拡散を緩和し、防
止する役目をする6−方。
Furthermore, when an InP-based semiconductor is used, the upper InP
The InP layer with a slightly high impurity concentration formed at the bottom of the layer is
6-way serves to alleviate and prevent abnormal lateral diffusion caused by stress at the interface between the upper InP layer and the InGaAs layer.

I n G a A s層の比較的上部に形成される不
純物濃度が比較的高いr nGaAsMでは拡散速度が
遅いため、その層の上端または内部でPN接合面を停止
することが容易である。
In r nGaAsM, which has a relatively high impurity concentration and is formed at a relatively upper portion of the I n Ga As layer, the diffusion rate is slow, so it is easy to stop the PN junction at the upper end or inside the layer.

〔実施例〕〔Example〕

以下1本発明の一実施例を図を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.

実施例1 本実施例ではInP系の材料を用いた場合について説明
するが、本発明の本質は他のGaSb系など他の化合物
半導体を用いた場合においても変るものではない。
Example 1 This example describes the case where an InP-based material is used, but the essence of the present invention does not change even when other compound semiconductors such as other GaSb-based materials are used.

高不純物濃度のn+−■nP基板1上に、気相成長技術
(例えばM o −CV D法、ハライド系あるいはハ
ライド系のVPE法)により、連続的に低濃度のn−−
InPバッファ層2.低不純物濃度のn−−InGaA
s光吸収層3.窓層として働ら<n−InPH4’及び
低濃度のn−−1nP層4′を成長させる。領域3は不
純物濃度が1×10”Ql−8,厚さ2.5pmである
。また、4′層及び4′層は各々不純物濃度が2 X 
I Q ”cxs−”。
On the n+-■nP substrate 1 with a high impurity concentration, continuously low-concentration n--
InP buffer layer 2. n--InGaA with low impurity concentration
s light absorption layer 3. Grow <n-InPH4' and a low concentration n-1nP layer 4' to serve as a window layer. Region 3 has an impurity concentration of 1 x 10"Ql-8 and a thickness of 2.5 pm. The 4' layer and 4' layer each have an impurity concentration of 2 x
IQ “cxs-”.

I X 1018cm−”、 7m[さは0.2μm、
1.8μmである。プラズマCVDによって形成したS
 x Nえ膜をマスクとして、選択的に不純物を導入し
、p型頭域5を形成する。領域5の光端は領域4′に接
するかあるいは4′の内部に存在する。p形不純物領域
の形成においては、ZnやCdなどの熱拡散、あるいは
BeやMgなどのイオン打込み法が取られる。pn接合
の先端を10で示す。次にパッシベーション膜としてS
 x N x / P S G /Si○2三層膜6全
層膜6、反射防止膜としてSiNう7を使用した。p形
電極にはT i / P d/ A u蒸着膜8.nJ
T161!極にはAuGeNi/P d / A u蒸
着膜9を形成した。
I x 1018cm-”, 7m [length 0.2μm,
It is 1.8 μm. S formed by plasma CVD
Using the xN film as a mask, impurities are selectively introduced to form a p-type head region 5. The optical end of the region 5 is in contact with or inside the region 4'. In forming the p-type impurity region, thermal diffusion of Zn, Cd, etc., or ion implantation of Be, Mg, etc. is used. The tip of the pn junction is indicated by 10. Next, as a passivation film, S
xNx/PSG/Si○2 three-layer film 6, full-layer film 6, and SiN layer 7 were used as the antireflection film. 8. T i / P d / Au vapor deposited film on the p-type electrode. nJ
T161! An AuGeNi/P d /Au vapor deposited film 9 was formed on the pole.

本発明では拡散電位により、接合からの空乏層端はIn
GaAs領域3に達しており、バイアス電圧を印加する
ことによって空乏層は領域3の全領域に伸びる。領域3
の不純物濃度が低いため。
In the present invention, due to the diffusion potential, the edge of the depletion layer from the junction is In
The depletion layer reaches the GaAs region 3, and by applying a bias voltage, the depletion layer extends to the entire region 3. Area 3
Because the impurity concentration is low.

逆バイアス5vで全領域が空乏層化する。本素子に光が
入射した場合、入射光は領域3内でほとんど吸収され、
光励起キャリアはドリフト電界によって、接合10に集
められる。このため、光励起キャリアはほとんど再結合
なく集められるので量子効率が高く、かつドリフトによ
って移行するため高速応答が可能になる。1.55μm
の半導体レーザを用いた実験により、量子効率90%、
パルス立上り、立下り時間ins以下を得た。
With a reverse bias of 5V, the entire region becomes a depletion layer. When light is incident on this element, most of the incident light is absorbed within region 3,
Photoexcited carriers are collected at junction 10 by the drift electric field. For this reason, photoexcited carriers are collected with almost no recombination, resulting in high quantum efficiency, and since they migrate by drift, high-speed response is possible. 1.55μm
Experiments using a semiconductor laser showed a quantum efficiency of 90%,
Pulse rise and fall times of less than ins were obtained.

本実施例によれば、接合は比較的不純物濃度の高い薄い
領域に形成され、かつ、ヘテロ界面の影響を軽減できる
ため、暗電流が小さくなる。また、無バイアス電圧で空
乏層は光吸収領域に達するため、零バイアスでも高い感
度を持つ。更に、低バイアス電圧で光吸収領域は空乏層
化するため、TTLなどのIC電源と両立できる電圧(
例えば5V)で、高速応答を実現できる。更に、表面に
は不純物濃度が低く、E+tの大きい物質が形成される
(領域4′)ため、逆方向の耐電圧が大きくなる。
According to this embodiment, the junction is formed in a thin region with a relatively high impurity concentration, and the influence of the hetero interface can be reduced, so that the dark current is reduced. Furthermore, since the depletion layer reaches the light absorption region with no bias voltage, it has high sensitivity even with zero bias. Furthermore, since the light absorption region becomes a depletion layer at a low bias voltage, a voltage that is compatible with IC power supplies such as TTL (
For example, 5V), high-speed response can be achieved. Furthermore, since a substance with a low impurity concentration and a large E+t is formed on the surface (region 4'), the withstand voltage in the reverse direction becomes large.

実施例2 第2図によって説明する。Example 2 This will be explained with reference to FIG.

第2図は、InGaAs  PINホトダイオードの縦
断面図である。
FIG. 2 is a longitudinal cross-sectional view of an InGaAs PIN photodiode.

n型1nP基板(Sドープ)1上にn−−InPバッフ
ァ層2.n−−InGaAsnGaAs光吸収層nGa
As層14.n−−InP窓層15をMOCVD法(ま
たは、クロライドVPE法。
An n--InP buffer layer 2 is formed on an n-type 1nP substrate (S-doped) 1. n--InGaAsnGaAs light absorption layer nGa
As layer 14. The n--InP window layer 15 is formed by MOCVD (or chloride VPE).

ハイドライドVPE法、MBE法)により連続成長させ
る。pn接合16はZnまたはCdの選択熱拡散または
Be、Mgのイオン注入によりn −InGaAs光吸
収層内に形成する。拡散定数が大はくならないようにn
 −I n G a A s層の不純物濃度をIXIO
lGam−8に設定し、pn接合の拡散フロントの制御
性を±0.1μmにしている。
Continuous growth is performed using hydride VPE method, MBE method). The pn junction 16 is formed in the n-InGaAs light absorption layer by selective thermal diffusion of Zn or Cd or ion implantation of Be or Mg. n to prevent the diffusion constant from becoming large.
-The impurity concentration of the I n Ga As layer is IXIO
lGam-8, and the controllability of the diffusion front of the pn junction is set to ±0.1 μm.

パッシベーション膜17は、Si○x/PSG/ S 
i N xの三Mm造を採用し、S i N、 / I
nPの界面準位を5 X 10 ”国−1以下に抑え、
表面リーク電流による暗電流の劣化を防止している。
The passivation film 17 is Si○x/PSG/S
Adopts 3Mm structure of i N x, S i N, / I
The nP interface level is suppressed to less than 5 × 10” country-1,
This prevents dark current deterioration due to surface leakage current.

反射防止膜18はパッシベーション膜に用いたS i 
Nx膜を採用し、膜厚を1.5μm帯に最適化した結果
、反射率をz以上に抑えである。
The antireflection film 18 is made of Si used as a passivation film.
By adopting an Nx film and optimizing the film thickness to the 1.5 μm band, the reflectance can be suppressed to z or higher.

p型オーミック電極はA u / P t / T i
 19、n型オーミック電極はA u / P d /
 A u G s N 1110を用い、良好なオーミ
ック特性を実現している。
The p-type ohmic electrode is A u / P t / T i
19. The n-type ohmic electrode is A u / P d /
Good ohmic characteristics are achieved by using A u G s N 1110.

入射した光はI nGaAs光吸収層によって吸収され
る。p−InGaAs層での光吸収は損失となるa I
nGaAsの吸収係数が10’ay+−’であるので、
厚さを0.1μm以内にすれば10%程度の損失となり
、その他の損失の要因はほとんど存在しないため、90
%以上の量子効率を期待できる。また、I nGaAs
の禁止帯幅がo、75eVとInP (1,35ev)
  に比べて小さいため、暗電流はInP層にpn接合
にある場合より若干大きくなるが、バイアス電圧10V
で1nA程度の実用的レベルに低く抑えることができる
The incident light is absorbed by the InGaAs light absorption layer. Light absorption in the p-InGaAs layer results in loss a I
Since the absorption coefficient of nGaAs is 10'ay+-',
If the thickness is within 0.1 μm, the loss will be about 10%, and there are almost no other loss factors, so 90%
% or more quantum efficiency can be expected. Also, InGaAs
The forbidden band width of InP (1,35ev) is o, 75eV.
Since the dark current is smaller than that of the InP layer, the dark current is slightly larger than that of the pn junction in the InP layer, but the bias voltage of 10V
This can be suppressed to a practical level of about 1 nA.

n −I n G a A s層の不純物濃度が低いた
め、低−バイアス電圧で空乏層が大きく伸び、1o■で
0.5 P F 程度の容量を期待できる。
Since the impurity concentration of the n-I n Ga As layer is low, the depletion layer is greatly extended at a low bias voltage, and a capacitance of about 0.5 PF can be expected at 1 o.

ホトダイオードの高速応答性はCR時定数で制限される
ため、負荷抵抗を50Ωとすると、CR時定数は25P
Sとなり、10 G Hz以上の高速応答が期待できる
The high-speed response of the photodiode is limited by the CR time constant, so if the load resistance is 50Ω, the CR time constant is 25P.
S, and high-speed response of 10 GHz or more can be expected.

実施例3 第3図により説明する。Example 3 This will be explained with reference to FIG.

第3図はI n P / I n A n A s /
 I n G a A 5PINホトダイオードの縦断
面図である。
Figure 3 shows I n P / I n A n A s /
FIG. 2 is a longitudinal cross-sectional view of an InGaA 5PIN photodiode.

n型InP基板1 (SまたはSnドープ)上に、MO
CVD法(またはVPE法、MBE法)により、n−−
InPバッファ層2.n−−InGaAsnGaAs光
吸収層nAQAs窓層24.InB”窓層25を連続成
長させる。n−層の不純物濃度はlXl0I”■−8で
ある。次にプラズマCVD法により形成したSiN、膜
を拡散マスクとしてZnの選択熱拡散を行ない、p+ 
−InB層。
On n-type InP substrate 1 (S or Sn doped), MO
By CVD method (or VPE method, MBE method), n--
InP buffer layer 2. n--InGaAsnGaAs light absorption layer nAQAs window layer 24. An InB" window layer 25 is continuously grown. The impurity concentration of the n-layer is lXl0I" -8. Next, selective thermal diffusion of Zn was carried out using the SiN film formed by plasma CVD method as a diffusion mask, and p+
-InB layer.

p+  InAaAs層26を形成する。次に、プラズ
マCVD法によるSiNx、熱CVD法にょるSiOx
 / P S Gの三層構造7によりパッシベーション
を施した後、5iOz/PSGを除去しS i N x
の反射防止膜8を形成する。
A p+ InAaAs layer 26 is formed. Next, SiNx by plasma CVD method and SiOx by thermal CVD method.
/ After passivating with the three-layer structure 7 of PSG, 5iOz/PSG is removed and S i N x
An antireflection film 8 is formed.

最後にp型オーミック電極(A u / P t / 
T i )29、n型オーミック電極(Au/Pd/A
uGeN1)210を形成する。
Finally, p-type ohmic electrode (A u / P t /
T i )29, n-type ohmic electrode (Au/Pd/A
uGeN1) 210 is formed.

ホトダイオードに入射した光は、バイアスされて空乏層
化しているI n G a A s層で吸収され、キャ
リアを発生する。発生したキャリアは空乏層内をドリフ
トして進行し、pn接合に倒達し、電極から光電流とし
て外部回路に取り出される。
Light incident on the photodiode is absorbed by the InGaAs layer, which is biased and becomes a depletion layer, and carriers are generated. The generated carriers drift and advance within the depletion layer, reach the pn junction, and are taken out from the electrode as a photocurrent to an external circuit.

本実施例のホトダイオードは、低暗電流の良好な特性が
得られる。InGaAs53μm程度にとれば内部量子
効率は100%近くなる。またSiNx膜の無反射コー
ティングにより表面反射も1%以下に抑えることができ
るため、外部量子効率は90%を期待できる。また、結
晶成長層の不純物濃度がlX10130−3と低いため
、IOVで0.5pFの低容量を実現できる。また、暗
電流もI n A Q A s / I n G a 
A s へテロ界面での暗電流の劣化を防ぐことが可能
になるため、10Vで1nA以下に抑えることができる
。また、高周波特性についても通常CRの時定数で帯域
制御され、容量が低いため10 G Hz以上の高速動
作が可能である。
The photodiode of this example has good characteristics of low dark current. If the thickness of InGaAs is about 53 μm, the internal quantum efficiency will be close to 100%. In addition, the non-reflective coating of the SiNx film can suppress surface reflection to 1% or less, so an external quantum efficiency of 90% can be expected. Furthermore, since the impurity concentration of the crystal growth layer is as low as 1X10130-3, a low capacitance of 0.5 pF can be achieved at IOV. In addition, the dark current is also I n A Q A s / I n Ga
Since it is possible to prevent the dark current from deteriorating at the A s hetero interface, it is possible to suppress the dark current to 1 nA or less at 10V. Furthermore, the high frequency characteristics are usually band controlled by the CR time constant, and high-speed operation of 10 GHz or higher is possible due to the low capacity.

以上、本実施例では低電圧動作で良好な電気、光学特性
を示すことが分かる。
As described above, it can be seen that this example exhibits good electrical and optical characteristics with low voltage operation.

また、A Q I n A s層の不純物′a度が比較
的高いため、pn接合を±0.2μmの精度で形成でき
、ホトダイオードを工業的に生産する場合も高歩留りが
期待できる。
In addition, since the impurity content of the A Q I n A s layer is relatively high, a pn junction can be formed with an accuracy of ±0.2 μm, and a high yield can be expected when photodiodes are industrially produced.

実施例4 第4図により説明する。第3図は、InP/I n G
 a A sプレーナ型PINホトダイオードの縦断面
図である。
Example 4 This will be explained with reference to FIG. Figure 3 shows InP/InG
FIG. 2 is a longitudinal cross-sectional view of an a As planar PIN photodiode.

(1+   InP基板(Sドープ)1上にn−−In
PバッファM2.n−−I nGaAs光吸収層3.n
−InGaAs層34.n−1nP窓層35.n−−I
nP窓層36をMOCVD法により連続成長した。各層
の厚さと、不純物濃度は2 ; 0.5 pm、 I 
X 10”am−8,3;2μm。
(n--In on 1+ InP substrate (S-doped) 1
P buffer M2. n--I nGaAs light absorption layer 3. n
-InGaAs layer 34. n-1nP window layer 35. n--I
The nP window layer 36 was continuously grown by MOCVD. The thickness of each layer and the impurity concentration are 2; 0.5 pm, I
X 10”am-8,3; 2 μm.

lXl0”m−’、34 ; 0.4pm、2xlO1
6cts−”、35 ; 0.2μm、2X1016a
n−”、36 ;3 pm、 I X 10”cm−’
である。つぎに、36の上に5iOz/PSG膜をCv
Dで付着し、フォトリングラフィで拡散マスクパターン
を形成した。
lXl0"m-', 34; 0.4pm, 2xlO1
6cts-”, 35; 0.2μm, 2X1016a
n-'', 36; 3 pm, I x 10''cm-'
It is. Next, a 5iOz/PSG film was placed on top of 36.
D, and a diffusion mask pattern was formed by photolithography.

拡散径は100μmφである。次にZnPzを閉管法を
用いて、550℃で熱拡散し、PN接合面を320t 
p型1 n P 7  l p p型InGaAs7−
2を形成した。パッシベーション膜38はSiOx /
PSG/SiNx三層構造膜2反射防止膜39はSiN
xである。p型電極310にはA u / P t /
 T iを、n型電極311にはAu/P d / A
 u G e N iを用いた。
The diffusion diameter is 100 μmφ. Next, ZnPz was thermally diffused at 550°C using a closed tube method, and the PN junction surface was heated to 320t.
p-type 1 n P 7 l p p-type InGaAs7-
2 was formed. The passivation film 38 is made of SiOx/
PSG/SiNx three-layer structure film 2 anti-reflection film 39 is SiN
It is x. The p-type electrode 310 has A u /P t /
Ti and Au/P d/A for the n-type electrode 311.
uGeNi was used.

素子作成後、EB IC法およびスティンエッチ法でP
N接合位置を調べたところ、PNN接合フロン8置置n
−InGaAs層34の上端または内部に再現性良く位
置しており、かつ36と35゜35と34各層間の接合
面に沿った横方向異常拡散は全く認められなかった。
After device fabrication, P is etched using EB IC method and stain etch method.
When I checked the N junction position, I found that PNN junction Freon 8 was placed n
- It was located at the upper end or inside the InGaAs layer 34 with good reproducibility, and no abnormal lateral diffusion was observed along the bonding surfaces between the layers 36 and 35 and 35 and 34.

得られた素子はバイアス電圧なしで、量子効率80%を
示し、接合容量は約2pFと高性能であつた。
The obtained device had a quantum efficiency of 80% without a bias voltage, and had a high performance with a junction capacitance of about 2 pF.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、比較的不純物濃度の高い禁止帯幅の大
きい物質と不純物tA度の低い禁止帯幅の小さい物質が
接した構造になっており、禁止帯幅の大きい領域内に形
成された接合から拡散電位で空乏層は禁止帯幅の小さい
領域に伸びているので、以下の様な効果がある。
According to the present invention, the structure is such that a material with a relatively high impurity concentration and a large bandgap width is in contact with a material with a small bandgap width and a low degree of impurity tA, and the material is formed in a region with a large bandgap width. Since the depletion layer extends from the junction to the region where the forbidden band width is small at the diffusion potential, the following effects are produced.

(1)接合位置を光吸収頭域近くに再現性良く形成でき
る。
(1) The bonding position can be formed near the light-absorbing head region with good reproducibility.

(2)ヘテロ界面の影響による異常な不純物拡散の影響
を軽減できる。
(2) The influence of abnormal impurity diffusion due to the influence of hetero-interfaces can be reduced.

(3) !!バイアス、あるいは低バイアスで高鈍感を
達成できる。
(3)! ! High insensitivity can be achieved with bias or low bias.

(4)接合はE5の大きい領域にあり、ヘテロ界面の影
響がなくなるため、暗電流が小さくなる。
(4) The junction is located in a region where E5 is large, and the influence of the hetero interface is eliminated, so the dark current becomes small.

また、本発明によれば、光吸収層と窓層のへテロ界面の
残留ヒ素ガスによる変性層を取り除くことができるため
、格子欠陥に基づく暗電流の劣化を低く抑えることがで
きる効果がある。
Further, according to the present invention, since the modified layer due to residual arsenic gas at the hetero interface between the light absorbing layer and the window layer can be removed, there is an effect that deterioration of dark current due to lattice defects can be suppressed to a low level.

さらに、本発明によれば、零バイアス電圧で感度を持つ
高性能(低静電容量、低暗電流、高量子効率)なプレー
ナPINホトダイオードを、再現性良く生産できる効果
がある。
Further, according to the present invention, a high-performance (low capacitance, low dark current, high quantum efficiency) planar PIN photodiode that has sensitivity at zero bias voltage can be produced with good reproducibility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は実施例1を示す素子の縦断面図、第2図は実施
例2のInP/InAlAs/InGaAs断面図、第
3図は実施例3のInGa’Asを用いた素子の断面図
、第4図は実施例4に示す素子の断面図、および第5図
は従来の受光素子の断面図である。 1−n+ −I nP基板、2−n−−I nPバッフ
ァ層、3−n−−I nGaAs光吸収層、4’・・・
n−InP薄層、4’ −n−−I nP窓層、5・・
・p−InP拡散層、6・・・パッシベーション層、7
・・・反射防止膜、8・・・p側電極、9・・・n側電
極、10− p n接合、14−n−−I nAffA
sg層、15−n−−I n P窓層、16− p −
I n P層。 p −I n A Q A s M(Z n拡散) 、
1 ’7−3 iOz/PSG/SiNx (2000
人72000人/2000人)、18−8iNx  (
1900人)、19・・・p型オーミック電極A u 
/ P t / T i(1,0μm10.1 μm1
0.1 μm)  、  110”’nn型オーミック
電極Au / P d / A u G e N i(
1,0μm10.t umlo、1 μm)  、  
24 ・・・n−1nGaAs光吸収層、25−n−−
InP窓層、26−p−InP、p−InG、aAs層
(ZnまたはCdの選択熱拡散)、27・・・パッシベ
ーション膜Si○z / P S G / S x N
x、  28・・・反射防止膜(S x N x t 
1900人)、29・・・P型オーミック電極(Au/
Pt/Ti)、210”・n型オーミック電極(A u
 / P d / AuGeN1)、34 =−n −
I n G a A s光吸収層、35− n −In
P窓層、36−n−−I n P窓層、37・ p−I
nP、37−p −I n G a A s、38 ・
・・パッシベーション膜、39・・・反射防止膜、31
0・・・p型電極、311・・・n型電極、320・・
・PN接合面。 ”\
FIG. 1 is a longitudinal cross-sectional view of an element showing Example 1, FIG. 2 is a cross-sectional view of InP/InAlAs/InGaAs of Example 2, and FIG. 3 is a cross-sectional view of an element using InGa'As of Example 3. FIG. 4 is a sectional view of an element shown in Example 4, and FIG. 5 is a sectional view of a conventional light receiving element. 1-n+ -I nP substrate, 2-n--I nP buffer layer, 3-n--I nGaAs light absorption layer, 4'...
n-InP thin layer, 4'-n--I nP window layer, 5...
・p-InP diffusion layer, 6...passivation layer, 7
...Anti-reflection film, 8...p-side electrode, 9...n-side electrode, 10-p-n junction, 14-n--I nAffA
sg layer, 15-n--I n P window layer, 16-p-
I n P layer. p −I n A Q A s M (Z n diffusion),
1 '7-3 iOz/PSG/SiNx (2000
72,000 people/2,000 people), 18-8iNx (
1900 people), 19...p-type ohmic electrode A u
/ P t / T i (1.0 μm10.1 μm1
0.1 μm), 110'''nn type ohmic electrode Au/Pd/AuGeNi(
1.0μm10. tumlo, 1 μm),
24...n-1nGaAs light absorption layer, 25-n--
InP window layer, 26-p-InP, p-InG, aAs layer (selective thermal diffusion of Zn or Cd), 27...passivation film Si○z / P S G / S x N
x, 28...Anti-reflection film (S x N x t
1900 people), 29...P-type ohmic electrode (Au/
Pt/Ti), 210” n-type ohmic electrode (A u
/ P d / AuGeN1), 34 = −n −
InGaAs light absorption layer, 35-n-In
P window layer, 36-n--I n P window layer, 37-p-I
nP, 37-p-I n Ga As, 38 ・
...Passivation film, 39...Antireflection film, 31
0...p-type electrode, 311...n-type electrode, 320...
・PN junction surface. ”\

Claims (1)

【特許請求の範囲】 1、基板上に、受光素子機能を有する主接合を含む半導
体積層構造体を設けてなる半導体受光素子において、一
の導電形を有し、禁止帯幅が大きく、光を吸収する半導
体層(光吸収層)と、禁止帯幅が小さい光を透過する半
導体層(窓層)の間に、不純物濃度が当該光吸収層およ
び当該窓層のそれより大きい中間層を1以上有し、該中
間層を有することを特徴とする半導体受光素子。 2、前記中間層が、前記窓層の前記光吸収層側部分の不
純物濃度を高くした領域、および前記吸収層の前記窓層
側部分の不純物濃度を高くした領域の両者もしくはいず
れかである特許請求の範囲第1項記載の半導体受光素子
。 3、前記窓層および前記光吸収層がInPであつて前記
中間層がInAlAsである特許請求の範囲第1項記載
の半導体受光素子。 4、前記窓層がInPであつて、前記中間層がInAl
Asである特許請求の範囲第1項記載の半導体受光素子
。 5、前記窓層をInP、前記光吸収層をInGaAsと
し、前記中間層が当該光吸収層の不純物濃度の高い領域
であつて、前記接合が当該中間層内にある特許請求の範
囲第1項記載の半導体受光素子。 6、前記主接合が前記中間層内に形成されてなる特許請
求の範囲第1項記載の半導体受光素子。 7、前記中間層の不純物濃度が1×10^1^6〜1×
10^1^7cm^3で、この厚さが0.1〜0.3μ
mである特許請求の範囲第1項記載の半導体受光素子。 8、前記中間層の不純物濃度が1×10^1^6cm^
−^3以上であり、前記窓層および光吸収層の不純物濃
度が10^1^6cm^−^1以下である特許請求の範
囲第1項記載の半導体受光素子。 9、前記中間層の不純物濃度が5×10^1^6〜5×
10^1^6cm^−^3で、厚さが0.5μm以下で
ある特許請求の範囲第1項記載の半導体受光素子。 10、基板上に、受光素子機能を有する主接合を含む半
導体層構造体を形成する諸工程でなる半導体受光素子の
製造方法において、一の導電形を有し、禁止帯幅が大き
く、光を吸収する半導体層(光吸収層)を形成する工程
と、禁止帯幅が小さく、光を透過する半導体層(窓層)
を形成する工程の間に、中間層を形成する工程を有する
ことを特徴とする半導体受光素子の製造方法。 11、前記主接合を中間層内に形成する特許請求の範囲
第10項記載の半導体受光素子の製造方法。 12、前記主接合がZnの熱拡散により形成することを
特徴とする特許請求の範囲第10項記載の半導体受光素
子の製造方法。
[Claims] 1. A semiconductor light-receiving device comprising a semiconductor laminated structure including a main junction having a light-receiving device function on a substrate, which has one conductivity type, has a large forbidden band width, and emits light. Between the semiconductor layer that absorbs (light absorption layer) and the semiconductor layer (window layer) that transmits light with a small forbidden band width, one or more intermediate layers are provided whose impurity concentration is higher than that of the light absorption layer and the window layer. A semiconductor light-receiving element comprising the intermediate layer. 2. A patent in which the intermediate layer is a region of the window layer in which the impurity concentration is increased in the light absorption layer side portion, and/or a region in which the impurity concentration in the window layer side portion of the absorption layer is increased. A semiconductor light-receiving device according to claim 1. 3. The semiconductor light-receiving device according to claim 1, wherein the window layer and the light absorption layer are made of InP, and the intermediate layer is made of InAlAs. 4. The window layer is InP, and the intermediate layer is InAl.
The semiconductor light receiving element according to claim 1, which is made of As. 5. The window layer is InP, the light absorption layer is InGaAs, the intermediate layer is a region of the light absorption layer with a high impurity concentration, and the junction is within the intermediate layer, claim 1. The semiconductor photodetector described above. 6. The semiconductor light-receiving device according to claim 1, wherein the main junction is formed within the intermediate layer. 7. The impurity concentration of the intermediate layer is 1×10^1^6 to 1×
10^1^7cm^3, and this thickness is 0.1 to 0.3μ
The semiconductor light-receiving device according to claim 1, which is m. 8. The impurity concentration of the intermediate layer is 1×10^1^6 cm^
-^3 or more, and the impurity concentration of the window layer and the light absorption layer is 10^1^6 cm^-^1 or less. 9. The impurity concentration of the intermediate layer is 5×10^1^6~5×
The semiconductor light-receiving element according to claim 1, which has a diameter of 10^1^6 cm^-^3 and a thickness of 0.5 μm or less. 10. A method for manufacturing a semiconductor light-receiving device comprising steps of forming a semiconductor layer structure including a main junction having a light-receiving device function on a substrate, which has one conductivity type, has a large forbidden band width, and does not emit light. The process of forming a semiconductor layer that absorbs light (light absorption layer) and the semiconductor layer that has a small forbidden band width and transmits light (window layer)
1. A method for manufacturing a semiconductor light-receiving device, comprising the step of forming an intermediate layer between the steps of forming the semiconductor light-receiving device. 11. The method of manufacturing a semiconductor light receiving element according to claim 10, wherein the main junction is formed in an intermediate layer. 12. The method of manufacturing a semiconductor light receiving element according to claim 10, wherein the main junction is formed by thermal diffusion of Zn.
JP61143000A 1986-06-20 1986-06-20 Semiconductor light receiving element and method of manufacturing the same Expired - Lifetime JP2708409B2 (en)

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