JPH01297868A - Planar type semiconductor photodetector - Google Patents

Planar type semiconductor photodetector

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Publication number
JPH01297868A
JPH01297868A JP63128850A JP12885088A JPH01297868A JP H01297868 A JPH01297868 A JP H01297868A JP 63128850 A JP63128850 A JP 63128850A JP 12885088 A JP12885088 A JP 12885088A JP H01297868 A JPH01297868 A JP H01297868A
Authority
JP
Japan
Prior art keywords
layer
type
quantum well
junction
light absorbing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63128850A
Other languages
Japanese (ja)
Inventor
Isao Watanabe
功 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63128850A priority Critical patent/JPH01297868A/en
Publication of JPH01297868A publication Critical patent/JPH01297868A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a semiconductor photodetector having high speed response characteristics without degrading the reliability by providing a required p-n junction to a part of a quantum well adjacent to a light absorbing layer. CONSTITUTION:A quantum well layer 4 and a layer 5 in which the quantum well layer is disordered are provided. The thickness of the quantum well layer is so selected as to provide an absorbing end nearly the same as a light absorbing layer 3 in which a quantum level is almost neglected. The barrier layers are so composed as to have thicknesses within a range in which band discontinuity is relieved by a tunnel effect and to have the band gap after disordering larger than the band gap of the light absorbing layer 3 to avoid the light absorption by this layer. Whereever in the layers 4 and 5 a p-n junction is formed, the p-n junction is formed in the hetero boundary between the light absorbing layer 3 and a window cap layer 6 having a larger gap than the layer 3 in a self-alignment manner, so that the deterioration of responsiveness caused by diffused carrier components can be avoided.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、p−n接合の位置制御に高い制御精度を必要
としない高速pinフォトダイオードに関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-speed pin photodiode that does not require high control accuracy for controlling the position of a pn junction.

(従来の技術) 高速大容量光通信システムや加入者系光通信システムを
可能にするには、Gb/sオーダーの高速応答特性を有
し、かつ、製作プロセスの簡便な半導体受光素子が必要
である。このため、近年シリカ系ファイバの低損失波長
域1.0〜1.6pmに適応できるInGaAs/In
P系pin型フォトダイオードの高速化、製作プロセス
の簡易化に対する研究が活発となっている。プレーナ型
へテロ接合ルミn型フォトダイオードの高速応答化のた
めにはp−n接合形成の際、接合位置の高精度制御が重
要となる。この理由を従未例を示す第2図を用いて説明
する。この構造は、石原等がエレクトロニクス・レター
(El、6ctron。
(Prior art) In order to enable high-speed, large-capacity optical communication systems and subscriber-based optical communication systems, semiconductor light-receiving elements that have high-speed response characteristics on the order of Gb/s and are easy to manufacture are required. be. For this reason, in recent years, InGaAs/In, which can be applied to the low-loss wavelength range of 1.0 to 1.6 pm for silica-based fibers, has been developed.
Research into increasing the speed of P-type pin-type photodiodes and simplifying the manufacturing process is active. In order to achieve high-speed response of a planar heterojunction luminum n-type photodiode, highly accurate control of the junction position is important when forming a pn junction. The reason for this will be explained using FIG. 2, which shows a conventional example. This structure was proposed by Ishihara et al. in Electronics Letters (El, 6ctron).

Lett、)20巻、No、16、p654−656、
Aug、 (1984年)で発表したものであり、1は
n生型InP基板、2はn型InPバッファ層、3はn
−型InGaAs光吸収層、4はn−型InPウィンド
ウ・キャップ層、5はp生型Zn拡散領域、6は絶縁層
、7はp側電極、8はn側電極である。
Lett,) Volume 20, No. 16, p654-656,
August, (1984), where 1 is an n-type InP substrate, 2 is an n-type InP buffer layer, and 3 is an n-type InP substrate.
4 is an n-type InP window cap layer, 5 is a p-type Zn diffusion region, 6 is an insulating layer, 7 is a p-side electrode, and 8 is an n-side electrode.

高速応答特性を有するpin型フォトダイオードでは、
通常p十型領域はZnの熱拡散等により、ウィンドウ・
キャップ層4(光吸収層よりワイドギャップ)と光吸収
層3のへテロ界面と、その界面から光吸収層中へ深さd
程入った領域に形成されなければならない。その深さd
は、高速応答特性のpinフォトダイオードの光吸収層
厚が1〜2pmであることがら経験的にその10%であ
る0、2pm程以下でなければならない。なぜならば、
p生型領域が光吸収層領域に入り込み過ぎるとその領域
は空乏化せずバイアス電界はこの領域に印加されないた
めにフォトキャリアは拡散によってその領域を走行しな
ければならず、この走行時間により応答が劣化するから
であり、一方、p生型領域がウィンドウ、キャップ層途
中までしか形成されていない場合も、価電子帯不連続に
よるペテロ障壁(ΔEv)によってフォトキャリア(正
孔)の移動が阻止されて応答が劣化するからである。
A pin-type photodiode with high-speed response characteristics has
Normally, the p-type region has a window due to thermal diffusion of Zn, etc.
The hetero interface between the cap layer 4 (wider gap than the light absorption layer) and the light absorption layer 3, and the depth d from that interface into the light absorption layer.
It must be formed in a moderate area. its depth d
Since the light absorption layer thickness of a pin photodiode with high-speed response characteristics is 1 to 2 pm, empirically, the thickness must be less than 0.2 pm, which is 10% of the thickness. because,
If the p-type region penetrates into the light absorption layer region too much, that region will not be depleted and a bias electric field will not be applied to this region, so photocarriers must travel in that region by diffusion, and the response time depends on this travel time. On the other hand, even if the p-type region is formed only halfway through the window or cap layer, the movement of photocarriers (holes) is blocked by the Peter barrier (ΔEv) due to valence band discontinuity. This is because the response is degraded.

(発明が解決しようとする課題) 以上の理由で高速応答特性を有するpin型フォトダイ
オードを形成するには深さ精度〜0.1pmの高精度な
熱拡散技術が要求される。しかし、現在の熱拡散技術で
は0.1pmの精度を再現性良く得ることは難しく、素
子製作上の歩留りを低下させる原因となっていた。
(Problems to be Solved by the Invention) For the above reasons, a highly accurate thermal diffusion technique with a depth accuracy of 0.1 pm is required to form a pin-type photodiode with high-speed response characteristics. However, with the current thermal diffusion technology, it is difficult to obtain an accuracy of 0.1 pm with good reproducibility, which causes a decrease in the yield of device manufacturing.

本発明は、上述の欠点を解決し、信頼性を損ねることな
く、p−n接合の高い位置制御精度を必要とせずに、高
速応答特性を有する半導体受光素子を実現することを目
的とする。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and realize a semiconductor light-receiving element having high-speed response characteristics without impairing reliability and without requiring high position control accuracy of a pn junction.

(課題を解決するための手段) 本発明は、光吸収層に隣接する量子井戸層の一部が無秩
序化された層と無秩序化されない層、あるいは、量子井
戸層の全部が無秩序化された層と前記光吸収層によって
形成されるp−n接合を有することを特徴とするプレー
ナ型半導体受光素子である。
(Means for Solving the Problems) The present invention provides a layer in which a part of the quantum well layer adjacent to a light absorption layer is disordered, a layer in which the quantum well layer is not disordered, or a layer in which the entire quantum well layer is disordered. and a pn junction formed by the light absorption layer.

(作用) 本発明は、上述の構成により従来の欠点を克服した。第
1図は、本半導体受光素子の一例を示す構造断面図であ
る。図において、1はn+型半導体基板、2はn型バッ
ファ層、3はn−型光吸収層、4はn−型量子井戸層、
5は拡散もしくはイオン注入によって量子井戸が無秩序
化された層、6は拡散もしくはイオン注入によるp生型
ウィンドウ・キャップ層、7はn−型キャップ層、8.
9は各々p側、n側電極、10は絶縁層である。6.7
部はp生型化を行う前の時点で光吸収層よりワイドギャ
ップのバルク層でも量子井戸層4でもどちらでもよい。
(Operation) The present invention overcomes the conventional drawbacks by the above-described configuration. FIG. 1 is a structural sectional view showing an example of the present semiconductor light-receiving device. In the figure, 1 is an n + type semiconductor substrate, 2 is an n type buffer layer, 3 is an n - type light absorption layer, 4 is an n - type quantum well layer,
5 is a layer in which quantum wells are disordered by diffusion or ion implantation; 6 is a p-type window cap layer formed by diffusion or ion implantation; 7 is an n-type cap layer; 8.
9 is a p-side electrode and an n-side electrode, and 10 is an insulating layer. 6.7
The portion may be either a bulk layer with a wider gap than the light absorption layer or a quantum well layer 4 before conversion to p-type.

本発明の特徴を第3図に示す本構造のバンド図を用いて
説明する。図中の各部は第1図の同一数字で示される箇
所に対応する。本発明の特徴である量子井戸層4と、量
子井戸層を無秩序化した層5に関しては、以下の通りで
ある。即ち、井戸層厚は量子準位が無視し得る程度、即
ち、光吸収層3とほぼ同じ吸収端(バンドギャップE、
1)となる厚さであり、障壁層はバンド不連続Δ町、Δ
Eoがトンネル効果によって緩和される範囲で、しかも
無秩序化後のバンドギャップE82(井戸層と障壁層の
平均値)が光吸収層のバンドギャップE3、より大きく
、この層で光が吸収されないような組成・厚さである。
The features of the present invention will be explained using the band diagram of the present structure shown in FIG. Each part in the figure corresponds to the part indicated by the same numeral in FIG. The quantum well layer 4 and the layer 5 which is a disordered quantum well layer, which is a feature of the present invention, are as follows. That is, the well layer thickness is such that the quantum level can be ignored, that is, the absorption edge (band gap E,
1), and the barrier layer has band discontinuity Δmachi, Δ
Within the range where Eo is relaxed by the tunneling effect, the bandgap E82 (average value of the well layer and barrier layer) after disordering is larger than the bandgap E3 of the light absorption layer, and no light is absorbed in this layer. composition and thickness.

以上の構造によると、量子井戸層中のどの位置にp−n
接合が形成されていても、そのp−n鏡台は、自己整合
的に光吸収層とそれよりワイドギャップのウィンドウキ
ャップ層とのへテロ界面に形成されることになり、拡散
キャリア成分による応答劣化を受けることがない。また
、無秩序化されずに残った量子井戸によるバンド不連続
のキャリア走行への影響も、障壁層が上記条件を満たす
ことにより無視し得る。以上の結果、高速応答特性を有
するプレーナルミn型フォトダイオードを製作するとき
の拡散もしくはイオン注入の精度が緩くなり容易に製作
することができる。
According to the above structure, at which position in the quantum well layer is p-n
Even if a junction is formed, the p-n mirror table will be formed in a self-aligned manner at the hetero interface between the light absorption layer and the window cap layer with a wider gap, resulting in response degradation due to diffused carrier components. I never receive it. In addition, the influence of band discontinuity on carrier transport due to quantum wells that remain undisordered can be ignored because the barrier layer satisfies the above conditions. As a result of the above, the precision of diffusion or ion implantation when manufacturing a planar aluminum n-type photodiode having high-speed response characteristics is relaxed, and manufacturing can be facilitated.

(実施例) 以下、本発明の実例として、InGaAs/InP系p
in型フォトダイオードを用いて説明するが、他の半導
体系、例えば、InGaAs/InAlAs系、AlG
aAs/GaAs系等についても同じである。第1図に
示す半導体受光素子を以下の工程によって製作した。
(Example) Hereinafter, as an example of the present invention, InGaAs/InP-based p
Although the explanation will be made using an in-type photodiode, other semiconductor types such as InGaAs/InAlAs type, AlG
The same applies to aAs/GaAs systems and the like. The semiconductor light-receiving device shown in FIG. 1 was manufactured by the following steps.

(実施例1) n十型InP基板1上に、n型InPバッファ層2をl
pm厚に、キャリア濃度〜2×1015cm−3のn−
型In。、5aGa04゜AS光吸収層3を1〜1.5
11m厚に、厚さ200Aのn−型InP層(キャリア
濃度〜1×1016cm−3)と厚さ100〜200人
のn−型In。53Ga0.4゜As層(キャリア濃度
〜2 X 1015cm−3)からなる量子井戸層4を
0.3〜0.5pm厚に、キャリア濃度〜1×1016
cm−3のn−型InPウィンドウキャップ層7を11
1m厚に順次ハイドライド気相成長法を用いて成長する
。次にSiO2拡散マスクを用いて直径20pmの円形
領域に通常の方法でZn拡散を深さ1〜1.3pmまで
行う。これにより量子井戸層の一部または全部を無秩序
化した層5とp生型ウィンドウキャップ層6を形成する
(Example 1) An n-type InP buffer layer 2 is formed on an n-type InP substrate 1.
pm thickness, carrier concentration ~2 x 1015 cm-3 n-
Type In. , 5aGa04°AS light absorption layer 3 from 1 to 1.5
11 m thick with a 200 A thick n-type InP layer (carrier concentration ~1 x 1016 cm-3) and a 100-200 nm thick n-type InP layer. The quantum well layer 4 made of 53Ga0.4°As layer (carrier concentration ~2 x 1015 cm-3) has a thickness of 0.3 to 0.5 pm, and the carrier concentration is ~1 x 1016.
cm-3 n-type InP window cap layer 7 to 11
It is grown sequentially to a thickness of 1 m using the hydride vapor phase epitaxy method. Next, using a SiO2 diffusion mask, Zn is diffused to a depth of 1 to 1.3 pm in a circular area with a diameter of 20 pm in a conventional manner. As a result, a layer 5 in which part or all of the quantum well layer is disordered and a p-type window cap layer 6 are formed.

基板研磨後に絶縁層10を形成し、さらにp側電極8を
AuZnで、n側電極9をAuGeで形成した。
After polishing the substrate, an insulating layer 10 was formed, and furthermore, the p-side electrode 8 was formed of AuZn, and the n-side electrode 9 was formed of AuGe.

(実施例2) 1型InP基板1上に、n型InPバッファ層2を11
1m厚に、ギヤリア濃度〜2×1015cm−3のn−
型■nO,53GaO,47””光吸収層3を1−1.
5pm厚に、厚さ200人のn−型InP層(キャリア
濃度〜1×1016cm−3)と厚さ100〜200人
のn−型■no53Gao4゜As層(キャリア濃度〜
2 X 1015cm ’)からなる量子井戸層4を0
.3−0.5pm厚に、キャリア濃度〜1×1016c
m−3のn−型InPウィンドウキャップ層7を0.7
pm厚に順次ハイドライド気相成長法を用いて成長する
。次に厚さ0.6pmの8102膜と厚さ2pmのフォ
トレジスト膜からなるイオン注入用マスクを用いて直径
20pmの円形領域に通常の方法でBe注入を深さ〜1
.Opmまで行う。これにより量子井戸層の一部または
全部を無秩序化した層5とp生型ウィンドウキャップ層
6を形成する。基板研磨後に絶縁層10を形成し、さら
にp側電極8をAuZnで、n側電極9をAuGeで形
成した。
(Example 2) On a 1-type InP substrate 1, an n-type InP buffer layer 2 is formed by 11 layers.
1 m thick, gearia concentration ~2 x 1015 cm-3 n-
1-1.
5 pm thick, a 200-layer n-type InP layer (carrier concentration ~1 x 1016 cm-3) and a 100-200 layer-thick n-type ■no53Gao4°As layer (carrier concentration ~1x1016 cm-3).
The quantum well layer 4 consisting of 2 x 1015 cm') is
.. 3-0.5pm thickness, carrier concentration ~1x1016c
m-3 n-type InP window cap layer 7 of 0.7
The film is grown sequentially to a thickness of 100 pm using the hydride vapor phase epitaxy method. Next, using an ion implantation mask consisting of an 8102 film with a thickness of 0.6 pm and a photoresist film with a thickness of 2 pm, Be was implanted into a circular region with a diameter of 20 pm to a depth of ~1 pm using the usual method.
.. Perform up to Opm. As a result, a layer 5 in which part or all of the quantum well layer is disordered and a p-type window cap layer 6 are formed. After polishing the substrate, an insulating layer 10 was formed, and furthermore, the p-side electrode 8 was formed of AuZn, and the n-side electrode 9 was formed of AuGe.

(発明の効果) これらの実施例1.2においてともに、順方向立ち上が
りが電圧0.7■と均一で、かつ、無バイアス時で光応
答を示す、即ち、InGaAs光吸収層が空乏化してい
ると同時にカットオフ周波数も10GHz以上の素子が
再現性良く得られた。また、従来のプレーナ構造と同じ
< p−n接合界面がメサ・エツチング等で露出するこ
とがないため暗電流の増加も観測されないなど、信頼性
に関しても従来のプレーナ構造素子と同等であった。以
上、本発明の構造により、信頼性を損ねることなく p
−n接合位置制御に高い制御精度を必要としない高速応
答特性を有する光検出器を得ることができ、その価値は
太きい。
(Effects of the Invention) In both Examples 1 and 2, the forward rise is uniform with a voltage of 0.7 cm, and a photoresponse is exhibited in the absence of bias, that is, the InGaAs light absorption layer is depleted. At the same time, a device with a cutoff frequency of 10 GHz or higher was obtained with good reproducibility. Furthermore, since the p-n junction interface, which is the same as the conventional planar structure, is not exposed due to mesa etching, no increase in dark current was observed, and the reliability was equivalent to that of the conventional planar structure element. As described above, with the structure of the present invention, p
-n It is possible to obtain a photodetector having high-speed response characteristics that does not require high control accuracy for junction position control, and its value is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体受光素子の一例を示す構造断面
図である。図において、1はn生型半導体基板、2はn
型バッファ層、3はn−型光吸収層、4はn−型量子井
戸層、5は拡散もしくはイオン注入によって量子井戸が
無秩序化された層、6は拡散もしくはイオン注入による
p生型ウィンドウギヤップ層、7はn−型ギャップ層、
8.9は各々p側、n側電極、10は絶縁層である。第
2図は従来のプレーナ型pin型フォトダイオードの構
造断面図である。この図において、1はn十型InP基
板、2はn型InPバッファ層、3はn−型InGaA
s光吸収層3.4はn−型InPウィンドウ・キャップ
層、5はp生型Zn拡散領域、6は絶縁層、7はp側電
極、8はn側電極である。第3図は、本発明の半導体受
光素子のバンド図である。図において、1はn+型半導
体基板、2はn型バッファ層、3はn−型光吸収層、4
はn−型量子井戸層、5は拡散もしくはイオン注入によ
って量子井戸が無秩序化された層、6は拡散もしくはイ
オン注入によるp生型ウィンドウギヤップ層である。
FIG. 1 is a structural sectional view showing an example of the semiconductor light receiving element of the present invention. In the figure, 1 is an n-type semiconductor substrate, 2 is an n-type semiconductor substrate, and 2 is an n-type semiconductor substrate.
3 is an n-type light absorption layer, 4 is an n-type quantum well layer, 5 is a layer in which the quantum well is disordered by diffusion or ion implantation, and 6 is a p-type window gap by diffusion or ion implantation. layer 7 is an n-type gap layer;
8.9 are p-side and n-side electrodes, and 10 is an insulating layer. FIG. 2 is a structural cross-sectional view of a conventional planar pin type photodiode. In this figure, 1 is an n-type InP substrate, 2 is an n-type InP buffer layer, and 3 is an n-type InGaA substrate.
The s-light absorbing layer 3.4 is an n-type InP window cap layer, 5 is a p-type Zn diffusion region, 6 is an insulating layer, 7 is a p-side electrode, and 8 is an n-side electrode. FIG. 3 is a band diagram of the semiconductor light receiving element of the present invention. In the figure, 1 is an n+ type semiconductor substrate, 2 is an n type buffer layer, 3 is an n- type light absorption layer, and 4
is an n-type quantum well layer, 5 is a layer in which the quantum well is disordered by diffusion or ion implantation, and 6 is a p-type window gap layer by diffusion or ion implantation.

Claims (1)

【特許請求の範囲】[Claims]  光吸収層に隣接する量子井戸層の一部が無秩序化され
た層と無秩序化されない層、あるいは、量子井戸層の全
部が無秩序化された層と前記光吸収層によって形成され
るp−n接合を有することを特徴とするプレーナ型半導
体受光素子。
A p-n junction formed by a partially disordered quantum well layer adjacent to a light absorption layer and a non-disordered layer, or a partially disordered quantum well layer and the light absorption layer. A planar semiconductor light-receiving element characterized by having:
JP63128850A 1988-05-25 1988-05-25 Planar type semiconductor photodetector Pending JPH01297868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63128850A JPH01297868A (en) 1988-05-25 1988-05-25 Planar type semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63128850A JPH01297868A (en) 1988-05-25 1988-05-25 Planar type semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPH01297868A true JPH01297868A (en) 1989-11-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281542A (en) * 1992-03-31 1994-01-25 At&T Bell Laboratories Planar quantum well photodetector
CN112152081A (en) * 2020-11-26 2020-12-29 武汉敏芯半导体股份有限公司 Hybrid integrated resonant cavity laser and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281542A (en) * 1992-03-31 1994-01-25 At&T Bell Laboratories Planar quantum well photodetector
CN112152081A (en) * 2020-11-26 2020-12-29 武汉敏芯半导体股份有限公司 Hybrid integrated resonant cavity laser and preparation method thereof

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