JPH0350966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a two-wire displacement measuring device that measures mechanical displacement by converting it into a change in capacitance.

[Prior art and its problems]

Generally, when detecting capacitance, there is a drawback that errors occur in the detection results due to the influence of the dielectric constant between the electrodes. Therefore, a capacitance detection method that is free from such influences has already been proposed.

FIG. 1 is a principle diagram for explaining the principle of such a detection method. In this Figure 1, 2
A movable electrode _Ev is arranged between the two fixed electrodes _Ef , and the movable electrode _Ev moves in the left-right direction in response to mechanical displacement. In this case, if one of the capacitances C _A and C _B between the electrodes increases, the other decreases. In other words, it changes differentially. Here, the area of each electrode is A, the dielectric constant between the electrodes is ε, and the distance between the movable electrode E _v and the fixed electrode E _f is d. For example, as shown by the dotted line, the movable electrode
When E _v changes by Δd, the capacitances C _A and C _B can be calculated using the following equations.

C _A = εA/(d-Δd) C _B = εA/(d+Δd) (1) Now, consider the sum and difference of these capacitances.

Therefore, take the ratio.

C _A −C _B /C _A +C _B = Δd/d (3) Therefore, the displacement Δd is the sum of the capacitances C _A and C _B (C _A +
C _B ) and the difference (C _A −C _B ). Therefore, as is clear from equation (3), the amount of displacement Δd is a function only of capacitance, so
It is not affected by the dielectric constant between the electrodes, and therefore it is possible to accurately detect the amount of mechanical displacement using capacitance.

By the way, conventional methods for detecting capacitor capacitance include applying high-frequency alternating current to the capacitor being measured, and using the fact that the current flowing through the capacitor at that time is proportional to the frequency, power supply voltage, and capacitance to measure the capacitance. A method has been used in which the detected current is amplified and calculated using a differential amplifier or the like and converted into a two-wire current signal.

However, such a method requires an oscillation circuit and a transformer winding in order to apply high-frequency alternating current to the capacitor, and also requires a rectifier circuit and a smoothing circuit to rectify and smooth the current flowing to the capacitor. The problem was that it was necessary.
That is, since the current flowing through the capacitor is proportional to the frequency and the power supply voltage as described above, a measurement error occurs when the power supply frequency fluctuates.

Furthermore, capacitors C _A and C _B generally have floating amounts connected in parallel, respectively.
The influence of these stray capacitances cannot be ignored either.

[Purpose of the invention]

The present invention has been made in view of these points, and an object of the present invention is to provide a displacement measuring device that can eliminate the above-mentioned drawbacks, particularly the influence of stray capacitance.

[Key points of the invention]

The present invention provides two measuring capacitors whose capacitance values differentially change according to mechanical displacement, a circuit for charging and discharging these two measuring capacitors, and a charging pressure of the two measuring capacitors that is maintained at a predetermined value. A bistable means is driven by the detection means to perform bistable operation, and the bistable means is charged during one output state of the bistable means and is charged during the other output state. a first capacitor that is discharged; a second capacitor that is charged during the other output state of the bistable means and discharged during the one output state; and charging of the first and second capacitors. a differential amplifier that is supplied with voltage and outputs a voltage that is proportional to the difference between the charged voltages of the first and second capacitors; and current control means that is controlled by the differential amplifier and supplies an output current that represents the mechanical displacement. and the first
and delay means for delaying the start of discharge of each of the second capacitors by a predetermined time, and by appropriately setting the delay time of the delay means, the influence of stray capacitance on the measurement capacitor is compensated. It is.

According to an advantageous embodiment of the displacement measuring device according to the invention, the detection means consist of a flip-flop of the C-MOS type and switch means which alternately direct the charged voltages of the two measuring capacitors to the flip-flop.

According to another advantageous embodiment of the displacement measuring device according to the invention, the bistable means allow the first capacitor to be charged during one of its output states and the second capacitor during the other output state. It is equipped with a switch means that enables the capacitor to be charged.

According to yet another advantageous embodiment of the displacement measuring device according to the present invention, the delay means is incorporated in a C-MOS type D flip-flop and a discharge circuit of the first and second capacitors, and and switch means for on/off control.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention. In this FIG. 2, E is an external power supply connected to the load L, and power is supplied from this external power supply E via a transmission line. Diode D is connected to external power supply E.
A field effect transistor (FET) T ₅ , resistors R ₁₄ , R ₁₅ and a Zener diode ZD are connected in series through the field effect transistor T ₅ so that a constant current flows through the Zener diode ZD. . A transistor T ₃ is connected to the connection point between the resistors R ₁₄ and R ₁₅ , and a drive current is supplied to each component described below through this transistor T ₃ .

C _A and C _B are a pair of measurement capacitors that vary differentially depending on the amount of mechanical displacement, one end of which is connected to the transmission line l ₁ through resistors R ₁ and R ₂ , and the other end connected to a common The transmission line is connected to _L2 . capacitor
C _A and C _B have stray capacitances C _SA and C _SB connected in parallel, respectively. Each capacitor C _A , C _B
A C-MOS switch _CM1 is connected to one end of the switch CM1, and a D-flip-flop _Q1 is connected to the output side of the switch _CM1 . This D-flip-flop _Q1 consists of a C-MOS type flip-flop, and is set when the charging voltage of capacitors C _A and C _B exceeds a predetermined voltage level (threshold level), and is set at a predetermined time constant. (time constant determined by resistor R _f and capacitor C _f ). Note that when using a conventional general D-flip-flop, a special circuit (for example, a Schmitt circuit) is required to determine the threshold level at the front stage, but when using a C-MOS type flip-flop, When used, such a circuit is not required and the switching voltage can be used as it is as a threshold voltage. Thus, the Q output V ₂ of the flip-flop Q ₁ is led to the clock pulse input CP of the flip-flop Q ₂ , and is also connected to the transistors T 1 and _CP via resistors R ₃ and R ₄ .
Used to drive _T2 . Note that the transistors T ₁ and T ₂ are transistors for discharging the capacitors C _A and C _B. flip flop
Q ₂ similarly consists of a D-flip-flop, but
Bistable operation is performed by the output signal _V2 of flip-flop _Q1 . The output signal _V3 of flip-flop _Q2 is led to C-MOS switch _CM2 .

C-MOS switch CM ₁ and C-MOS switch CM ₂ actually consist of one C-MOS switch CM in this embodiment, as shown in _{FIG .} Therefore, switching is controlled. That is, in this example,
When the output signal V ₃ of the flip-flop Q ₂ is an “H” signal, the contacts A ₁ , A ₂ , and B ₃ are made conductive, while when the output signal V ₃ is an “L” signal, the contacts B ₁ , B ₂ , and A ₃ are switched to conduction. Contacts A ₁ and A ₃ are connected to transmission line l ₁ (potential V _C ) via resistor R ₆ , and contact A ₂ is connected to capacitor C _A. Contacts B ₁ and B ₃ are connected to a transmission line l ₂ (ground potential) via a C-MOS switch CM ₃ and a resistor R, which will be described later, and contact B ₂ is connected to a capacitor C _B. And contact A ₁
is connected to buffer amplifier DA ₁ and capacitor C ₁ , contact A ₃ is connected to buffer amplifier DA ₂ and capacitor C ₂ , and contacts A ₂ , B ₂ or C-
MOS switch _CM1 is connected to the clock pulse input CP of flip-flop _Q1 .

The outputs of buffer amplifiers DA ₁ and DA ₂ are connected to their own inverting input terminals, and are connected to resistors R ₇ and R ₈
and its output is connected to _{the non-inverting input terminal of the differential amplifier DA 4 via} a span adjustment resistor VR ₁ . A zero point adjustment resistor is connected to the non-inverting input terminal of this differential amplifier DA ₄ .
VR ₂ and resistor R ₁₂ are connected. and,
The output of the differential amplifier DA ₄ is connected to the output transistor T ₄ via a resistor R ₁₃ to control the current flowing through the transistor T ₄ . Note that _R9 is the feedback resistance. Furthermore, the divided voltage V _C1 of the resistors R ₉ and R ₁₀ is applied to the non-inverting input terminal of the differential amplifier DA ₃ and the inverting input terminal of the differential amplifier DA ₄ , respectively.
is supplied.

Further, the output voltage _V2 of the flip-flop _Q1 is also applied to a C-MOS type D-flip-flop _Q3 . This flip-flop Q ₃ 's Q
The output is given to variable resistor VR ₃ and capacitor C ₃ , while the output voltage V ₇ of its output is C-MOS
Type of switch given to CM ₃ . This D-
Flip-flop Q ₃ is set by the output voltage V ₂ of flip-flop Q ₁ and reset after a certain time T _S determined by a predetermined time constant (time constant determined by resistor VR ₃ and capacitor C ₃ ). It is configured as follows. Switch CM ₃ indicates that the output voltage V ₇ of flip-flop Q ₃ is “H”.
It is conductive when it is in the "L" state, and is cut off when it is in the "L" state.

Next, regarding the operation of the embodiment shown in FIG.
This will be explained with reference to the waveform diagram shown in FIG.

In an embodiment according to the invention, the capacitor
It is divided into a measurement mode for C _A and a measurement mode for capacitor C _B. Therefore, first, capacitor C _A
We will explain the measurement mode for capacitors and then
The measurement mode of C _B will be explained.

Capacitor C _A measurement mode Now, the output signal V ₂ of flip-flop Q ₁ makes transistors T ₁ and T ₂ conductive, and the capacitor
Suppose that C _A and C _B are discharged. flip flop
The output signal V ₂ of Q ₁ is given to the flip-flop Q ₂ , and the Q output of this flip-flop Q ₂ is set to “H”.
transfer to a state. As a result, the output signal _V3 becomes an "H" signal, and the C-MOS switches _CM1 , _CM2
The contacts A ₁ , A ₂ , and B ₃ are made conductive. Thereby, the capacitor C ₁ is charged by the potential V _C via the resistor R ₆ (see V ₄ in FIG. 4 for the charging characteristics of the potential V ₄ of the capacitor C ₁ ). on the other hand,
The output signal V ₂ of the flip-flop Q ₁ is also applied to the capacitor C _f via the resistor R _f , which
Charge C _f . When the charging voltage of capacitor C _f reaches a predetermined value, flip-flop Q ₁ is cleared,
As a result, from the flip-flop Q ₁ , as shown in Fig. 4, V ₂
An output pulse with a constant width T _C is obtained. Thereafter, due to the disappearance of the output signal _V2 of the flip-flop _Q1 , the transistors _T1 and _T2 are cut off. As a result, capacitors C _A and C _B begin to be charged by potential V _C via resistors R ₁ and R ₂ . At this time, C-
Since the contact _A2 of the MOS switch _CM1 is conductive, the charging voltage of the capacitor _CA is guided to the flip-flop _Q1 . When the charging voltage of the capacitor C _A , that is, the output signal V ₁ of the C-MOS switch CM ₁ exceeds the threshold voltage V _T of the flip-flop Q ₁ after a time T _A , the flip-flop Q 1 is set and the output signal V ₁ of the C-MOS switch CM 1 is set. An output signal V ₂ is obtained. This output signal V ₂ is a flip-flop Q ₂
is applied to invert the flip-flop _Q2 , bringing its output signal _V3 to the "L" signal state. As a result, the contacts B ₁ , B ₂ , and A ₃ of the C-MOS switches CM ₁ and CM ₂ are controlled to conduct. In this way, the C _A measurement mode ends.

Here, if the voltage when the charging voltage of the capacitor C _A becomes equal to the threshold voltage V _T of the flip-flop Q ₁ is V _A , it is expressed by the following equation.

Therefore, the charging time T _A of the capacitor C _A (Fig. 4
(see V ₁ ) is expressed by the following equation.

T _A =-R ₁ (C _A +C _SA )log (1-V _T /V _C ) (5) In addition, the above time T _C is similarly expressed by the following equation.

T _C = -R _f C _f log (1 - V _T /V _C ) (6) Since the values of R _f and C _f are known, this T _C
is a constant value.

Therefore, the output signal V ₃ of flip-flop Q ₂ is
The ON period (H signal state period) is ( _TA + T _C ) (see Figure 4).

Capacitor C _B measurement mode In the capacitor C _A measurement mode described above, the setting of flip-flop Q ₁ generates an output signal V ₂ , which controls the C-MOS switch CM via flip-flop Q ₂ , and its contact
It has been stated that B ₁ , B ₂ , and A ₃ are controlled to be conductive. As a result, capacitor C ₂ is charged via resistor R ₆ . On the other hand, the output signal V ₂ of the flip-flop Q ₁ makes the transistors T ₁ and T ₂ conductive, and the capacitors C _A and C _B are discharged. Further, as described above, capacitor C _f is charged via resistor R _f by this output signal V ₂ . When the charging voltage of this capacitor C _f reaches a predetermined value, the flip-flop
Q ₁ is cleared, resulting in flip-flop
From _Q1 , an output pulse with a constant width _Tc as shown in FIG. 4, _V2, is obtained. Thereafter, due to the disappearance of the output signal _V2 of the flip-flop _Q1 , the transistors _T1 and _T2 are cut off. As a result, capacitors C _A and C _B begin to be charged by potential V _C via resistors R ₁ and R ₂ .
At this time, since the contact _B2 of the C-MOS switch _CM1 is conductive, the charging voltage of the capacitor C _B is guided to the flip-flop _Q1 . When the charging voltage of the capacitor C _B , that is, the output signal V ₁ of the C-MOS switch CM ₁ exceeds the threshold voltage V _T of the flip-flop Q ₁ after a time T _B , the flip-flop Q 1 is set and the output signal V ₁ of the C-MOS switch CM 1 is set. An output signal V ₂ is obtained. This output signal V ₂ is applied to flip-flop Q ₂ to
_Q2 is inverted and its output signal _V3 is brought to the "H" signal state. As a result, the C-MOS switch
Switching control is performed so that contacts A ₁ , A ₂ , and B ₃ of CM (CM ₁ , CM ₂ ) are conductive. In this way, the C _B measurement mode ends.

Here, if the voltage at which the charging voltage of the capacitor C _B becomes equal to the threshold voltage V _T of the flip-flop Q ₁ is V _B , it is expressed by the following equation.

Therefore, the charging time T _B to capacitor C _B (Fig. 4
(see V ₁ ) is expressed by the following equation.

T _B =-R ₂ ( _CB + C _SB ) log (1-V _T /V _C ) (8) Note that the above time T _C is expressed in the same way as in equation (6).

Therefore, the output signal V ₃ of flip-flop Q ₂ is
The OFF period (“L” signal state period) is (T _A + T _C )
(See Figure 4).

Next, let's focus on capacitors C ₁ and C ₂ . Capacitor C ₁ is charged during the “H” state of flip-flop Q ₂ output signal V ₃ , while capacitor C ₂
It was mentioned in the explanation of the C _A and C B measurement modes that the C A and C _B measurement modes are charged during the "L" state period of the output signal _V3 . The capacitor _C1 is discharged during the "L" state of its output voltage _V3 , and the capacitor _C2 is discharged during the "H" state of the output voltage _V3 . Discharging of these capacitors C ₁ and C ₂ takes place via switch CM ₃ and resistor R ₆ .
Switch CM ₃ is controlled by flip-flop Q ₃ . This flip-flop _Q3 is set by the output signal _V2 of flip-flop _Q1 ,
It is reset after a certain time T _S according to the time constant determined by variable resistor VR ₃ and capacitor C ₃ . Therefore, the output voltage _V7 at the output of flip-flop _Q3 is as shown in FIG. In other words,
At the start of each measurement mode of C _A and C _B , the signal becomes "L" for a certain period of time T _S . Switch _CM3 is cut off during the "H" state of output voltage _V7 . Therefore,
Switch CM ₃ similarly controls the output voltage of flip-flop Q ₂ at the start of each measurement mode of C _A and C _B.
When _V3 is switched between the "H" state and the "L" state, it is cut off for a certain period of time _T.sub.S.
Therefore, even if the output voltage V ₃ of the flip-flop Q ₂ becomes "H" and the contact B ₃ of the switch CM ₂ becomes conductive, the discharge circuit of the capacitor C ₂ remains active for a certain period of time T _S
Similarly, even if the output voltage V ₃ becomes "L" and the contact B ₁ of the switch CM ₂ becomes conductive, the discharge circuit of the capacitor C ₁ will not be formed until a certain period of time T _S has passed. not formed until That is, the discharge start point of the capacitors C ₁ and C ₂ is delayed for the predetermined time T _S .
This means that the charging voltages V ₄ and V ₅ of capacitors C ₁ and C ₂
It is shown as a waveform diagram. This delay time T _S
is expressed by the following equation.

Note that in the V ₄ and V ₅ waveforms in FIG. 4, the dotted line indicates the discharge characteristics when the switch CM ₃ is not present.

Therefore, here, the average value obtained by smoothing the charging voltages V ₄ and V ₅ of the capacitors C ₁ and C ₂ will be considered.
The average value of charging voltage V ₄ during charging and discharging (i.e., excluding the period T _S in which no discharging occurs) is ₄ , and the charging voltage is
If the average value during charging and discharging of V ₅ is ₅ , then ₄ , ₅
is expressed by the following formula.

₄ = T _A + T _C / (T _A + T _C ) + {(T _B + T _C ) − T _S } V _C (10
) ₅ = T _B + T _C / {(T _A + T _C ) − T _S } + (T _B + T _C ) V _C (11
) Note that in one measurement cycle consisting of the period of C _A measurement mode (T _A + T _C ) and the period of C _B measurement mode (T _B + T _C ), there is a period T during which no discharge occurs during each measurement mode. _S is included, and this period T _S
must be excluded from each measurement mode period, so
In equations (10) and (11), respectively, {(T _B +T _C )−
T _S }, {( _TA + T _C ) - T _S } are treated as the actual discharge time.

Therefore, in equations (10) and (11), equation 5 and equation (6)
T _A , T _C expressed by equations (8) and (9),
Substitute T _B and T _S.

₄ = R ₁ (C _A + C _SA ) + R _f C _f /R ₁ (C _A + C _SA )
+R ₂ (C _B +C _SB ) +2R _f C _f −VR ₃・C ₂ V _C (12) ₅ = R ₂ (C _B +C _SB ) +R _f C _f /R ₁ (C _A +C _SA )
+R ₂ (C _B + C _SB ) + 2R _f C _f −VR ₃・C ₂ V _C (13) The charging voltages V ₄ and V ₅ of capacitors C ₁ and C ₂ are given to buffer amplifiers DA ₁ and DA _2, respectively. , and then applied to the inverting input terminal of differential amplifier DA ₃ via resistors R ₇ and R ₈ . As a result, the charge voltage V ₄ ,
A voltage proportional to the difference in V ₅ ( ₄ − ₅ ) is extracted. Here, the output voltage of the differential amplifier DA ₃ V ₆
is expressed by the following equation.

V ₆ = K ( ₄ − ₅ ) + V _C1 (14) However, V _C1 = R ₉ /R ₉ + R ₁₀ V _C (15) Here, equation (14) is replaced by equation (12) and equation (13). Substituting the formula, formula (14) becomes as follows.

V ₆ = R ₁ (C _A + C _SA ) − R ₂ (C _B + C _SB )/R ₁ (C _A
+C _SA ) +R ₂ (C _B +C _SB ) +2R _f C _f −VR ₃・C ₂ V _C +V _C1 (16
) Here, the resistors R ₁ and R ₂ are usually set equal.
Therefore, R ₁ =R ₂ =R (17). Substitute equation (17) into equation (16).

V ₆ = C _A − C _B + R (C _SA − C _SB )/C _A + C _B + (C _S
A +C _SB +2R _f /RC _f -VR ₃ /R・C ₂ )V _C +V _C1 (18) Furthermore, stray capacitances C _SA and C _SB are usually made equal due to the design of capacitors C _A and C _B. is being done. Therefore, it is stipulated as follows.

C _SA = C _SB = C _S (19) Therefore, equation (18) can be rewritten as follows.

V ₆ =C _A −C _B /C _A +C _B +2C _S +2R _f /RC _f −VR ₃ /RC ₂ V _C +
V _C1 (20) Therefore, in equation (20), the resistance value of variable resistor VR ₃ , that is, so that _2CS + 2R _f /RC _f -VR ₃ /RC ₂ =0 (21)
Adjust and set the delay time T _S. Therefore, equation (20) can be rewritten as follows.

V ₆ =C _A −C _B /C _A +C _B V _C +V _C1 (22) Therefore, the influence of stray capacitance C _S can be removed. The output voltage V ₆ of the differential amplifier DA ₃ is applied to the non-inverting input terminal of the differential amplifier DA ₄ via the span adjustment resistor VR ₁ . The differential amplifier DA ₄ controls the current flowing through the output transistor T _{4 in accordance with the differential voltage (4-5 ) ,} thereby controlling the output current I flowing through the load L. This output current I flows through a feedback resistor R ₁₇ whose voltage drop is fed back to the non-inverting input terminal of _the differential amplifier DA ₄ via a resistor R ₁₂ according to known two-wire measurement techniques. Ru. Thereby, the voltage at the non-inverting input terminal and the voltage at the inverting input terminal of the differential amplifier DA ₄ are made equal.

Here, the current flowing through the transistor T ₄ is controlled according to the output voltage V ₆ of the differential amplifier DA ₄ , and the output current I is related to the current flowing through this transistor T ₄ , so this output voltage I is It is expressed by the formula.

I∝V ₆ (23) That is, I∝C _A −C _B /C _A +C _B =Δd/d (24) That is, the output current I is proportional to the mechanical displacement amount Δd.

In the embodiment shown in FIG. 2, a C-MOS type D-flip-flop is used as a detection means for detecting that the charging voltage of capacitors C _A and C _B has reached a predetermined value. As mentioned above, it is also possible to use an ordinary D-flip-flop, in which case a comparator is inserted between this flip-flop and switch _CM1 , and the reference voltage of the comparator is set appropriately to achieve the same function. be able to.

Furthermore, the two-wire measurement technique consisting of differential amplifiers DA ₃ , DA ₄ , output transistor T ₄ , feedback resistor R ₁₇ , resistor network VR ₂ , R ₁₂ , etc. is well known, and the design can be modified as appropriate.

〔Effect of the invention〕

As explained above, according to the present invention, two measurement capacitors that differentially change depending on the amount of mechanical displacement are charged and discharged, and when the charging pressure reaches a predetermined value is alternately detected. and operating the bistable means based on this detection and charging the first capacitor during one stable output condition and the second capacitor during the other stable output condition;
Since the output current is controlled based on the difference between the charged voltages of both capacitors, there is no need for an oscillation circuit or transformer as in the conventional case, and error factors such as frequency are eliminated. The amount of displacement can be measured with high accuracy.

Moreover, a delay means is provided which is driven based on detection that the charging voltage of the measurement capacitor has reached a predetermined value and delays the start of discharge of each of the first and second capacitors, and the delay time of this delay means is set to an appropriate value. By setting , it is possible to compensate for the influence of stray capacitance on the measurement capacitor, thereby further increasing measurement accuracy.

[Brief explanation of drawings]

Fig. 1 is a principle diagram for explaining a method of detecting a mechanical displacement amount by converting it into a capacitance change, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is a circuit diagram of an embodiment of the present invention. FIG. 4 is a partial circuit diagram for explaining the MOS switch, and a waveform diagram for explaining the operation of the embodiment of FIG. 2. C _A , C _B ...Measurement capacitor, CM ₁ , CM ₂ ,
_CM3 ...C-MOS switch, _Q1 , _Q2 , _Q3 ...D
−Flip-flop, DA ₃ , DA ₄ ... Differential amplifier, T ₁ to T ₅ ... Transistor, C ₁ , C ₂ , C ₃ ...
Capacitor, E...power supply, L...load.

Claims (1)

[Claims] 1. Two measuring capacitors whose capacitance values differentially change according to mechanical displacement, a circuit for charging and discharging these two measuring capacitors, and a charging voltage of the two measuring capacitors. A detection means that alternately detects that a predetermined value has been reached, a bistable means that is driven by the detection means to perform bistable operation, and a bistable means that is charged during one output state of the bistable means and whose other output state is a first capacitor discharged during a period of;
a second capacitor that is charged during the other output state of the bistable means and discharged during the one output state; a differential amplifier that outputs a voltage proportional to the difference between the charging voltages of the capacitors; a current control means that is controlled by the differential amplifier and supplies an output current representing the mechanical displacement; and a delay means for delaying the start of discharge of each of the first and second capacitors by a predetermined time, and by appropriately setting the delay time of the delay means, the influence of stray capacitance on the measurement capacitor is compensated. Characteristic displacement measurement device. 2. In the displacement measuring device according to claim 1, the detection means comprises a C-MOS type flip-flop and a switch means that alternately guides the charging voltage of the two measuring capacitors to the flip-flop. A displacement measuring device featuring: 3. In the displacement measuring device according to claim 1 or 2, the bistable means allows the first capacitor to be charged during one of the output states and during the other output state. A displacement measuring device characterized by comprising a switch means for enabling charging of a second capacitor. 4. In the displacement measuring device according to any one of claims 1 to 3, the delay means includes a C-MOS type D flip-flop;
1. A displacement measuring device comprising a switch means incorporated in a discharge circuit for the first and second capacitors and controlled on and off by the flip-flop.