JPH0350834A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic resistance in a bipolar transistor by forming a mask film at emitter and base electrodes formation parts, and forming openings, and stacking a semiconductor film and a flattening film on the openings and the mask films. CONSTITUTION:A mask film 7, which has windows at an emitter formation part and a base electrode formation part, is formed on insulating films 4 and 5, and with this as a mask, the insulating films 4 and 5 are removed selectively by etching so as to form openings. Next, on the openings and the mask film 7, a semiconductor film and, successively, a flattening film 9 for almost flattening the surface are stacked. Next, the semiconductor film 8 and the flattening film 9 on the region excluding the openings are removed by etching, and successively the mask 7 is removed. Next, with the semiconductor films 8 and the fattening films 9, left in the openings, as masks, opposite conductivity type impurities are introduced through the insulating films 4 and 5 so as to form an outer base layer 10. And with the insulating films 4 and 5 as masks, one conductivity type impurities are introduced selectively from the opening of the emitter electrode formation part into the semiconductor film 8 and the inner base layer 6 so as to form an emitter layer 12.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a bipolar transistor, the purpose is to reduce parasitic base resistance by forming an emitter and an external base in self-alignment, and to reduce parasitic base resistance by forming an emitter and an external base in self-alignment. forming an internal base layer and an insulating film covering the internal base layer, and forming a mask film having windows in the emitter electrode forming part and the base electrode forming part on the insulating film, using this as a mask to form the insulating film. A step of selectively etching and removing a film to form an opening, a step of depositing a semiconductor film on the opening and the mask film, and then a planarizing film for substantially planarizing the surface, and a step of depositing a semiconductor film on the opening and the mask film, The semiconductor film and the planarization film on the area are etched away, and then the mask film is removed. a step of introducing impurities of opposite conductivity type to form an external base layer; and a step of etching away the upper semiconductor film and planarization film, leaving a portion of the semiconductor film connected to the internal base layer within the opening. , the step of selectively introducing impurities of one conductivity type into the semiconductor film and the internal base layer through the opening of the emitter electrode forming portion using the insulating film as a mask to form an emitter layer.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bipolar transistor.

In order to realize higher speed semiconductor ICs including bipolar transistors, it is necessary to reduce parasitic capacitance and parasitic resistance, and in particular, it is required to reduce parasitic base resistance by reducing the distance between the emitter and the external base.

[Conventional technology]

FIG. 3 is a cross-sectional view showing the main part of the manufacturing process of a conventional bipolar transistor. As shown in figure (a), p
The n-type epitaxial layer 31 on the type St substrate 30 is separated by an insulating film 32 for element isolation, and boron (B) ions are implanted through the thermal oxide film 33 and nitride film 34 formed thereon, followed by heat treatment. An internal base diffusion layer 35 is formed. Next, as shown in the same figure [present], a resist pattern 36 is formed.
Using this as a mask, B ions are implanted and heat treated to form an external base diffusion layer 37. After removing the resist pattern 36, a resist pattern 3 having an opening for forming an emitter electrode is formed as shown in FIG.
8 is formed, and using this as a mask, the oxide film 33 and the nitride film 34 are selectively etched to form an emitter opening. After removing the resist pattern 38, the same figure (d) is shown.
As shown in FIG. 3, an emitter electrode 39 made of n-type child crystal St is selectively formed on the emitter opening, and an emitter diffusion layer 40 is formed by heat treatment. Next, the same figure (
As shown in e), the oxide film 33 is formed on the external base diffusion layer 37.
Then, a hole is made in the nitride film 34 to selectively form a base extraction electrode 41 made of p-type polycrystalline Si.

[Problem to be solved by the invention]

As described above, in the conventional method, the distance between the emitter and the external base member, that is, the external base diffusion layer 37 shown in FIG.
The distance between the resist pattern 3 and the emitter diffusion layer 40 is
6 and 38, and a large value must be set in consideration of the alignment error in design. Further, even in actual manufacturing, the pattern is not constant due to pattern alignment errors between lofts and variations in etching accuracy of the emitter opening. This makes it difficult to reduce the parasitic base resistance determined by the distance between the emitter and the external base, and increases its dispersion, resulting in deterioration of the high frequency characteristics of the device and dispersion of the characteristics between lofts.

Therefore, an object of the present invention is to form an emitter and an external base in a self-aligned manner to reduce parasitic base resistance.

[Means to solve the problem]

The solution to the above problem is to cover the inner base layer of the opposite conductivity type on the surface of the -conductivity type semiconductor layer and the inner base layer! ! A step of forming an edge film, and forming a mask film having windows in the emitter electrode forming part and the base electrode forming part on the insulating film, and using this as a mask, selectively etching away the insulating film to form an opening. a step of depositing a semiconductor film on the opening and the mask film, followed by a planarization film for substantially planarizing the surface, and a step of depositing the semiconductor film and the planarization film on a region other than the opening. and then removing the mask film, using the semiconductor film and planarization film left in the opening as a mask, and introducing impurities of opposite conductivity type through the insulating film to form an external base layer. a step of etching away the upper semiconductor film and planarization film while leaving a portion of the semiconductor film connected to the internal base layer within the opening; and a step of etching the insulating film from the opening of the emitter electrode formation region. This is achieved by a method for manufacturing a semiconductor device characterized by including a step of selectively introducing impurities of one conductivity type into a semiconductor film and an internal base layer using a mask to form an emitter layer.

[Function] In the method according to the present invention, first, the openings of the emitter electrode forming portion and the base electrode forming portion are simultaneously formed using one mask film, for example, a resist pattern.

Therefore, the spacing between the emitter and base openings can be reduced to the limit of pattern miniaturization, and fluctuations due to lot-to-lot variations can also be reduced. Next, in the present invention, a semiconductor film and a planarization film are deposited on the resist pattern at a low temperature below the curing temperature of the resist. For example, an ECR plasma CVD method can be used to deposit a silicon film as a semiconductor film and an oxide film as a planarization film. In the ECR plasma CVD method, a magnetic field is applied along with microwave power to turn the raw material gas into plasma, and the electrons that have gained high energy by absorbing the microwave power through cyclotron resonance increase the ionization rate of the plasma, so A more active plasma can be obtained than with the thermal CVD method or the plasma CVD method. Therefore, it is possible to deposit a high-quality film without heating the substrate (below the curing temperature of the resist). Therefore, after etching away the silicon film and oxide film deposited on the resist pattern other than the openings, It becomes possible to remove the resist pattern with a resist stripping solution.

In the present invention, a semiconductor film and a planarizing film that fills the recesses of the film are formed in the openings of the emitter electrode forming part and the base electrode forming part by the method described above, and this is used as a mask to introduce impurities and externally. The emitter and external base can be formed in self-alignment by forming a base layer, removing the upper part of the semiconductor film and the planarization film, and then introducing impurities into the opening of the emitter electrode formation part to form the emitter layer. .

[Example] Figures 1 (a) to (5) are process cross-sectional views according to examples of the present invention, and Figure 2 is a cross-sectional view of an ECR plasma CVD apparatus used in this example. Refer to and explain.

First, as shown in Figure (a), an n-type epitaxial layer N2 on a p-type Si substrate 1 is separated by an element isolation insulating film 3 according to the normal manufacturing process of bipolar transistors, and a film thickness of 3 (100 thermal oxide film 4, followed by normal thermal CVD
A nitride film 5 with a thickness of 5 (10) is formed by a method. Then, using the thermal oxide film 4 and nitride film 5 as masks, an acceleration voltage of 16
B ions are implanted under the conditions of 0 keV and a dose of 1×10 14 cm −2 and heat treated to form the internal base diffusion layer 6 . Next, as shown in FIG. 2B, a positive resist pattern 7 having a thickness of 1 μm and having openings for forming an emitter electrode and a base electrode is formed. Next, a silicon film 8 with a thickness of 1 (100%) was deposited as shown in FIG. An oxide film 9 is deposited.

FIG. 2 shows a cross-sectional view of an ECR plasma CVD apparatus used to deposit silicon film 8 and oxide film 9. As shown in FIG. In the figure, a sample on which the resist pattern 7 has been formed is set in a sample chamber 21, and source gas is introduced into the sample chamber 21 and plasma chamber 22 through gas inlets 28 and 29, respectively, and the gas pressure is set to 1×10-'. Hold at Torr. At this time, the substrate was not heated. A frequency of 2.45 GHz is input into the plasma chamber 22 from the outside through a waveguide 24.
A microwave power of 8 (10 W) is supplied to generate plasma, and a magnetic coil 23 placed around the plasma chamber 22 generates a magnetic field that diverges from the plasma chamber 22 toward the sample chamber 21.Microwave frequency and plasma When the magnetic field is set so that the rotation period of the electrons in the microwave matches, the electrons cause cyclotron resonance, absorb microwave energy, become highly energetic, promote ionization of the plasma, and create active plasma. The formed plasma is introduced into the sample chamber 21 by the divergent magnetic field, and a film is deposited on the substrate.SiH4 gas is flowed into the sample chamber 21 as a raw material gas, and Ar gas is introduced into the plasma chamber 22.
When gas is flowed, a polycrystalline or amorphous silicon film is obtained, and when SiH4 gas is flowed into the sample chamber 21 and 0□ gas is flowed into the plasma chamber 22, an oxide film is obtained.

After depositing the silicon film 8 and the oxide film 9 as shown in FIG. 1(C) by the above method, the surface of the oxide film 9 is etched until the surface of the silicon film 8 on the resist pattern 7 is exposed. The oxide film 9 is left only within the opening. Next, using the oxide film 9 left in the opening as a mask, the silicon film 9 is etched until the surface of the resist pattern 7 is exposed, and then the resist pattern 7 is removed by immersion in a resist stripping solution or by ashing.
As shown in FIG. 2D, the silicon film 8 and the oxide film 9 are left only in the opening. As mentioned above, E
When the silicon film and oxide film are deposited by the CR plasma CVD method, the substrate temperature can be maintained below the resist curing temperature, so the resist pattern 7 can be easily removed by the above-mentioned method. Next, an acceleration voltage of 1 is applied using the silicon film 8 and oxide film 9 in the opening as a mask.
B ions are implanted under the conditions of 60 keV and a dose of IXl015 cm-2 to form the external base diffusion layer 10.

Then, as shown in FIG. 3E, the oxide film 9 inside the opening and the silicon film 8 on the side walls of the opening are removed by etching, leaving the silicon film 8 only on the internal base diffusion layer 6 inside the opening. Next, as shown in Figure 1), a resist pattern 11 with a hole formed above the opening that will become the emitter electrode is formed, and using this as a mask, the silicon film 8 in the opening is exposed to an acceleration voltage of 40 keV and a dose of lXl0''. The emitter diffusion layer 12 is implanted with As ions and heat-treated under the condition of "cm-".
form. After removing the resist pattern 11, a resist pattern 13 with an opening that will become a base electrode is formed as shown in FIG.
A base contact 14 is formed by implanting B ions under the condition of ``thcm-''.
A bipolar transistor can be obtained by forming the emitter electrode 15 and the base lead-out electrode 16 made of an I film.

〔Effect of the invention〕

As described above, according to the present invention, the emitter and the external base can be formed in self-alignment. Therefore, it is possible to reduce the distance between the emitter and the external base compared to the conventional method, thereby reducing parasitic base resistance and increasing the speed of the bipolar transistor.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are process cross-sectional views showing embodiments of the present invention. FIG. 2 is an ECR plasma CVD process used in an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the device, and a process cross-sectional view showing problems in the conventional example. In the figure, 1.30 is a Si substrate, 2.31 is an evixial layer, 3.32 is an insulating film for element isolation, 4.33 is a thermal oxide film, 5.34 is a nitride film, 6.35 is an internal base diffusion layer , 7.11.13.36.38 is a resist pattern, 8 is a silicon film, 9 is an oxide film, 10.37 is an external base diffusion layer, 12.40 is an emitter diffusion layer, 14 is a base contact, 15.39 is an emitter electrode, 16.41 is a base extraction electrode, 21 is a sample chamber, 22 is a plasma chamber, 23 is a magnetic coil, 24 is a waveguide, 25 is an exhaust port, 26 is a sample support stand, 27 is a sample, 28. 29 is a gas inlet.ゝ2、It、PiR≦a month/one? Noshi Eyorebutari 17o T-Ding-o-shigo-gamma side chart genealogy c child 2)

Claims (1)

[Claims] An internal base layer (6) of the opposite conductivity type on the surface of the semiconductor layer (2) of one conductivity type and an insulating film (4) covering the internal base layer (6).
, 5), and forming a mask film (7) having a window in the emitter electrode forming part and the base electrode forming part on the insulating film (4, 5), and using this as a mask, forming the insulating film (4, 5). . ), etching away the semiconductor film (8) and the planarization film (9) on the area other than the opening, and then removing the mask film (7).
a step of removing the semiconductor film (8) and the planarization film (9) left in the opening.
) as a mask, introducing impurities of opposite conductivity type through the insulating films (4, 5) to form an external base layer (10), and forming a semiconductor film () connected to the internal base layer (6) in the opening. A process of etching away the upper semiconductor film (8) and planarization film (9), leaving the part 8), and removing the semiconductor film from the opening of the emitter electrode formation part using the insulating film (4, 5) as a mask. A method for manufacturing a semiconductor device, comprising the step of selectively introducing impurities of one conductivity type into a film (8) and an internal base layer (6) to form an emitter layer (12).