JPH0350732A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0350732A JPH0350732A JP18535589A JP18535589A JPH0350732A JP H0350732 A JPH0350732 A JP H0350732A JP 18535589 A JP18535589 A JP 18535589A JP 18535589 A JP18535589 A JP 18535589A JP H0350732 A JPH0350732 A JP H0350732A
- Authority
- JP
- Japan
- Prior art keywords
- measuring electrode
- integrated circuit
- cutting
- measurement electrode
- cutting line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005259 measurement Methods 0.000 claims description 21
- 239000000523 sample Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体装置、特に集積回路の製造において、
回路中に使用されるトランジスタ、抵抗器などの素子革
体の電気的特性を試験するための試験用回路の第4造に
関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention is applicable to manufacturing semiconductor devices, especially integrated circuits.
The present invention relates to a fourth structure of a test circuit for testing the electrical characteristics of element bodies such as transistors and resistors used in the circuit.
[従来の技術]
集積回路の集積度が太き(なり、素子サイズが小さ(な
るにつれて、試験、評価すべき項目が多(なり、前記試
験用回路も複雑化する傾向にある複雑化、大型化した試
駆用回路は、集積回路本体の高集積度を保つため、集積
回路本体の外にあるスクライブ領域、即ち完成した集積
回路チップを切断する際の「切りしろ」領域内に設置す
ることが多い。[Prior Art] As the degree of integration of integrated circuits increases and the element size decreases, the number of items to be tested and evaluated increases. In order to maintain the high degree of integration of the integrated circuit itself, the trial circuit that has been standardized must be installed in the scribe area outside the integrated circuit itself, that is, in the "cut margin" area when cutting the completed integrated circuit chip. There are many.
評価が終了して不要になったスクライブ領域内の試験用
回路は、集積回路チップを切断する際に切り屑と化して
消滅するから、上記の方法によって、集積回路チップ本
体のサイズをいたずらに太き(すること無(、大型の試
験用回路を設置することが可能になる。The test circuit in the scribe area that is no longer needed after evaluation is turned into chips and disappears when the integrated circuit chip is cut, so the above method can be used to unnecessarily increase the size of the integrated circuit chip. This makes it possible to install large test circuits without having to do anything.
[発明が解決しようとする課題]
しかし、従来の技術によって前記スクライブ領域内に試
験用回路を設置した場合、試°験測定時に測定用の探針
を受けるための大型の測定用電極を設置しなければなら
ず、この測定用電極がアルミニウムなどの柔らかい金属
で形成されることが一般的であるため、集積回路チップ
を切断する際に測定電極の切り屑が「ひげ状」にめ(れ
上がって集積回路本体に接触するなどして、故障の原因
になる危険があった。[Problems to be Solved by the Invention] However, when a test circuit is installed within the scribe area using the conventional technology, a large measurement electrode is installed to receive the measurement probe during test measurement. This measurement electrode is generally made of a soft metal such as aluminum, so when cutting the integrated circuit chip, chips from the measurement electrode curl up in a "whisker-like" pattern. There was a risk that the product could come into contact with the integrated circuit itself and cause a malfunction.
本発明は、このような従来の半導体集積回路の試験用回
路測定用電極の「ひげ状」めくれあがりの問題を解決す
るもので、その目的とするところは、半導体集積回路の
故障率の低減、及び信頼性の向上を提供するところにあ
る。The present invention solves the problem of the "whisker-like" curling up of conventional test circuit measurement electrodes for semiconductor integrated circuits, and aims to reduce the failure rate of semiconductor integrated circuits, and improved reliability.
[課題を解決するための手段]
本発明の半導体装置は、半導体基板表面に完成品チップ
切断用の「切りしろ」、即ちスクライブ領域を有し、前
記スクライブ領域に素子特性試験のための試験用回路と
、前記試験用回路を測定する除の探針を受けるための測
定用電極とを有する半導体装置において、前記測定用電
極に切り欠きを有することを特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention has a "cutting margin", that is, a scribe area for cutting finished product chips on the surface of a semiconductor substrate, and a test area for testing device characteristics in the scribe area. A semiconductor device having a circuit and a measurement electrode for receiving a probe for measuring the test circuit, characterized in that the measurement electrode has a notch.
[作用コ
本発明の上記の+4成によれば、前記測定用電極に適切
な切り欠きを設けることによって、測定用電極が切断線
に沿って細かく分断された形となり、集積回路チップを
切断するliK測定電極の切り屑が「ひげ状」にめくれ
上がる現象を防止することができる。[Function] According to the above-mentioned +4 of the present invention, by providing an appropriate notch in the measuring electrode, the measuring electrode becomes finely divided along the cutting line, and the integrated circuit chip is cut. It is possible to prevent the phenomenon in which the chips of the liK measurement electrode curl up in a "whisker-like" manner.
[実施例]
第1図は、本発明の実施例における半導体装置の試験用
回路の測定用電極を示す平面図であって切り欠きの形状
を例示する。また第2図は、第1図に示した電極の切断
線にそった断面図である1はアルミニウムで形成された
測定用電極、2は測定用電極に設けられた切υ欠き、3
は半導体基板、4は二酸化硅素膜、5は集積回路本体チ
ップとの境界線、6は本体チップを切断する際の切断線
である。[Example] FIG. 1 is a plan view showing a measurement electrode of a test circuit of a semiconductor device in an example of the present invention, and illustrates the shape of a notch. FIG. 2 is a sectional view taken along the cutting line of the electrode shown in FIG. 1. 1 is a measurement electrode made of aluminum, 2 is a notch provided in the measurement electrode, and 3
4 is a semiconductor substrate, 4 is a silicon dioxide film, 5 is a boundary line with the integrated circuit main body chip, and 6 is a cutting line when cutting the main body chip.
測定用電極1及び切り欠き2は、半導体基板3の上に形
成した絶縁膜である二酸化硅素膜4の上にスパッタ快ン
グなどの方法で形成した均一なアルミニウム膜を、フォ
ト・エツチングなどの方゛法で選択的に除去して一度に
形成する。The measurement electrode 1 and the notch 2 are formed by photo-etching a uniform aluminum film formed on a silicon dioxide film 4, which is an insulating film formed on a semiconductor substrate 3, by a method such as sputtering. It is selectively removed using the ``method'' and formed all at once.
このような構造により、測定用電極1が切断線6に沿っ
て細かく分断之れた形となり、集憧回路チップを切断す
る際に測定電極1の切り屑が「ひげ状」にめ(れ上がる
現象を防止することができる。Due to this structure, the measurement electrode 1 has a shape in which it is finely divided along the cutting line 6, and when cutting the collector circuit chip, the chips of the measurement electrode 1 are curled up in a "beard shape". The phenomenon can be prevented.
[発明の効果]
以上述へたように本発明によれば、スクライブ領域に設
置した試験用回路測定用電極を集積回路チップ切断時の
切断線に沿って細かく分断することにより、測定電極の
切り屑が「ひげ状」にめくれ上がって集積回路本体に接
触し品質が低下するのを防止する効果を有する。[Effects of the Invention] As described above, according to the present invention, the test circuit measurement electrode installed in the scribe area is finely divided along the cutting line when cutting the integrated circuit chip, thereby making it possible to cut the measurement electrode. This has the effect of preventing debris from curling up in a "whisker-like" manner and contacting the integrated circuit body, thereby reducing quality.
第1図は、本発明の実施例における半導体装置の試験用
回路の測定用電極を示す平面図である。
第2図は、第1図に示した電極の切断線に沿った断面図
である。
1・・・・・・−・・アルミニウムで形成された測定用
電極2・・・・・・・・・測定用電極に設けられた切り
欠き3・・・・・・・・・半導体基板
4・・・・・・〜・・二酸化硅素膜
5・・・・・・・・・集積回路本体チップとの境界線6
・・・・・・・・・本体チップを切断する際の切断線以
上FIG. 1 is a plan view showing measurement electrodes of a test circuit for a semiconductor device in an embodiment of the present invention. FIG. 2 is a sectional view taken along the cutting line of the electrode shown in FIG. 1...Measurement electrode formed of aluminum 2...Notch provided in the measurement electrode 3...Semiconductor substrate 4 ......... Silicon dioxide film 5 ...... Boundary line with integrated circuit main chip 6
・・・・・・・・・Above the cutting line when cutting the main chip
Claims (1)
即ちスクライブ領域を有し、前記スクライブ領域に素子
特性試験のための試験用回路と、前記試験用回路を測定
する際の探針を受けるための測定用電極とを有する半導
体装置において、前記測定用電極に切り欠きを有するこ
とを特徴とする半導体装置。"Cut" for cutting finished product chips on the surface of the semiconductor substrate,
That is, in a semiconductor device that has a scribe region, and has a test circuit for element characteristic testing in the scribe region, and a measurement electrode for receiving a probe when measuring the test circuit, A semiconductor device characterized by having a notch in an electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18535589A JPH0350732A (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18535589A JPH0350732A (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0350732A true JPH0350732A (en) | 1991-03-05 |
Family
ID=16169339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18535589A Pending JPH0350732A (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0350732A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0621188A (en) * | 1991-12-13 | 1994-01-28 | Yamaha Corp | Semiconductor wafer |
US9406571B2 (en) | 2014-01-31 | 2016-08-02 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device including inline inspection |
-
1989
- 1989-07-18 JP JP18535589A patent/JPH0350732A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0621188A (en) * | 1991-12-13 | 1994-01-28 | Yamaha Corp | Semiconductor wafer |
US9406571B2 (en) | 2014-01-31 | 2016-08-02 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device including inline inspection |
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