JPH0350722A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To solve the problem of non-ohmic properties resulting from plasma damage when contact holes are formed; besides, allow both channels to obtain stable ohmic contact by masking a contact hole that is formed on a P<+> type diffusion layer after forming the contact hole and etching Si only at a contact hole which is formed on an N<+> type exposed diffusion layer. CONSTITUTION:A contact hole which is formed on a P<+> type diffusion layer 1 is masked with a photo resist 4. Further, Si is exposed from the contact hole and dry etching is performed to Si sb that only slight damage may occur. In this way, ohmic contact with contact holes in both channels is obtained by etching only Si.

Description

[Detailed Description of the Invention] [Industrial Application] The present invention provides a method of masking the contact hole on the P+ diffusion layer after forming the contact hole of a complementary semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device in which dry etching is performed only on contact holes on exposed N 2 diffusion layers to perform S1 etching.

[Prior Art] With the development of microfabrication technology associated with the increase in the density of integrated circuits, the etching process for contact holes is being shifted from wet chemical etching to dry etching using plasma. However, when etching the contact hole using high-frequency discharge, plasma damage accumulates on the S1 surface in the contact hole, causing a major problem in that ohmic contact cannot be established.Contact hole formation using conventional technology , 51 exposed after dry etching the phosphor glass and oxide film layer.
By dry etching the surface with low damage,
Ohmic contact was maintained, but as shown in Figure 3, the relationship between the etching amount of 81 and contact resistance is critical, so the etching amount of S1 had to be kept within ±5% for 100 people, and stable contact was maintained. This had the disadvantage that ohmic contact could not be obtained.

[Problems to be Solved by the Invention] The present invention eliminates such drawbacks, and its purpose is to:
The object is to solve the non-ohmic problem caused by plasma damage during contact hole formation and to obtain stable ohmic contact for both channels.

[Means for Solving the Problems] The present invention provides contact holes formed on a P+ diffusion layer after forming contact holes of a complementary semiconductor device.
A method for manufacturing a semiconductor device in which ohmic contact can be obtained in both channels by dry etching only the contact hole formed on the exposed N+ diffusion layer by masking it with an photoresist or the like and performing Si etching.

[Examples] The present invention will be described in detail below based on Examples. 1st
The figure shows a complementary MOS 4.0 that performs S1 etching using conventional technology. FIG. 2 is a cross-sectional view of a complementary MO3 structure subjected to S1 etching using the present invention. 1 in FIG. 2 is a P+ diffusion region, 2 is a , a silicon oxide film by LOOO8, 3 is a phosphorus glass layer, 4 is a photoresist for masking the contact hole formed on the P diffusion layer according to the present invention, 5 is a LU S1 diffusion region, 8 9 is an S1 substrate which is a raw material; 9 is an oxide film; 10 is a low-damage dry etching process for etching exposed SI, which may be a contact hole; and 11 is polysilicon used as a gate electrode and wiring.

When etching is performed in step 10 in the state shown in Figure 1,
The results of S1 etching amount and contact resistance are shown in FIG.

[Effects of the Invention] In the conventional method, there was a problem that unless the etching amount of Sl was controlled to 100, ohmic properties of the contacts in both channels could not be obtained.
As shown in the figure, the amount of Si etched increases (Fig. 5 α). The contact hole formed on the P diffusion layer is masked with photoresist, and only the contact hole 81 formed on the N+ diffusion layer is etched. By performing this, ohmic contact with the contact holes of both channels can be obtained, and at the same time, the reliability of the semiconductor device is improved.

In this explanation, photoresist is used as the mask pattern material, but similar results can be obtained with any photosensitive organic film such as polyimide that does not lose its masking properties during S1 etching.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device having a complementary MO3 structure subjected to S1 etching using a conventional technique. FIG. 2 is a cross-sectional view of a semiconductor device having a complementary MO3 structure when performing S1 etching using the present invention. FIG. 5 is a diagram showing the relationship between S1 etching pattern and contact resistance when S1 etching is performed using the conventional technique. (α) in FIG. 6 is the result in contact with the P 2 diffusion layer, and Cb> in FIG. 3 is the result in contact with the N+ diffusion layer. 1...P+ diffusion region 2...Silicon intoxication film by LOOO3 6...Phosphorous glass layer 4...・Photoresist 5・・・・・・n, ″″81 Substrate area 6...
・・・・・・P″″S1 board area 7・・・・・・・・・N
10 Diffusion region 8... S1 substrate 9 which is a raw material...
...Oxide film layer 10...Dry etching 11 for etching Sl...Polysilicon

Claims (1)

[Claims] In the process of forming a contact hole for a complementary semiconductor device, a contact hole forming process is performed in which a phosphorous glass layer and an oxide film layer are etched using a dry etching method, and a P^+ diffusion layer is formed over the contact hole formed in the same process. A method for manufacturing a semiconductor device, comprising: a mask pattern forming step for masking a contact hole; and in the same step, dry etching is performed on Si in the contact hole portion that is exposed without being covered by the formed mask.