JPH0349406Y2 - - Google Patents
Info
- Publication number
- JPH0349406Y2 JPH0349406Y2 JP1984196017U JP19601784U JPH0349406Y2 JP H0349406 Y2 JPH0349406 Y2 JP H0349406Y2 JP 1984196017 U JP1984196017 U JP 1984196017U JP 19601784 U JP19601784 U JP 19601784U JP H0349406 Y2 JPH0349406 Y2 JP H0349406Y2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- electrode
- groove
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 26
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 3
- 229910017401 Au—Ge Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000113 methacrylic resin Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Description
【考案の詳細な説明】
［産業上の利用分野］
本考案は２個又は３個以上の発光面を有する発
光ダイオードに係り、特に電極を改良したものに
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a light emitting diode having two or more light emitting surfaces, and particularly to one with improved electrodes.
［従来の技術］
複数個の発光点または発光面を有する発光ダイ
オードの従来の技術としては、例えば実開昭57−
83766号公報に示されているものがある。すなわ
ち、第３図に示す如く一枚のプリント基板１上に
独特の発光ダイオードチツプ２を並べるようにし
たもので、光拡散シート３と反射枠４との併用に
より文字等の表示に使用するようになつている。[Prior Art] As a conventional technology of a light emitting diode having a plurality of light emitting points or light emitting surfaces, for example,
There is one shown in Publication No. 83766. That is, as shown in FIG. 3, unique light emitting diode chips 2 are arranged on a single printed circuit board 1, and when used in combination with a light diffusion sheet 3 and a reflective frame 4, it can be used to display characters, etc. It's getting old.
また、第４図に示す如く、一枚の結晶基板６の
表面にPN接合を形成し、このPN接合のＰ層７
の表面に電極８を設けて、これにアルミニウム線
又は金線等のリード線９をボンデイングする一
方、結晶基板６の裏面に共通電極１０を設けたも
ので、光プリンタ分野等の検討が進められてい
る。 Further, as shown in FIG. 4, a PN junction is formed on the surface of one crystal substrate 6, and a P layer 7 of this PN junction is formed.
An electrode 8 is provided on the surface of the crystal substrate 6, and a lead wire 9 such as an aluminum wire or a gold wire is bonded to this, while a common electrode 10 is provided on the back surface of the crystal substrate 6. Studies are progressing in the field of optical printers, etc. ing.
［発明が解決しようとする問題点］
しかしながら、第３図の構造のものでは、リー
ド線５を電極１１にボンデイングする際に圧力の
不均一等が生じ、発光ダイオードチツプ２と電極
１１との間に均一な接触が得られにくく、高い信
頼性が望めないばかりか、接触抵抗に起因する発
光強度のバラツキが生じるという欠点があつた。
また、第４図の構造のものでは、結晶基板６の裏
面に共通電極１０を設けるようにしたことによ
り、基板６が介在するため電極８，１０間の抵抗
が異なる基板中央部にある発光面と両端にある発
光面とでは自ずと電流差が生じ、そのため発光強
度のバラツキが生じるという欠点があつた。[Problems to be Solved by the Invention] However, in the structure shown in FIG. 3, uneven pressure occurs when bonding the lead wire 5 to the electrode 11, resulting in Not only is it difficult to obtain uniform contact between the two and high reliability cannot be expected, but there are also disadvantages in that the emission intensity varies due to contact resistance.
In addition, in the structure shown in FIG. 4, since the common electrode 10 is provided on the back surface of the crystal substrate 6, the resistance between the electrodes 8 and 10 is different due to the presence of the substrate 6 on the light emitting surface in the center of the substrate. A current difference naturally occurs between the light emitting surface and the light emitting surfaces at both ends, and this has the drawback of causing variations in light emission intensity.
その結果、従来の発光ダイオードでは、発光強
度が均一で、しかも信頼性の高い複数個の発光面
を持つ発光ダイオードを必要とする光プリンタに
適用することが未だ困難であつた。 As a result, it is still difficult to apply conventional light emitting diodes to optical printers that require light emitting diodes with a plurality of light emitting surfaces with uniform light emission intensity and high reliability.
［考案の目的］
本考案の目的は、電極をすべて表面に設けると
共に各発光ダイオード領域に均一な電流密度を与
えることによつて、上記した従来技術の問題点を
解消し、発光面数の増大化に伴い発光ダイオード
長が大きくなつても、各発光面の発光強度が均一
で、信頼性の高い優れた発光ダイオードを得るこ
とである。[Purpose of the invention] The purpose of the invention is to solve the above-mentioned problems of the conventional technology and increase the number of light-emitting surfaces by providing electrodes on all surfaces and providing uniform current density to each light-emitting diode region. An object of the present invention is to obtain an excellent light-emitting diode with uniform light emission intensity on each light-emitting surface and high reliability even when the length of the light-emitting diode increases as the light-emitting diode length increases.
［考案の概要］
上記目的に沿う本考案の構成は、結晶基板上に
成長させた結晶層に隆起状の発光ダイオード領域
を形成する溝を設け、この溝の底部に露出した基
板表面に発光ダイオード領域を囲む第１の電極
を、また発光ダイオード領域頂部の結晶層表面に
発光面を囲む第２の電極をそれぞれ独立して設け
たことを特徴とする。これにより電極と発光ダイ
オード領域との接触を安定にするとともに電極間
の抵抗を均一化できるようにし、発光面の電流密
度が不均一になつたり、発光強度にバラツキが生
じたりしないようにしたものである。[Summary of the invention] The structure of the present invention, which meets the above objectives, is to provide a groove for forming a raised light emitting diode region in a crystal layer grown on a crystal substrate, and to form a light emitting diode on the substrate surface exposed at the bottom of the groove. It is characterized in that a first electrode surrounding the region and a second electrode surrounding the light emitting surface are provided independently on the surface of the crystal layer at the top of the light emitting diode region. This stabilizes the contact between the electrode and the light emitting diode area, and also equalizes the resistance between the electrodes, preventing uneven current density on the light emitting surface and variation in light emission intensity. It is.
［実施例］
本考案の実施例を第１図〜第２図に基づいて説
明すれば以下の通りである。[Example] An example of the present invention will be described below based on FIGS. 1 and 2.
第１図は発光ダイオードの断面図、第２図は同
平面図である。この発光ダイオードは次のように
して構成される。同図に示す如く一導電型、例え
ばＰ型結晶基板１５上に、液相エピタキシヤル成
長法により基板１５と反対導電型の第１結晶層と
してのｎ型エピタキシヤル層１６及び基板１５と
同じ導電型の第２結晶層としてのＰ型エピタキシ
ヤル層１７を同時成長させる。次いで、ホトレジ
スト液を塗布し、結晶表面上にパターンを焼き付
けて、Ｐ型エピタキシヤル層１７からｎ型エピタ
キシヤル層１６を貫いて結晶基板１５にまで達す
る溝１８を形成する。したがつて、この溝１８の
底部には結晶基板１５の表面が露出している。溝
１８は結晶表面の中央に矩形状に２個又は３個以
上形成され、その溝１８で囲まれた内側に隆起状
の発光ダイオード領域１９，１９……を形成す
る。また、この発光ダイオード領域１９，１９…
…間及び結晶表面の周端にも溝１８，１８……が
形成され、発光ダイオード領域１９，１９、……
外の結晶表面にこれらよりも広大な他領域として
の隆起状の非発光ダイオード領域２０，２０，…
…を形成する。溝自体の断面形状は、後述する引
出し配線が横切る方向にあるものでは断線が生じ
ないように特にＶ字形にしてある。 FIG. 1 is a sectional view of a light emitting diode, and FIG. 2 is a plan view thereof. This light emitting diode is constructed as follows. As shown in the figure, an n-type epitaxial layer 16 as a first crystal layer of a conductivity type opposite to that of the substrate 15 is formed on a crystal substrate 15 of one conductivity type, for example, a P-type, by a liquid phase epitaxial growth method. A P-type epitaxial layer 17 as a second crystal layer of the type is simultaneously grown. Next, a photoresist solution is applied and a pattern is baked onto the crystal surface to form a groove 18 that extends from the P-type epitaxial layer 17 to the N-type epitaxial layer 16 and reaches the crystal substrate 15. Therefore, the surface of the crystal substrate 15 is exposed at the bottom of the groove 18. Two or more rectangular grooves 18 are formed in the center of the crystal surface, and raised light emitting diode regions 19, 19, . . . are formed inside the grooves 18. Moreover, these light emitting diode regions 19, 19...
Grooves 18, 18... are formed between... and also at the peripheral edge of the crystal surface, and light emitting diode regions 19, 19,...
On the outer crystal surface there are raised non-light emitting diode regions 20, 20, . . . that are larger than these.
form... The cross-sectional shape of the groove itself is particularly V-shaped so as not to cause disconnection in the direction in which the later-described lead wire crosses.
このように溝１８を形成した後に、溝表面を含
む結晶表面にCVD法により絶縁層２１を形成し
てから、発光ダイオード領域１９を形成している
溝１８の底部全周と、発光ダイオード領域１９の
Ｐ型エピタキシヤル層表面の外周とに、エツチン
グによりコンタクト用のスリツトを設けて金属蒸
着を行い、これらのスリツトに蒸着した金属が残
るようにする。溝１８の底部の露出した基板表面
に残つた金属が発光ダイオード領域１９を囲む第
１電極を構成するマイナス電極２２となる。ま
た、発光ダイオード領域頂部のＰ型エピタキシヤ
ル層表面の外周に残つた金属が発光面２３を囲む
第２の電極を構成するプラス電極２４となる。 After forming the groove 18 in this way, an insulating layer 21 is formed by CVD on the crystal surface including the groove surface, and then the entire bottom of the groove 18 forming the light emitting diode region 19 and Slits for contact are provided by etching on the outer periphery of the surface of the P-type epitaxial layer, and metal vapor deposition is performed so that the vapor-deposited metal remains in these slits. The metal remaining on the substrate surface exposed at the bottom of the groove 18 becomes the negative electrode 22 constituting the first electrode surrounding the light emitting diode region 19. Further, the metal remaining on the outer periphery of the surface of the P-type epitaxial layer at the top of the light emitting diode region becomes the positive electrode 24 constituting the second electrode surrounding the light emitting surface 23.
このようにして、マイナス電極２２と、プラス
電極２４を形成した後、発光ダイオード領域１９
のＶ字形溝１８を横切る一側（図では左側）に溝
底部のマイナス電極２２に接続され、これより溝
１８を伝わつて非発光ダイオード領域２０の頂部
に延びる第１の引出配線２５が既述した絶縁層２
１上に蒸着される。また、この第１の引出配線２
５が蒸着された一側の反対側となる発光ダイオー
ド領域１９の他側に、発光ダイオード領域頂部の
プラス電極２４に接続され、これより予め溝１８
を渡り非発光ダイオード領域２０の頂部に延びる
CVD法により形成された絶縁層２６の上を走る
第２の引出配線２７が蒸着さている。すなわち、
発光ダイオード領域１９の他側に位置する溝１８
内では絶縁層２６を介してマイナス電極２２とプ
ラス電極２４に連なる第２の引出線２７は２層構
造となつている。 After forming the negative electrode 22 and the positive electrode 24 in this way, the light emitting diode region 19
The first lead wiring 25 is connected to the negative electrode 22 at the bottom of the groove on one side (left side in the figure) across the V-shaped groove 18 and extends from this through the groove 18 to the top of the non-light emitting diode region 20. Insulating layer 2
1. In addition, this first lead wiring 2
The groove 18 is connected to the positive electrode 24 at the top of the light emitting diode region on the other side of the light emitting diode region 19, which is opposite to the one side on which the light emitting diode region 5 is deposited.
and extends to the top of the non-light emitting diode region 20.
A second lead wire 27 running on the insulating layer 26 formed by the CVD method is deposited. That is,
Groove 18 located on the other side of light emitting diode region 19
Inside, the second lead wire 27 connected to the negative electrode 22 and the positive electrode 24 via the insulating layer 26 has a two-layer structure.
このようにして形成された第１及び第２の引出
配線２５，２７は隣り合う非発光ダイオード領域
２０，２０から延びる第１及び第２の引出線２
５，２７同志とそれぞれ接続されるとともに発光
ダイオード領域１９，１９，……ではない非発光
ダイオード領域２０，２０，……上の任意の２箇
所でそれそれリード線とボンデイングされて、並
列接続されたダイオードアレイ、即ち、本考案の
発光ダイオードが完成する。 The first and second lead wires 25 and 27 formed in this way are the first and second lead wires 2 extending from the adjacent non-light emitting diode regions 20 and 20.
5 and 27, respectively, and are bonded to lead wires at any two locations on the non-light emitting diode regions 20, 20, . . . , not the light emitting diode regions 19, 19, . The diode array, ie, the light emitting diode of the present invention, is completed.
さて、上記のような構成において、リード線を
介してマイナス電極２２に負、プラス電極２４に
正の電圧を印加すると、電流がプラス電極２４か
ら入り、PN接合を経由し、結晶基板１５の表面
を通つてマイナス電極２２から出ていくことによ
り発光面２３が発光する。この場合において、正
負のリード線が発光ダイオード領域１９上の小面
積のプラス電極２４や基板１５上の小面積のマイ
ナス電極２２にではなく、非発光ダイオード領域
２０，２０上の大面積の第１及び第２の引出配線
２５，２７に各１本ボンデイングされているだけ
なので、ボンデイングを安定且つ確実に行え、リ
ード線が外れたり、焼き切れたりすることがな
い。また、発光面の数だけボンデイングされてい
るものとは異なり、１つの発光ダイオード内にお
ける接触抵抗のバラツキは生じ得ない。したがつ
て、接触抵抗に起因する発光強度のバラツキも生
じない。なお、発光ダイオード領域１９，１９，
……上ではボンデイングされないので、これらを
ボンデイング圧力から保護でき、また電極２２，
２４上でボンデイングされないので、これらの形
状が損なわれず、発光ダイオード内のすべての電
極形状の同一性が保てる。更に、各電極２２，２
４はそれぞれ共通の第１及び第２の引出配線２
５，２７に共通接続されているので、ボンデイン
グが２箇所で足りボンデイング作業が極めて容易
となる。 Now, in the above configuration, when a negative voltage is applied to the negative electrode 22 and a positive voltage is applied to the positive electrode 24 via the lead wire, a current enters from the positive electrode 24 and flows through the PN junction to the surface of the crystal substrate 15. The light emitting surface 23 emits light by exiting from the negative electrode 22 through. In this case, the positive and negative lead wires are connected not to the small-area positive electrode 24 on the light-emitting diode region 19 or the small-area negative electrode 22 on the substrate 15, but to the large-area first electrode on the non-light-emitting diode regions 20, 20. Since only one lead wire is bonded to each of the second lead wires 25 and 27, bonding can be performed stably and reliably, and the lead wires will not come off or burn out. Further, unlike the case where bonding is performed by the number of light emitting surfaces, variations in contact resistance within one light emitting diode cannot occur. Therefore, variations in luminous intensity due to contact resistance do not occur. Note that the light emitting diode regions 19, 19,
... Since they are not bonded on the top, these can be protected from bonding pressure, and the electrodes 22,
Since bonding is not performed on the light emitting diode 24, these shapes are not damaged, and the same shape of all electrodes in the light emitting diode can be maintained. Furthermore, each electrode 22,2
4 are the common first and second lead wires 2
5 and 27, bonding only needs to be done at two locations, making the bonding work extremely easy.
一方、プラス電極２４が発光面２３を囲むよう
に設けられているため、光子の放出に対して影を
作ることなく、PN接合面全面にわたつて均一な
電流が流れる。このとき、発光ダイオード領域１
９が絶縁層２６で覆われPN接合面が露出してい
ないので、漏れ電流も流れない。また、PN接合
面を通過した電流は結晶基板１５の厚さ方向を横
切るのではなく、結晶基板１５の表面を横切るだ
けであり、しかも発光ダイオード領域１９の直ぐ
近くの底面を囲つたマイナス電極２２へ流れるの
で、結晶基板抵抗に影響されず、各発光ダイオー
ド領域１９，１９，……間での電流バラツキも生
じない。したがつて、基板抵抗に起因する発光強
度のバラツキを可及的に低減することができる。 On the other hand, since the positive electrode 24 is provided so as to surround the light emitting surface 23, a uniform current flows over the entire PN junction surface without creating a shadow on the emission of photons. At this time, the light emitting diode area 1
9 is covered with the insulating layer 26 and the PN junction surface is not exposed, so no leakage current flows. Further, the current passing through the PN junction surface does not cross the thickness direction of the crystal substrate 15, but only crosses the surface of the crystal substrate 15, and moreover, the current passes through the negative electrode 22 surrounding the bottom surface immediately near the light emitting diode region 19. Therefore, it is not affected by the crystal substrate resistance, and no current variation occurs between the light emitting diode regions 19, 19, . . . . Therefore, variations in light emission intensity due to substrate resistance can be reduced as much as possible.
このように本実施例によれば、各発光面２３，
２３、……間で均一な発光強度を得ることができ
る。 As described above, according to this embodiment, each light emitting surface 23,
23, uniform luminescence intensity can be obtained between...
なお、上記実施例で述べた発光ダイオードの材
料としては、目的とする波長に合せて、
GaAsP，GaAAs，GaP，InP，InGaAs等いず
れも使用ができ、また、エポキシ樹脂、メタクリ
ル樹脂、アクリル樹脂等の透明性の良好な樹脂で
表面をコートすることにより、光子の内部吸収を
低減して製品価値を高めることは勿論である。 Note that as the material for the light emitting diode described in the above embodiment, GaAsP, GaAAs, GaP, InP, InGaAs, etc. can be used depending on the desired wavelength, and epoxy resin, methacrylic resin, acrylic resin, etc. Of course, by coating the surface with a highly transparent resin, internal absorption of photons can be reduced and product value can be increased.
また、上記実施例では隆起状の非発光ダイオー
ド領域２０，２０，……上の第１及び第２の引出
配線を設けるようにしたが、この非発光ダイオー
ド領域２０をもエツチングにより除去し、この除
去により露出した基板１５の表面に第１及び第２
の引出配線２５，２７を設けるようにしてもよ
い。 Further, in the above embodiment, the first and second lead wirings were provided above the raised non-light emitting diode regions 20, 20, . The first and second
The lead wirings 25 and 27 may be provided.
更に、プラス電極２４の形状は使用目的に応じ
て、長方形、正方形、円形等任意であるが、発光
面２３内から均一に発光するように考慮されるべ
きである。 Furthermore, the shape of the positive electrode 24 may be arbitrary, such as rectangular, square, or circular, depending on the purpose of use, but consideration should be given to uniformly emitting light from within the light emitting surface 23.
ここで、上記実施例にもとづいて行つた実施例
について説明する。 Here, an example based on the above example will be described.
実施例：
Ｐ型GaAs基板上にｎ型GA0.7Ａ 0.3As，Ｐ型
Ga0.7 0.3 Asをそれぞれ4μmと2μm厚となる
よう液相エピタキシヤル成長法で成長させ、４mm
×1.6mm角のチツプ中にフオトマスクを使用して
16個の発光ダイオード領域を形成し、第１図及び
第２図に示す発光ダイオードを作成した。なお、
絶縁層としてはPSG膜を用い、またｎ型電極と
してAu−Ge／Ni／Au，Ｐ型電極としてAu−
Zn／Ni／Auをそれぞれ使用した。Example: n-type GA 0.7 A 0.3 As on P-type GaAs substrate, P-type
Ga 0.7 0.3 As was grown using the liquid phase epitaxial growth method to a thickness of 4 μm and 2 μm, respectively.
Using a photo mask inside a 1.6mm square chip
Sixteen light emitting diode regions were formed to produce the light emitting diodes shown in FIGS. 1 and 2. In addition,
A PSG film was used as the insulating layer, Au-Ge/Ni/Au was used as the n-type electrode, and Au-Ge/Ni/Au was used as the P-type electrode.
Zn/Ni/Au were used, respectively.
このようにして得られた発光ダイオードの電極
間に３Ｖ印加したところ、16個の発光ダイオード
領域の全部が赤色の発光をし、発光強度は全て20
±2mWと均一であつた。 When 3V was applied between the electrodes of the light emitting diode obtained in this way, all 16 light emitting diode areas emitted red light, and the emission intensity was 20.
It was uniform at ±2mW.
［考案の効果］
以上要するに本考案によれば次のような優れた
効果を発揮する。[Effects of the invention] In summary, the present invention provides the following excellent effects.
隆起状の発光ダイオード領域の底部にこれを
囲む第１の電極を、また発光ダイオード領域の
頂部に発光面を囲む第２の電極を設けたことに
より、各接合面における電流密度ないしは電極
間の抵抗値を一定にすることができ、発光ダイ
オード長が大きくなつても発光面の位置による
発光強度のバラツキを抑え、各発光面の発光強
度を可及的に均一化することができる。 By providing a first electrode surrounding the bottom of the raised light emitting diode region and a second electrode surrounding the light emitting surface at the top of the light emitting diode region, the current density at each junction surface or the resistance between the electrodes can be reduced. The value can be made constant, and even if the length of the light emitting diode becomes large, variations in the light emitting intensity depending on the position of the light emitting surface can be suppressed, and the light emitting intensity of each light emitting surface can be made as uniform as possible.
各電極同士を蒸着した金属配線で接続し、こ
の金属配線にリード線をボンデイングできるの
で、電極形状を損うことなく、かつボンデイン
グ工数を低減できる。 Since the electrodes are connected to each other by vapor-deposited metal wiring and lead wires can be bonded to the metal wiring, the electrode shape can be maintained and the number of bonding steps can be reduced.
第１図は本考案による発光ダイオードの一実施
例を示す横断面図、第２図は第１図に示す発光ダ
イオードの平面図、第３図及び第４図は従来の発
光ダイオードを示す縦断面図である。
図中、１５は結晶基板、１６は第１結晶層とし
てのＮ型エピタキシヤル層、１７は第２結晶層と
してのＰ型エピタキシヤル層、１８は溝、１９は
発光ダイオード領域、２０は他領域としての非発
光ダイオード領域、２１，２６は絶縁層、２２は
第１の電極としてのマイナス電極、２３は発光
面、２４は第２の電極としてのプラス電極、２５
は第１の引出配線、２７は第２の引出配線であ
る。
FIG. 1 is a cross-sectional view showing an embodiment of the light-emitting diode according to the present invention, FIG. 2 is a plan view of the light-emitting diode shown in FIG. 1, and FIGS. 3 and 4 are vertical cross-sections showing a conventional light-emitting diode. It is a diagram. In the figure, 15 is a crystal substrate, 16 is an N-type epitaxial layer as a first crystal layer, 17 is a P-type epitaxial layer as a second crystal layer, 18 is a groove, 19 is a light emitting diode region, and 20 is another region. 21 and 26 are insulating layers, 22 is a negative electrode as a first electrode, 23 is a light emitting surface, 24 is a positive electrode as a second electrode, 25
27 is a first lead wiring, and 27 is a second lead wiring.
Claims (1)
発光面を有する発光ダイオードにおいて、上記
結晶基板の表面にこれと反対導電型の第１結晶
層と、さらにこの第１結晶層表面に上記結晶基
板と同じ導電型の第２結晶層を形成し、この第
２結晶層に上記結晶基板表面を露出させて隆起
状の発光ダイオード領域を形成する溝を設け、
この溝の底部の露出した基板表面に上記発光ダ
イオード領域を囲む第１の電極を、また上記発
光ダイオード領域の第２の結晶層表面に発光面
を囲む第２の電極をそれぞれ設けたことを特徴
とする発光ダイオード。 (2) 上記溝がＶ字形溝であることを特徴する実用
新案登録請求の範囲第１項記載の発光ダイオー
ド。 (3) 上記第１及び第２の電極が、上記発光ダイオ
ード領域外の他領域に絶縁分離して設けた第１
及び第２の引出配線にそれぞれ接続されている
ことを特徴とする実用新案登録請求の範囲第１
項又は第２項記載の発光ダイオード。[Claims for Utility Model Registration] (1) In a light emitting diode having two or more light emitting surfaces on a crystal substrate of one conductivity type, a first crystal layer of the opposite conductivity type is provided on the surface of the crystal substrate. Further, a second crystal layer of the same conductivity type as the crystal substrate is formed on the surface of the first crystal layer, and a groove is formed in the second crystal layer to expose the surface of the crystal substrate to form a raised light emitting diode region. established,
A first electrode surrounding the light emitting diode region is provided on the substrate surface exposed at the bottom of the groove, and a second electrode surrounding the light emitting surface is provided on the surface of the second crystal layer of the light emitting diode region. light emitting diode. (2) The light emitting diode according to claim 1, wherein the groove is a V-shaped groove. (3) The first and second electrodes are connected to a first electrode provided insulated and separated in a region other than the light emitting diode region.
and the second lead-out wiring, respectively.
The light emitting diode according to item 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984196017U JPH0349406Y2 (en) | 1984-12-26 | 1984-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984196017U JPH0349406Y2 (en) | 1984-12-26 | 1984-12-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112661U JPS61112661U (en) | 1986-07-16 |
| JPH0349406Y2 true JPH0349406Y2 (en) | 1991-10-22 |
Family
ID=30753656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984196017U Expired JPH0349406Y2 (en) | 1984-12-26 | 1984-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0349406Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307218B1 (en) * | 1998-11-20 | 2001-10-23 | Lumileds Lighting, U.S., Llc | Electrode structures for light emitting devices |
-
1984
- 1984-12-26 JP JP1984196017U patent/JPH0349406Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61112661U (en) | 1986-07-16 |
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