JPH0348978A - Bus arbitrating device for picture memory device - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of a picture memory bus by measuring the time required for a drawing controller to arbitrate the picture memory bus and granting the use of the bus before the measurement of the time is through. CONSTITUTION:A strobe signal (a) is set at a low level based on a request given from a host CPU for use of a picture memory bus 5. Thus a control circuit 2 sets an access request signal (b) synchronized with the rise of a clock signal CK at a low level. Then a request is given to a drawing controller 1 for use of the bus 5. The controller 1 sets an acknowledge signal (c) at a low level after a proper arbitrating time. Hereafter the host CPU can occupy the bus 5 and give an access to a picture memory. As a result, the accessible time rate is improved for the host CPU to the picture memory. Then the system through put is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to image memory devices in personal computers, workstations, etc., and in particular, the present invention relates to image memory devices in personal computers, workstations, etc. The present invention relates to a bus arbitration device.

<Prior Art> For example, in a workstation or the like, a host CPU uses a drawing controller LSI, which is a graphics processor, to access an image memory and perform predetermined drawing. This drawing controller has a function of arbitrating requests from others for the use of the image memory bus. For example, when there is a request for the use of the image memory bus from the host CPU, the drawing controller adjusts the use of the image memory bus after an appropriate arbitration time has elapsed. The image memory bus is permitted to be used by outputting a consent signal for consenting to its use. When the drawing controller accesses the image memory again, the permission signal is turned off at an appropriate timing to prohibit the host CPU from using the image memory, and after the arbitration time has elapsed, the drawing controller starts accessing the image memory. .

<Problems to be Solved by the Invention> However, as the performance of the host CPU increases and its processing speed increases, the time it takes for the host CPU to arbitrate the image memory bus by the drawing controller becomes quite long, resulting in wasted time. In addition, the utilization efficiency of the image memory bus is not sufficient. For this reason, there is a strong demand for increasing the percentage of time that the host CPU can access the image memory, but no effective method has been proposed at present.

This invention focuses on the fact that the image memory bus arbitration time by the drawing controller is longer than the image memory access time by the CPU, and by making it possible to access the image memory from other devices during this arbitration time, one image memory bus An object of the present invention is to provide a new bus arbitration device for an image memory device that can maximize the usage efficiency of the image memory and increase the percentage of time that the image memory can be accessed by a host CPU.

Means for Solving the Problems In order to achieve the above object, the present invention includes a drawing controller that has a function of arbitrating requests for the use of the image memory bus. In an image memory device configured to permit use of an image memory bus by outputting a consent signal, a method for measuring the time required for a drawing controller to arbitrate the image memory bus after the consent signal is turned off. A bus arbitration device is constituted by a clock section and a signal generation section that generates a signal to permit use of the image memory bus for the time taken until the measurement by the clock section is completed.

<Operation> When there is a request from the CPU for use of the image memory bus, the drawing controller outputs a consent signal to approve the use of the image memory bus after the arbitration time has elapsed, thereby permitting use of the image memory bus. After that, when the drawing controller starts accessing the image memory, the consent signal is turned off, and the timer measures the time required for the image memory bus to be arbitrated by the drawing controller. The time until the measurement by the clock unit is completed is determined by the signal generation unit generating and outputting a signal to permit the use of the image memory bus, and the host C
Enables the PU to access the image memory. This maximizes the utilization efficiency of the image memory bus and increases the percentage of time during which the image memory can be accessed by the host CPU.

<Embodiment> FIGS. 1 and 2 show an example of a circuit configuration of a bus arbitration device for an image memory device according to an embodiment of the present invention, and FIG. 3 shows a time chart thereof.

The bus arbitration device shown in FIG. 1 includes a drawing controller 1. Control circuit 22 oscillator 3. It includes a buffer circuit 4 and the like, and the drawing controller 1 is connected to an image memory (not shown) via an image memory bus 5.

The drawing controller 1 is a general-purpose drawing LSI (for example, Japan A
rAm95C60J manufactured by DM), in addition to the function of accessing the image memory via the image memory bus 5, it also has the function of arbitrating requests from a host CPU (not shown) etc. regarding the use of the image memory bus 5. We are prepared.

The control circuit 2 is connected from the host CPU to the host CPU.
When a strobe signal a requesting use of the image memory bus 5 is input through the bus 6, the strobe signal a is synchronized with the clock signal C to generate an access request signal S, which is output to the drawing controller l.

Note that the host CPU is a 32-pin 1-class CPU capable of high-speed data transfer, such as Motorola's R
Mc68030'' etc. are used.

When the drawing controller 1 receives the access request signal and outputs a signal (hereinafter referred to as "approval signal") C for consenting to the use of the image memory bus 5 to the control circuit 2,
The control circuit 2 outputs a permission signal d to the buffer circuit 4 for permission to use the image memory bus 5 by the host CPU. The buffer circuit 4 is a host CPU.
It is interposed between bus 6 and image memory bus 5 and functions as a bidirectional gate.

In FIG. 1, an oscillator 3 is used to supply a clock signal CK to the control circuit 2 and the drawing controller 1, and all signals except the strobe signal a change in synchronization with the rise of this clock signal CK. .

FIG. 2 shows a specific example of the control circuit 2, which includes a clock section 7 and a signal generation section 8. As shown in FIG.

The time measurement section 7 includes a plurality of (n) flip-flops F.
It is constituted by an up counter 9 formed by connecting 0 stages of F, to FF. This up counter 9 is for measuring the arbitration time by the drawing controller 1 after the consent signal C is turned off, and counts up in synchronization with the input of the clock signal CK immediately after the consent signal C is turned off. . In addition, in Fig. 2, each stage of flip-flop FFI~
In the FF, D indicates data input, Q indicates Q (positive) output, and R indicates reset input, and the data input of the first stage flip-flop FF is pulled up.
Flip-flop FF from 2nd stage onwards! The Q output of the previous stage flip-flop is given to the data input of ~FF,
Further, a consent signal C is given to the manual reset π of each stage of flip-flops FF, -FF.

The signal generation section 8 includes an AND gate 10 and a buffer gate 1
1. The AND gate 10 generates the permission signal d by ANDing the Q output of the final stage flip-flop FF and the permission signal C. In this embodiment, when 8 clock cycles are counted for the arbitration time of 9 clock cycles, the final stage flip-flop FF rises and the permission signal d is output. Note that the expansion gate 11 synchronizes the strobe signal a with the clock signal CK to generate an access request signal S.

Next, the circuit operation will be explained based on the time chart shown in FIG.

Now, when the strobe signal a goes to the LOW level based on a request from the host CPU to use the image memory bus 5, the control circuit 2 sets the access request signal a to the LOW level in synchronization with the rise of the clock signal GK. None, requests the drawing controller 1 to use the image memory bus 5.

When the drawing controller 1 sets the consent signal C to the "LOW" level after an appropriate arbitration time has elapsed, from this time on,
The (host) CPU can occupy the image memory bus 5 and access the image memory.

Thus, at time T in FIG. 3, the drawing controller 1 executes a drawing memory cycle that takes priority over others.
The consent signal C is returned to the "HIGH" level. The rising time of this consent signal C is T.

Assuming that the time width of 9 clock cycles between times T and T is the arbitration time guaranteed by the drawing controller l, one memory access cycle t2 of the host CPU
Since Lx is shorter than the arbitration time t (Lx<t), the image memory can be accessed by the host CPU during this time.

In such a system, since the access time of the image memory by the host CPU can be specified by the system as a fixed time, new memory accesses by the host CPU are allowed until the limit time when the system does not malfunction under critical operating conditions. This maximizes the utilization efficiency of the image memory bus 5.

<Effects of the Invention> As described above, the present invention measures the time required for the drawing controller to arbitrate the image memory bus after the consent signal for consenting to use of the image memory bus is turned off, and waits until this measurement is completed. Since the image memory bus is allowed to be used for every hour, the efficiency of image memory bus usage is maximized, increasing the percentage of time when image memory can be accessed by the host CPU, and improving system throughput. The invention has a remarkable effect of achieving the purpose of the invention.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a bus arbitration device for an image memory device according to an embodiment of the present invention, FIG. 2 is an electric circuit diagram showing a specific example of a control circuit, and FIG. 3 is a diagram similar to FIGS. 1 and 2. 2 is a time chart of the circuit shown in FIG. 1... Drawing controller 2... Control circuit 5... Image memory bus

Claims (1)

[Scope of Claims] A drawing controller is provided which has a function of arbitrating requests for use of the image memory bus, and the drawing controller outputs a consent signal for consenting to the use of the image memory bus, thereby requesting use of the image memory bus. In the image memory device that is configured to allow permission, there is provided a timer for measuring the time required for the drawing controller to arbitrate the image memory bus after the consent signal is turned off, and a time until the measurement by the timer completes the measurement. 1. A bus arbitration device for an image memory device, comprising: a signal generation unit that generates a signal for permitting use of an image memory bus.