JPH0348658Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an initialization circuit for initializing a digital circuit, and particularly to an initialization circuit that generates an initialization signal suitable for initializing a digital circuit constructed of CMOS.

In general, digital circuits require initial circuit conditions to be set when power is turned on, and an initialization circuit is provided that generates an initialization pulse in synchronization with power-on.

Conventionally, this initialization circuit uses a resistor and a capacitor, and is configured to generate an initialization pulse with a pulse width determined by the time constants of the resistors and capacitors.

An object of the present invention is to provide an initialization circuit that can generate an initialization signal without using such resistors or capacitors.

In order to achieve the above object, an initialization circuit according to the present invention includes a power supply control section to which a normal power supply is applied, which controls a semiconductor switch, connects an arithmetic control section to a power supply, and initializes the arithmetic control section. It is provided in the power supply control unit and is set by an external activation input, and is reset by a signal from the calculation control unit when a predetermined calculation control is completed or a predetermined time has elapsed. a first flip-flop, a counter which is connected to a clock from the arithmetic control unit via a gate and starts counting the clock after the first flip-flop is set; The output of the second flip-flop and the output of the first flip-flop are connected to each other, and when the first flip-flop is in the set state, the counter is initialized to the arithmetic control section until it reaches a predetermined count. The semiconductor switch 3 is provided with a gate circuit for providing a signal, and when the first flip-flop is in a reset state, the semiconductor switch 3 provides a reset signal to the counter and the second flip-flop to initialize them and to control the power supply of the arithmetic control section. is turned off, and when the first flip-flop is in the set state, the reset signal applied to the counter and the second flip-flop is released, the semiconductor switch is turned on, and the arithmetic control unit waits for an external input. The device is configured to generate a signal that creates a state.

According to the above configuration, the purpose of the present invention can be completely achieved.

The present invention will be described in more detail below with reference to the drawings and the like. FIG. 1 is a block diagram of a digital circuit to which an initialization circuit according to the present invention is applied. In FIG. 1, switch SW _o is a switch for turning on the power, and when SW _o is turned on, the power control section 1 turns on the switch transistor 3 and connects the arithmetic control section 2 to the power supply 4 . At the same time, the power supply control section 1 sends an initialization signal to the calculation control section 2. Switch SW _n is an input switch for arithmetic control commands. Here, power is always applied to the power supply control section 1, but it is in a static state in which the logic level does not change until the switch SW _o is turned on, so if it has a CMOS configuration, no current is consumed.

FIG. 2 is a circuit diagram showing a detailed embodiment of the power supply control section, FIG. 3 is a circuit diagram showing a detailed embodiment of the input section, and FIG. 4 is a waveform diagram for explaining the operation of the initialization circuit. It is.

In FIG. 2, switches SW _o and SW ₂ are power switches corresponding to SW _o in FIG. 1. switch
SW ₁ is a switch that, once turned on, turns on the switch transistor 3 for a period determined by the arithmetic control circuit 2 to maintain power hold. The switch _SW2 is a switch for turning on the switch transistor 3 only while the switch is on. R ₁ and R ₂ are pull-up resistors, F ₁
is a reset flip-flop. _F2
is a flip-flop that transfers the data at the D input to the output at the rising edge of the clock input to the input terminal. RES ₁ is a reset signal for counter 11 and F ₂ , RES ₂ is a reset signal for F ₁ , PHS is F ₁
CLK is the clock signal to the counter 11. _Io is an initialization signal, which initializes the counter, flip-flop, etc. of the arithmetic control circuit 2. Switches SW ₃ and SW ₄ are control switches for arithmetic control commands corresponding to switch SW _n shown in FIG. The input section is provided with P channel FETs, P1 and P2, as shown in FIG. The gates of these FETs are controlled by PH (power hold signal) and form pull-up resistors for switches SW ₃ and SW ₄ . Diodes D1 and D2 are input protection diodes for the arithmetic control circuit.

When PH=H, that is, power off, each FET
The gate of is at high level and FET, P1, P2 are in off state, and V _DD is passed through P1 or P2.
Prevents current from flowing to ground GND through SW ₃ or SW ₄ . Therefore, in the power-off state, no current flows even if SW ₃ and SW ₄ are in the on state. When PH=L, that is, in the power-on state, the gate is at low level, and P1,
P2 becomes active (e.g. conduction resistance
(100kΩ) serves as a pull-up resistor for SW ₃ and SW ₄ , and the states of switches SW ₃ and SW ₄ are sent to the calculation control unit 2.

Before power-on switch _SW1 or _SW2 is turned on, switch transistor 3 is non-conductive, so RES2=H, PHS=H, that is, F1 is reset, and F1's output PH=L, RES1=H. Counters 11 and F2 have already been reset. Further, the gate G1 is closed and CLK=L. As a result, the circuit configured with CMOS does not switch even if power is always applied to the power control section 2.
Since it is in a static state until SW ₁ and SW ₂ are turned on, it does not consume current. When the switch _SW1 is turned on, F1 is set and PH=H, the switch transistor 3 becomes conductive and power is applied to the arithmetic control section 2. At the same time, the reset of the counter 11 and F2 is released, and the initialization signal _Io becomes H using the gate G2, and the arithmetic control circuit 2
By initializing the arithmetic control circuit 2 that initializes the
RES2=L, PHS=L by detection of SW ₁
and sends a set signal to F1. Also, the gate of the P channel FET in the input section is at L level.
P1 and P2 become pull-up resistors, and switch SW ₃ ,
The state of SW ₄ is sent to the arithmetic control circuit 2.

Gate G1 opens due to PH=H and counter 11
starts counting the input clock CLK. When the counter 11 counts a predetermined input clock, CT
=H and sends a pulse to F2, Q =L and gate G2 closes I _o =L and initialization is completed.
The calculation control circuit 2 starts calculation. When the arithmetic control circuit finishes predetermined arithmetic control or reaches a predetermined time, PHS becomes H and the set signal of F1 is released, and F1 is reset by the pulse of RES2. By resetting F1, PH=L, switch transistor 3 is turned off, RHS2=H,
RES=H is maintained, the counters 11 and F2 are reset, and the input sections P1 and P2 become non-conductive, returning to the state before turning on the switch _SW1 .

In this way, in the present invention, before the power supply controller to which power is constantly applied is turned on the power supply switch, the reset signal is applied to reset the flip-flop and the counter 11 and the unit is in a static state. When input, an initialization signal is generated and the arithmetic control section is initialized. Since the pulse width of the initialization signal can be arbitrarily determined by the count number of the counter 11,
For example, by inserting a capacitor with a large capacitance into the arithmetic control section 2 to prevent noise, even if the power supply to the arithmetic control section 2 does not start up properly, initialization can be performed reliably. Further, since the counter 11 is always given a reset signal before the power supply switch is turned on, it can always start from the same state.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a digital circuit in which the initialization circuit according to the present invention is installed in the power supply control section.
FIG. 2 is a circuit diagram showing in detail an embodiment of the power supply control section of the digital circuit, FIG. 3 is a circuit diagram showing an embodiment of the input section, and FIG. 4 is a waveform diagram for explaining the operation. . 1: Power supply control section, 2: Arithmetic control section, 3: Switch transistor, 4: Power supply battery, 5: Input section, 1
1: Counter, SW _o (SW ₁ , SW ₂ ): Power on switch, SW _n (SW ₃ , SW ₄ ): Signal input switch.

Claims (1)

[Claims for Utility Model Registration] In an initialization circuit including a power supply control unit to which a normal power supply is applied, which controls a semiconductor switch, connects an arithmetic control unit to the power supply, and initializes the power supply control unit, the power supply control unit includes: a first flip-flop that is set by an external activation input and reset by a signal from the arithmetic control unit when the arithmetic control unit finishes a predetermined arithmetic control or a predetermined time elapses; a counter to which a clock from the arithmetic control unit is connected via a gate and starts counting the clock after the first flip-flop is set; and a second counter that is changed with respect to a predetermined count of the counter. an output of the flip-flop and an output of the first flip-flop are connected, and when the first flip-flop is in a set state, a gate circuit provides an initialization signal to the arithmetic control section until the counter reaches a predetermined count. and when the first flip-flop is in a reset state, a reset signal is given to the counter and the second flip-flop to initialize them, and the semiconductor switch 3, which controls the power supply of the arithmetic control section, is turned off; When the first flip-flop is in the set state, the reset signal applied to the counter and the second flip-flop is released, the semiconductor switch is turned on, and a signal is sent to the arithmetic control section to form an external input standby state. An initialization circuit characterized in that the initialization circuit is configured to generate a signal.