JPH0348436A - High frequency semiconductor device - Google Patents
High frequency semiconductor deviceInfo
- Publication number
- JPH0348436A JPH0348436A JP10128190A JP10128190A JPH0348436A JP H0348436 A JPH0348436 A JP H0348436A JP 10128190 A JP10128190 A JP 10128190A JP 10128190 A JP10128190 A JP 10128190A JP H0348436 A JPH0348436 A JP H0348436A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- electrode
- flexible film
- high frequency
- frequency semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000919 ceramic Substances 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 15
- 239000010931 gold Substances 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明｛上 優れた高周波特性を与える半導体実装に係
も
従来の技術
３ＧＨｚ以上の高周波トランジスタ特にＧａＡｓＦＥＴ
チップ１００は第５図に示すようなアルミナセラミック
１０ｌをペース素材としたパッケージに封止されも１０
３はボンディングワイヤ、１０３Ａ． １０３Ｂ， １
０３ＣはＡｕメッキ層見 それぞれドレンリード１０４
．ソースリードｌ０５，ゲートリード１０６が接続され
てい４ １０７はセラミックのふたであん このよう
なパッケージとしてＧａＡｓＦＥＴを組立てる時の組立
フローチャートの一例を第６図に示机 ま哄 所定の厚
さに研鳳整形したＧａＡｓウエハーの裏面に ダイスボ
ンド用ろう材（半田）接着のためｌ，＝ Ａｕなどの
メタライズを行う。次に これをチップ毎に切断し ブ
レークすム 次＋．：， １個１個のチップをＡｕ／
Ｓｎ半田などのろう材を用いてＡｕメッキ層１０３Ｂに
ダイスボンドすム この後でボレデイングワイヤ１０２
Ｓ， １０２Ｄ，１０２Ｇでワイヤボンドすも このと
き、ソースインダクタンスをできる限り小さくすること
爪 高周波特怯 特に雑音指数（Ｆ），利得（ Ｇａ）
を良くするために大切であん このたべ ソースのボン
デイングワイヤ１ ０２Ｓの長さをできる限り短くした
り、本数を増やしたり（第５図では４本）していも ワ
イヤボンディングの眞 キャップ（ふたｌ０７）を接着
すも
発明が解決しようとする課題
ところ玄 近亀 マイクロ波半導体パッケージのコスト
ダウン要望力ｔ 半導体チップのコストダウンだけでは
吸収しきれない程大きく、組立 実装コストの低減が切
望されていも そして、マイクロ波パッケージの中には
組立 実装コストが全優格の半分程度を占めるものか
あも しかし従来のセラミックパッケージを使用する限
りはコストダウンに限界がありｔ４ また さらに一
層の高性能化に対する要望も大きく、チップだけの改善
では限界があり、実装面からの改善が必要であも たと
えば前述ソースワイヤの長さを短くするために セラミ
ックパッケージの電極上にバンプを形成し チップ上の
パッドを対向させて接着するいわゆるフリップボンド方
式バ パワ一ＦＥＴで周知であん しかし この方法Ｃ
上 性能は向上するがセラミックパッケージを使用し
ており、高価なセラミック本体上にバンプを形或すると
いうプロセスが必要となり、いぜんとして高価であり、
低コスト化という方向とは相反すん 本発明ｇ１ か
かる不都合に鑑みてなされたもので、極めてすぐれた高
周波特性を低コストで実現するパッケージを得ることを
目的とすも
課題を解決するための手段
本発明の高周波半導体装置１よ フレキシブルフィルム
の片面上に金属電極パターンを設《ナ、前記電極パター
ンの一部に複数のバンプを形成し 高周波半導体素子の
複数の電極パッドと前記バンプを対向させて接着したも
のであり、そのとき複数のバンプの間のフレキシブルフ
ィルム上に凹みを設け、あるいはまた望ましくはフレキ
シブルフィルム上に設けられた凹みの表面の一部を、電
極パッドと接続される金属電極パターンでおおったもの
であム また 本発明（上 入出力間にシールド板が存
在するリードフレームの片面の一部にバンプを形＃ｔ，
ｔＡ たとえｌ．ｃ ３ＧＨｚ以上で使用する高周
波半導体素子の複数の電極パッドと前記バンプを対向さ
せて接着するとともにリードフレームと素子間に空隙を
設εナ、しかる抵 前記半導体装置を封止し しかる檄
前記フレームの一部を切断してリードを形成するもの
であも
作用
本発明によれ（Ｌ 高周波半導体チップを通常とは逆の
裏向きにして金属パターン上に接着するいわゆるフリッ
プボンド方式を、フィルムキャリア上で行うことができ
も そして、金属突起（バンプ）を用いるた△ 従来の
ワイヤボンディングエ程が省略できるばかりでなく、高
周波特性に悪い影響を与える素子のソースインダクタン
スを小さく抑えることができも また フイルムキャリ
アを使うとともに ここにバンプを形或するたべセラミ
ックパッケージに比べ大幅に低コスト化が達成できも
また セラミックパッケージに比べ浮遊容量を小さく抑
えることができ、高性能化に極めて有利であも また
本発明によれ（Ｌ 高周波トランジスタで特に問題とな
る入 出力間の分離において、凹みによる空気分離を行
うことにより、アイソレーション性能を大きく向上させ
ることが可能となん さらにまた 本発明はフィルムキ
ャリアリード又はリードフレームにバンプを形成し し
かるのち封止してリードとする方法を用いることにより
、低コストのパッケージを得ることが可能となん
実施例
本発明の実施例を、図面により説明すも 第ｌ図に示す
フレキシブルフィルム３０（ポリイミド・フィルム）の
主面側に 第ｌ図（ａ）に示すように金属パターンより
なる電極リード３２を形或し 次に 転写バンプ等の手
法により、電極リード３２上の必要な部分に金バンプ３
４を形成すも 例えば本実施例で（上 高周波半導体素
子として３ＧＨｚ以上の信号を処理するＧａＡｓＦＥＴ
３１のチップのボンディングパッドに合わせて、 リー
ド３２上にバンプ３４が形成されていも 転写バンプに
よるバンプの形成方法はま哄 ガラス板（図示せず）上
にバンプを形成Ｌ このバンプを金属リード３２上に接
合し バンプをガラス基板からはくリさせて転写するこ
とによって行えばよ鶏 但し バンプの形或は必ずしも
転写バンプ法でなくても良く、 リード３２に他の方法
でバンプ３４を形戊しても良Ｌ〜 半導体チップである
ＦＥＴ３１はパターンリード３２のバレプ３４ＦＥＴ３
１の電極パッドを認識して位置決めをし 一括ボンディ
ングすモ３５はバレブの間のフレキシブルフィルム３０
に形成した空隙部（凹部）であも な耘第１図（ａ）で
はセラミックのふた３６は省略していもまた第１図のリ
ード３２においてＳはソースリード、Ｂはドイレンすな
わち出力リーに Ｇはゲートすなわち入力リードであん
本発明Ｑ バンプ３４付近の拡大斜視図を第２図に示
す。この金属パターン３２の上に形或する金バンプ３４
の高さ及び径（上本実施例では５０〜１００μｍ，５０
μ鵬φとしｔ４ バンプの高さはある程度以上に高く
ないとＧａＡｓチップ３１と金属リードの間の寄生容量
が大きくなってしまい特性が劣化すも 本実施例で１友
高価な高周波半導体素子側にバンプを形或する必要が
なく、かつ高価権 高誘電率のアルミナセラミックを用
いる通常のセラミックパッケージに比べ 低価格低誘電
率のポリイミドフィルムを用いるたべ 大幅な低コスト
化 低浮遊容量化が達成できん ところで、高周波特性
において、入出力のアイソレーション（−１″＋２１）
が大きくとれることパ 良い性能を引き出すために重要
であん この−１″＋２１上 ほぼ入出力の結合容量に
よって決まも 本発明のように 入出力電極ポリイミド
フィルム上に構成した場念 第５図における従来例と異
なり、人出力間にシールド用のアースパターンがないた
べ アイソレーションが悪くなるという問題が生じも
実際のＦＥＴ３１のチップ上で｛上 ソース，ドレイン
の間隔は約３μｍと極めて近接しており、ここのアイソ
レーションを良好にすることは高周波チップにとって極
めて重要であも そこで本実施例で｛友 フレキシブル
フィルムの入出力電極の間に深さ２００μＩＱ〜３００
μｍ程度の凹み（空隙）３５を設け、人出力間に樹脂等
の誘電率の大きいものを存在させ哄 空気層で入出力を
分離するようにして、アイソレーションを高めるように
してあも またその凹み３５の表面にソースリード電極
パターン３２（Ｓ）をはわせることにより、シールド効
果をもたせ、一層アイソレーションが高められる構或に
してあ：ｌ， ＧａＡｓＦＥＴの一種であるＨＥＭＴ
半導体チップを実装した例ではこのようにすることによ
り、下表に示すようにＫｕ帯でアイソレーシタンが５ｄ
Ｂ程改善できｔラ この結果＆上 この種ＧＨｚ状上
に使用される高周波半導体素子にとって極めて大きい効
果をもたらも また雑音指数ＮＦも０．１ｄＢ程改善で
きｔラ（測定周波数／２ＧＨｚ）
フレキシブルフィルム３０上に接着されたチップ３１
Ｊ＆ セラミックのふた３６で封止し九 このような
封止方法で｛上 耐湿性に対し不完全である爪チップを
ＳｉＮで完全にパシベーションしておけば問題な〜１
本発明（上 外形上１上 従来のセラミックパッケージ
とあまり変わらないた奴 回路への実装は ほぼ同様に
可能であも 第３図は 本発明の他の実施例の方法によ
り、ビームリードタイプの半導体装置を与えるものであ
も 第４図（よ バンプ付近の拡大図を示す。リードフ
レームよりなるリード６２に前述のごとく転写バンプ法
等でバンプを形或すも 各リードは図示しない部分で一
体につながって支持されていも 第３図でｉ；Ｌ Ｆ
ＥＴ３１で入出力阻 あるい（上 ゲートドレイン間の
シールド効果をもたせるために ソースリード６２（Ｓ
）をくぼませて空隙３５を形成し 第３，４図に示すよ
うにバンプ３４を形成し接続した バンプ６３の高さが
５０μ船以上高ければ ソースリード６２（Ｓ）は必ず
し転 くぼませる必要はな（１ その抵 第４図では
セラミックケース（ふた）６０を、 リードをはさむよ
うにして接着しｔラ この後、 リードの接続部（図
示せず）すなわちリードフレームに一部を切断し リー
ドを１個ずつ独立したものとすることにより、ビームリ
ードタイプの半導体装置ができ上も セラミックケース
６０で封止する代りに樹脂をモールドしてもよいし フ
レキシブルフィルム樹脂でおおってもよ鶏 このような
ビームリードタイプの半導体装置（．ｔ．小型 低コス
トで有用であり、従来のセラミックパッケージに比べ半
分程度のコストが可能となん
発明の効果
本発明により３ＧＨｚ以上の高周波トランジスタにおい
て、極めて優れた高周波特性と、低コスト化が同時に実
現でき高周波半導体装置の製造に格別となん 特に衛生
放送東 衛星通信におけるＳＨＦコンバー夕のコストダ
ウン化に有利であり、本発明は高性能な高周波半導体装
置の提供にすぐれた工業的価値を発揮するものであも[Detailed Description of the Invention] Industrial Application Fields of the Invention {1] Related to semiconductor packaging that provides excellent high frequency characteristics, conventional techniques include high frequency transistors of 3 GHz or higher, especially GaAs FETs.
The chip 100 is sealed in a package made of alumina ceramic 10L as a paste material as shown in FIG.
3 is a bonding wire, 103A. 103B, 1
03C is Au plating layer, respectively drain lead 104
．． The source lead 105 and the gate lead 106 are connected. 4 107 is filled with a ceramic lid. An example of the assembly flowchart when assembling a GaAsFET as such a package is shown in Figure 6. On the back side of the GaAs wafer, metallization such as l, = Au is applied for adhesion of die bonding filler metal (solder). Next, cut this into chips and break them.Next +. :, Each chip is Au/
Dice bond to the Au plating layer 103B using a brazing material such as Sn solder. After this, the boring wire 102
S, 102D, and 102G are used for wire bonding.At this time, the source inductance should be made as small as possible, especially for high frequencies, especially noise figure (F) and gain (Ga).
It is important to make the wire bonding wires as short as possible or increase the number of wires (four wires in Figure 5). However, the problem that the invention is trying to solve is the desire to reduce the cost of microwave semiconductor packages.It is too large to be absorbed by reducing the cost of semiconductor chips alone, and even though there is a strong desire to reduce assembly and mounting costs, and However, as long as conventional ceramic packages are used, there is a limit to cost reduction, and there is a demand for even higher performance. However, there is a limit to improving the chip alone, and improvements from the mounting side are necessary.For example, in order to shorten the length of the source wire mentioned above, bumps are formed on the electrodes of the ceramic package, and the pads on the chip are placed opposite each other. However, this method C
Although the performance is improved, it uses a ceramic package and requires a process to form bumps on an expensive ceramic body, which is still expensive.
The present invention g1 was made in view of such disadvantages, and is a means to solve the problem with the aim of obtaining a package that realizes extremely excellent high frequency characteristics at low cost. High-frequency semiconductor device 1 of the invention A metal electrode pattern is provided on one side of a flexible film, a plurality of bumps are formed on a part of the electrode pattern, and the bumps are bonded to face the plurality of electrode pads of a high-frequency semiconductor element. At that time, a recess is provided on the flexible film between the plurality of bumps, or preferably, a part of the surface of the recess provided on the flexible film is formed with a metal electrode pattern to be connected to the electrode pad. In addition, according to the present invention (above), a bump is formed on a part of one side of the lead frame where a shield plate is present between the input and output.
tA analogy l. c. A plurality of electrode pads of a high frequency semiconductor device used at 3 GHz or higher and the bump are bonded facing each other, and a gap is provided between the lead frame and the device, and the semiconductor device is sealed. According to the present invention, a so-called flip-bond method in which a high-frequency semiconductor chip is turned upside down and bonded onto a metal pattern on a film carrier is used. Moreover, by using metal protrusions (bumps), not only can the conventional wire bonding process be omitted, but also the source inductance of the element, which has a negative effect on high frequency characteristics, can be kept small. In addition to using a ceramic package, it is possible to achieve a significant cost reduction compared to a ceramic package in which bumps are formed here.
In addition, stray capacitance can be kept small compared to ceramic packages, which is extremely advantageous for improving performance.
According to the present invention, it is possible to greatly improve isolation performance by separating air between input and output, which is a particular problem in high-frequency transistors. By using a method of forming bumps on a lead frame and then sealing them to form leads, it is possible to obtain a low-cost package.Embodiment An embodiment of the present invention will be explained with reference to the drawings. Form an electrode lead 32 made of a metal pattern on the main surface side of the flexible film 30 (polyimide film) shown in FIG. Gold bumps 3 where needed
For example, in this embodiment, a GaAsFET that processes signals of 3 GHz or higher is used as a high-frequency semiconductor element.
Even if the bumps 34 are formed on the leads 32 in accordance with the bonding pads of the chip No. 31, the bump formation method using transfer bumps is still the same.The bumps are formed on a glass plate (not shown). This can be done by peeling off the bumps from the glass substrate and transferring them.However, the bump shape or the transfer bump method is not necessarily required, and the bumps 34 can be formed on the leads 32 by other methods. It's OK to do this.FET31, which is a semiconductor chip, is connected to the pattern lead 32's valve 34FET3.
The batch bonding module 35 recognizes and positions the electrode pads 1 and 35 on the flexible film 30 between the valves.
Although the ceramic lid 36 is omitted in FIG. 1(a), in the lead 32 of FIG. 1, S is the source lead and B is the drain or output lead. is a gate, that is, an input lead. Q of the Invention An enlarged perspective view of the vicinity of the bump 34 is shown in FIG. A gold bump 34 is formed on this metal pattern 32.
height and diameter (in this example, 50 to 100 μm, 50
If the height of the bump is not higher than a certain level, the parasitic capacitance between the GaAs chip 31 and the metal lead will increase and the characteristics will deteriorate. There is no need to form bumps, and the price is high.Compared to ordinary ceramic packages that use high-permittivity alumina ceramics, the use of low-cost, low-permittivity polyimide films significantly reduces costs.Low stray capacitance cannot be achieved. , In high frequency characteristics, input/output isolation (-1″+21)
It is important to obtain a large value in order to obtain good performance. This -1"+21 above is determined by the coupling capacitance of the input and output. As in the present invention, when the input and output electrodes are constructed on a polyimide film, the conventional method shown in Fig. 5 Unlike the example, there is no ground pattern for shielding between the human outputs, which may cause problems such as poor isolation.
On the actual FET31 chip, the space between the source and drain is extremely close, about 3 μm, and it is extremely important to have good isolation here for high frequency chips. The depth between the input and output electrodes of the film is 200 μIQ ~ 300
A recess (void) 35 of approximately μm size is provided, and a material with a high dielectric constant such as resin is placed between the human output and the input and output are separated by an air layer to increase isolation. By placing the source lead electrode pattern 32 (S) on the surface of the recess 35, a shielding effect is provided and isolation is further improved.
In an example where a semiconductor chip is mounted, by doing this, the isolating tan can be reduced to 5d in the Ku band as shown in the table below.
This results in an extremely large effect on high-frequency semiconductor devices used in this type of GHz circuit.The noise figure NF can also be improved by about 0.1 dB (measurement frequency/2 GHz) Flexible Chip 31 glued onto film 30
J & Sealed with a ceramic lid 36.9 With this sealing method, if the nail chip, which has incomplete moisture resistance, is completely passivated with SiN, there will be no problem ~1
Although it is possible to implement the present invention into a circuit in almost the same way as a conventional ceramic package, Figure 3 shows a beam-lead type semiconductor package that can be manufactured using a method according to another embodiment of the present invention. Figure 4 shows an enlarged view of the vicinity of the bumps. Although bumps are formed on the leads 62 made of the lead frame by the transfer bump method as described above, each lead is integrated with a part not shown in the figure. Even if they are connected and supported, i;L F in Figure 3
The input/output is blocked by ET31 or (top) The source lead 62 (S
) is depressed to form a gap 35, and a bump 34 is formed and connected as shown in Figures 3 and 4. If the height of the bump 63 is 50 μm or more, the source lead 62 (S) must be depressed. Hana (1) In Figure 4,
The ceramic case (lid) 60 is glued in such a way as to sandwich the leads. After that, a part of the lead connection part (not shown), that is, the lead frame is cut to make each lead independent. When a beam lead type semiconductor device is completed, it may be molded with resin instead of being sealed with the ceramic case 60, or it may be covered with a flexible film resin.Such a beam lead type semiconductor device (.t. It is small, low cost, and useful, and the cost is about half that of conventional ceramic packages.Advantages of the InventionThe present invention enables extremely excellent high frequency characteristics and low cost to be achieved at the same time in high frequency transistors of 3 GHz or higher. This invention is particularly advantageous in reducing the cost of SHF converters in satellite communications, and the present invention exhibits excellent industrial value in providing high-performance high-frequency semiconductor devices. too
第１図（ａ）は本発明の一実施例の半導体装置の要部平
面は 第１図（ｂ）は同図（ａ）のＡ−Ａ’線断面は第
２図は第１図の装置のバンプ付近の拡大斜視は第３図（
ａ）は本発明の他の実施例の半導体装置の平面は 第３
図（ｂ）は同（ａ）のｃ−ｃ’線断面は 第４図は第３
図の実施例のバンプ付近の拡大斜視は 第５図（ａ）．
（ｂ）は従来の半導体装置の平面図 断面は第６図は
従来パッケージの組立工程図であも３ｌ・・・・ＧａＡ
ｓＦＥＴチッス ３２・・・・リード、 ３４・・・・
バンズ ３５・・・・空隙（凹部）、３６・・・・セラ
ミックのフ？，．５０・・・・樹Ｂ８． ６２−−−
−フレームリード、６０・・・・セラミックケ一人FIG. 1(a) is a plan view of the main part of a semiconductor device according to an embodiment of the present invention. FIG. 1(b) is a cross section taken along the line A-A' in FIG. An enlarged perspective view of the vicinity of the bump is shown in Figure 3 (
In a), the plane of the semiconductor device according to another embodiment of the present invention is the third one.
Figure (b) is the c-c' line cross section of (a). Figure 4 is the 3rd section.
An enlarged perspective view of the bump area of the illustrated embodiment is shown in Figure 5(a).
(b) is a plan view of a conventional semiconductor device, and the cross section is shown in Figure 6, which is an assembly process diagram of a conventional package.
sFET chiss 32...lead, 34...
Buns 35...Gap (concavity), 36...Ceramic flap? 、． 50...Tree B8. 62---
-Frame lead, 60...Ceramic one person
Claims (4)
ンを設け、前記電極パターンの一部に複数のバンプを形
成し、前記複数のバンプの間のフレキシブルフィルム上
に凹みを設け、高周波半導体素子の複数の電極パッドと
前記バンプを対向させて接着したことを特徴とする高周
波半導体装置。(1) A metal electrode pattern is provided on one side of a flexible film, a plurality of bumps are formed on a part of the electrode pattern, and a recess is provided on the flexible film between the plurality of bumps, and a plurality of high frequency semiconductor elements are formed. A high frequency semiconductor device characterized in that an electrode pad and the bump are bonded to each other so as to face each other.
の一部を、電極パッドと接続される金属電極パターンで
おおい、前記パターンを入出力間に設置してシールド電
極としてなることを特徴とする特許請求の範囲第１項記
載の高周波半導体装置。(2) A patent characterized in that a part of the surface of a recess provided on a flexible film is covered with a metal electrode pattern connected to an electrode pad, and the pattern is installed between input and output to serve as a shield electrode. A high frequency semiconductor device according to claim 1.
中空封止してなることを特徴とする特許請求の範囲第１
項記載の高周波半導体装置。(3) Claim 1, characterized in that the semiconductor element is covered with a ceramic container and the element is sealed in a hollow manner.
The high frequency semiconductor device described in Section 1.
片面の一部にバンプを形成し、高周波半導体素子の複数
の電極パッドと前記リードフレームのバンプを対向させ
て接着するとともに前記リードフレームと素子間に空隙
を設け、前記半導体素子を封止し、前記フレームの一部
を切断してリードを形成することを特徴とする高周波半
導体装置。(4) Bumps are formed on a part of one side of the lead frame where a shield plate is present between the input and output, and the plurality of electrode pads of the high frequency semiconductor element and the bumps of the lead frame are bonded so as to face each other, and the lead frame and the element are bonded together. A high-frequency semiconductor device, characterized in that a space is provided between the semiconductor elements, the semiconductor element is sealed, and a lead is formed by cutting a part of the frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2101281A JP2574510B2 (en) | 1989-04-17 | 1990-04-17 | High frequency semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9711489 | 1989-04-17 | ||
| JP1-97114 | 1989-04-17 | ||
| JP2101281A JP2574510B2 (en) | 1989-04-17 | 1990-04-17 | High frequency semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0348436A true JPH0348436A (en) | 1991-03-01 |
| JP2574510B2 JP2574510B2 (en) | 1997-01-22 |
Family
ID=26438317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2101281A Expired - Lifetime JP2574510B2 (en) | 1989-04-17 | 1990-04-17 | High frequency semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2574510B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529393A (en) * | 1991-07-22 | 1993-02-05 | Sharp Corp | Board for mounting semiconductor device |
| JPH05283552A (en) * | 1992-03-31 | 1993-10-29 | Nec Corp | High frequency semiconductor device |
| JP2001185655A (en) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | Microwave circuit |
| US6486412B2 (en) | 2000-09-13 | 2002-11-26 | Seiko Epson Corporation | Wiring board, method for producing same, display device, and electronic device |
| US6617521B1 (en) | 1998-12-21 | 2003-09-09 | Seiko Epson Corporation | Circuit board and display device using the same and electronic equipment |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102343920B1 (en) * | 2019-06-04 | 2021-12-29 | 제엠제코(주) | Semiconductor package |
| US11270969B2 (en) | 2019-06-04 | 2022-03-08 | Jmj Korea Co., Ltd. | Semiconductor package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103772A (en) * | 1975-03-10 | 1976-09-13 | Tokyo Shibaura Electric Co | HANDOTA ISOCHI |
| JPS5811246U (en) * | 1981-07-13 | 1983-01-25 | 三菱電機株式会社 | semiconductor equipment |
| JPS63209152A (en) * | 1987-02-25 | 1988-08-30 | Nec Corp | Lead frame |
-
1990
- 1990-04-17 JP JP2101281A patent/JP2574510B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103772A (en) * | 1975-03-10 | 1976-09-13 | Tokyo Shibaura Electric Co | HANDOTA ISOCHI |
| JPS5811246U (en) * | 1981-07-13 | 1983-01-25 | 三菱電機株式会社 | semiconductor equipment |
| JPS63209152A (en) * | 1987-02-25 | 1988-08-30 | Nec Corp | Lead frame |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529393A (en) * | 1991-07-22 | 1993-02-05 | Sharp Corp | Board for mounting semiconductor device |
| JPH05283552A (en) * | 1992-03-31 | 1993-10-29 | Nec Corp | High frequency semiconductor device |
| US6617521B1 (en) | 1998-12-21 | 2003-09-09 | Seiko Epson Corporation | Circuit board and display device using the same and electronic equipment |
| JP2001185655A (en) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | Microwave circuit |
| US6486412B2 (en) | 2000-09-13 | 2002-11-26 | Seiko Epson Corporation | Wiring board, method for producing same, display device, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2574510B2 (en) | 1997-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7622793B2 (en) | Flip chip shielded RF I/O land grid array package | |
| US6597059B1 (en) | Thermally enhanced chip scale lead on chip semiconductor package | |
| US7268426B2 (en) | High-frequency chip packages | |
| US7045883B1 (en) | Thermally enhanced chip scale lead on chip semiconductor package and method of making same | |
| KR20010012187A (en) | Ball grid array semiconductor package and method for making the same | |
| CN106024643B (en) | Substrate interposer on a leadframe | |
| EP0393584B1 (en) | High frequency semiconductor device | |
| TWI785515B (en) | Semiconductor packages and apparatus having the same | |
| US5917241A (en) | High frequency semiconductor device having source, drain, and gate leads | |
| JPH0348436A (en) | High frequency semiconductor device | |
| US7064009B1 (en) | Thermally enhanced chip scale lead on chip semiconductor package and method of making same | |
| WO2020227589A1 (en) | Electronic device with double-sided cooling | |
| US6933603B2 (en) | Multi-substrate layer semiconductor packages and method for making same | |
| US6982483B2 (en) | High impedance radio frequency power plastic package | |
| US7579680B2 (en) | Packaging system for semiconductor devices | |
| JPH0563136A (en) | Hybrid integrated circuit device | |
| US11830842B2 (en) | Hybrid device assemblies and method of fabrication | |
| JP2682200B2 (en) | Semiconductor device | |
| JP2002124627A (en) | Semiconductor device and its manufacturing method | |
| JP2701348B2 (en) | Semiconductor device | |
| JPH10321762A (en) | Semiconductor device | |
| JPH09213868A (en) | Lead frame for microwave semiconductor integrated circuit | |
| KR100345163B1 (en) | Ball grid array package | |
| JPH04137753A (en) | High frequency semiconductor device | |
| US20020030260A1 (en) | Electronic component and method of manufacture |