JPH0347589B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory cell of a static semiconductor MOS memory.

[Prior art]

Conventionally, this type of memory cell is highly integrated and
Various structures have been proposed for the purpose of reducing power consumption. Examples of this type of reference material include:
Electronics November 6, 1980 issue, pages 145-148. As indicated in the document, improvements have been made especially to the structure of the load resistor. Initially, enhancement-type MOS transistors were used as this load, but later they changed to depletion-type MOS transistors, then single-layer polysilicon, and then double-layer polysilicon.Currently, the most highly integrated method is to use a diffusion layer for the ground line. This is the structure shown in FIG. 1, using a double-layer polysilicon layer as a load. Figure 2 shows its equivalent circuit.As is clear from Figure 2, this memory cell consists of four cells connected drain-to-gate or drain-to-drain.
It consists of a MOS transistor and two resistors.

In FIG. 1, 1a to 1g are active regions without a field oxide film, which form the drain and source of a MOS transistor, 1a and 1g are connection parts 21 in FIG.
a, 1c are connection parts 23, 1d is ground terminal 22b,
1e corresponds to a connection to the bit line 24, and 1f corresponds to a connection to the bit line 25.
2a to 2c are first polysilicon layers; 2a to 2c are first polysilicon layers;
The MOS transistors 26a and 2b in Fig. 2 are the same, and the MOS transistors 26b and 2c are the same.
Each gate constitutes the MOS transistors 26c and 26d. Common contacts 3a to 3c connect the active region and the second polysilicon layer or the first polysilicon layer and the second polysilicon layer. 4a to 4e are second polysilicon layers formed by stacking on the first polysilicon layer, 4a to 4c are low resistance values, 4d and 4e
has a high resistance value, and 4a connects the active region 1c and the first polysilicon layers 2a and 4b connect the active region 1a, the active region 1g, and the first polysilicon layer 2b. 4c is a power supply line corresponding to 27 in FIG. 4d and 4e are resistors 28a and 2 in FIG.
Compatible with 8b. Furthermore, 5a and 5b are bit lines 2 formed of metal conductors such as aluminum.
This is the contact for 4,25. In addition, in FIG. 2, 29 is a word line.

In this way, in the structure based on the conventional two-layer polysilicon process, the two resistors, the connection line, and the power supply line are all formed from the second polysilicon layer.
The disadvantage is that the conditions for setting the width of the pattern 4e and the mutual spacing are extremely strict, making it difficult to achieve higher integration.

[Summary of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory cell that allows the cell area to be reduced and a static type semiconductor memory to be more highly integrated.

In order to achieve such an objective, the present invention
A first MOS transistor 26c and a second MOS transistor 26d whose gates are connected to a word line, and a third MOS transistor 2 whose drains are mutually connected to the first MOS transistor.
6b, the gate is connected to the drain of the third MOS transistor, the drain is connected to the drain of the second MOS transistor, and the third
a fourth connected to the gate of the MOS transistor;
MOS transistor 26a and a first resistor 28a connected to the drain of the third MOS transistor
and a second resistor 28b connected to the drain of the fourth MOS transistor, in which the gates of the first, second, third, and fourth transistors are each formed from the first polysilicon layer. , a connection between the drain of the third transistor and the gate of the fourth transistor, a connection between the drain of the fourth transistor and the gate of the third transistor, and a connection between the drain of the first transistor and the gate of the third transistor. The connection between the drains and the connection between the drain of the second transistor and the drain of the fourth transistor are formed using the second layer of polysilicon, and the first and second resistors are formed using the first and second layers of polysilicon. It is formed of a third polysilicon layer having a higher resistance value than the other layers. Hereinafter, the present invention will be explained in detail using Examples.

[Embodiments of the invention]

FIG. 3 is a plan view showing an embodiment of the present invention. In the figure, active regions 1a to 1g, first polysilicon layers 2a to 2c, and common contact 3a
3c, second polysilicon layers 4a, 4b and contacts 5a, 5b are similar to the conventional one shown in FIG. On the other hand, 31a-3
1c is the third polysilicon layer, 32a, 3
2b is what is called a direct contact for connecting the second polysilicon layers 4a, 4b and the third polysilicon layers 31a, 31b. The third polysilicon layers 31a and 31b have a high resistance value,
They correspond to the second polysilicon layers 4d and 4e in FIG. 1, that is, the resistors 28a and 28b in FIG. 2, respectively. On the other hand, the third polysilicon layer 31c
has a low resistance value and corresponds to the second polysilicon layer 4c in FIG. 1, that is, the power supply line 27 in FIG. 2.

In this way, the second
Since the elements constituted by the polysilicon layer are dispersed between the second polysilicon layer and the third polysilicon layer, it has become possible to reduce the cell area. Also, if the same cell area is maintained,
Conventionally, the length of the high resistance polysilicon layers 4d and 4e (shaded area) was not sufficient, making it difficult to stably manufacture a high resistance load. The length of 31b (hatched portion) can be made sufficiently large.

In addition, in the above-mentioned embodiment, an example was explained in which the connection between the active region 1a, the active region 1g, and the first polysilicon layer 2b was configured by the parallel connection of the first polysilicon layer and the second polysilicon layer. However, this only needs to be connected to either one.

〔Effect of the invention〕

As explained above, according to the present invention, a high resistance load is connected to the first polysilicon layer forming the gate of the MOS transistor and the active region and first polysilicon layer forming the source and drain of the MOS transistor. By forming the third polysilicon layer separate from the second polysilicon layer used for connections, etc., it is possible to achieve even higher integration of static semiconductor MOS memories, and stable control of high resistance values is possible. It has an effect that is easy to perform.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a memory cell of a conventional static type semiconductor MOS memory, FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is a plan view showing an embodiment of the present invention. 1a to 1g...MOS transistor sources,
Active regions forming the drain, 2a to 2c...
First polysilicon layer forming the gate of the MOS transistor, 4a, 4b...Second polysilicon layer forming the drain-gate and drain-drain connection of the MOS transistor, 31
a, 31b...Third polysilicon layer forming a resistor.

Claims (1)

[Claims] 1. A first MOS whose gate is connected to a word line.
a transistor and a second MOS transistor;
A third MOS transistor whose drains are connected to the first MOS transistor, a third MOS transistor whose gate is connected to the drain of the third MOS transistor, whose drain is connected to the drain of the second MOS transistor, and a third MOS transistor whose drains are connected to the drain of the second MOS transistor. Consists of a fourth MOS transistor connected to the gate of the MOS transistor, a first resistor connected to the drain of the third MOS transistor, and a second resistor connected to the drain of the fourth MOS transistor. In the semiconductor memory cell, the gates of the first, second, third, and fourth MOS transistors are each formed of a first polysilicon layer, and the drain of the third MOS transistor and the fourth MOS transistor are formed of a first polysilicon layer.
Connection between the gates of MOS transistors, the fourth
The connection between the drain of the MOS transistor and the gate of the third MOS transistor, and the connection between the drain of the MOS transistor and the gate of the first
A connection between the drain of the MOS transistor and the drain of the third MOS transistor, and a connection between the drain of the second MOS transistor and the drain of the fourth MOS transistor are formed using the second polysilicon layer, respectively; A semiconductor memory cell characterized in that first and second resistors are formed of a third polysilicon layer having a higher resistance value than the first and second polysilicon layers, respectively.