JPH0345932B2 - - Google Patents

Description

Claim 1: In an integrated circuit adapted to receive operating power via first and second supply voltage nodes, a source region of a first conductivity type coupled to the first supply voltage node, a source region of a first conductivity type coupled to an intermediate node; a drain region of a first conductivity type; a current channel region of a second conductivity type between the source region and the drain region and coupled to the first supply voltage node; and a region adjacent to the current channel region; a first field effect transistor having a gate electrode insulated from and coupled to a second supply voltage node; a source region of a second conductivity type coupled to the first input node; a second conductivity type coupled to the intermediate node; a current channel region of a first conductivity type between the source and drain regions and coupled to the input node; and a first conductivity type current channel region adjacent to but insulated from the current channel region and coupled to the input node. a second field effect transistor having a gate electrode coupled to two supply voltage nodes; a source region of a first conductivity type coupled to the first supply voltage node; a drain region of a first conductivity type coupled to an output node; a second supply voltage node between the region and its drain region and coupled to the first supply voltage node;
a third field effect transistor having a conductivity type current channel region and a gate electrode adjacent to but insulated from the current channel region and coupled to a second input node; a source region of a second conductivity type coupled to a drain region of a second conductivity type; a current channel region of a first conductivity type between the source region and its drain region coupled to the first input node; and a fourth field effect transistor having a gate electrode adjacent to but insulated from the current channel region and coupled to the second input node; and a second conductivity transistor coupled to the drain region of the fourth transistor. a drain region of a second conductivity type coupled to the output node; a current channel region of a first conductivity type between the source region and its drain region coupled to the first input node; a fifth field effect transistor having a gate electrode adjacent to but insulated from the current channel region and coupled to the intermediate node; and a source region of a second conductivity type coupled to the first input node. a drain region of a second conductivity type coupled to the output node, a current channel region of the first conductivity type between the source region and the drain region and coupled to the first input node, and adjacent to the current channel region. a sixth field effect transistor having a gate electrode coupled to the second supply voltage node and isolated from the region, the voltage sensing and conversion circuit generating an output signal at an output node.

2 The on-resistance of the second transistor is smaller than the on-resistance of the first transistor, and the voltage at the first supply voltage node and the voltage at the second supply voltage node and the first
2. The voltage detection and conversion circuit of claim 1, which provides a significant intermediate node voltage swing between input node voltages.

3. The voltage sensing and conversion circuit of claim 2 further comprising at least one additional gain stage coupled between the intermediate node and the gate electrode of the fifth field effect transistor.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to voltage sensing and translating circuits, and more particularly to detecting the presence of an input voltage that is outside the range of the circuit's supply voltage. , relates to a circuit for translating an input signal within a range of the circuit's supply voltage to a wider voltage range of detected input voltages.

Description of the Prior Art Generally speaking, voltage sensing circuits are designed to provide a particular output in response to the presence of an input signal that is within the range of the circuit's supply voltage. However, in some applications it is desirable to detect the presence of input voltages that are outside the range of the detection circuit's supply voltages. In contrast, voltage conversion circuits are designed to provide an input signal that is related to, but different from, an input signal that is within the supply voltage of the circuit. In some applications, it is desirable to provide an output voltage that is outside the range of the converter circuit's normal supply voltages.

For example, in a typical monolithic microprocessor with electrically programmable permanent memory (EPROM), the microprocessor supply voltages are +5 volts and 0 volts.
However, on-chip EPROMs can only be programmed with programming voltages well outside these supply voltages. In a typical N-channel device, the programming voltage will be on the order of +20 volts, but in CMOS devices, the programming voltage will be -15 or +20 volts, depending on the conductivity type of the field effect transistor used to form the EPROM storage cell. It will be about. If the microprocessor is also self-programming, that is, the contents of external memory can be automatically transferred to on-chip EPROM, then some means must be provided to put the device into self-programming mode. . One convenient way to perform this function is to include a voltage sensing circuit that provides a distinct output signal only when a programming voltage is applied to a particular input pin of the microprocessor. However, prior art voltage detection circuits of this type tend to take the form of rather complex voltage comparators. Furthermore, the output signal that such prior art voltage detection circuits provide to indicate the presence of a programming voltage is typically limited to a range of supply voltages.

If the device is to be placed in self-programming mode, some means must also be provided to couple the programming voltage to the EPROM programming logic. One convenient way to perform this function is to include a voltage conversion circuit that selectively provides the programming voltage as an output signal when the programming voltage is applied to a particular input pin of the microprocessor. be. However, prior art voltage conversion circuits of this type tend to be relatively complex. Furthermore,
Such circuits typically require a bias voltage generation circuit to bias the current channel region of the coupling transistor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a simple voltage detection circuit for detecting input signals outside the range of the circuit's supply voltage.

Another object of the invention is to provide a voltage detection circuit that provides an output signal of approximately the same voltage as the detected input signal outside the range of the circuit's supply voltage.

Another object of the invention is to provide a simple voltage conversion circuit that converts an input signal within the range of the circuit's supply voltage to an output signal outside such range.

Yet another object of the invention is to provide a voltage conversion circuit that provides an output signal of approximately the same voltage as a control voltage outside the range of the circuit's supply voltage.

These and other purposes include: a source region of a first conductivity type coupled to a first supply voltage node; a drain region of a first conductivity type coupled to an output node; a first electric field having a current channel region of a second conductivity type coupled to the first supply voltage node; and a gate electrode adjacent to but insulated from the current channel region and coupled to the second supply voltage node. an effect transistor, a source region of a second conductivity type coupled to the input node, a drain region of the second conductivity type coupled to the output node, a first conductivity type between the source region and the drain region and coupled to the input node. a second field effect transistor having a gate electrode adjacent to but insulated from the current channel region and coupled to a second supply voltage node; achieved. On resistance of the second transistor (on
Preferably, the on-resistance of the first transistor is significantly smaller than the on-resistance of the first transistor.

In a preferred embodiment, the voltage sensing circuit includes a source region of a first conductivity type coupled to a first operating voltage node, a drain region of a first conductivity type coupled to an output node, and between the source region and the drain region. a current channel region of a second conductivity type coupled to the first operating voltage node; and a gate electrode adjacent to but insulated from the current channel region and coupled to the first input node. a field effect transistor; a source region of a second conductivity type coupled to a second input node; a drain region of a second conductivity type; a second field effect transistor coupled to the second input node between the source region and the drain region; a second field effect transistor having a current channel region of one conductivity type, and a gate electrode adjacent to but insulated from the current channel region and coupled to the first input node; and a drain region of the second transistor. a source region of a second conductivity type coupled to the output node, a drain region of the second conductivity type coupled to the output node, and a current of the first conductivity type between the source region and the drain region coupled to the second input node. a third field effect transistor having a channel region and a gate electrode adjacent to but insulated from the current channel region and coupled to a third input node; and a second conductivity transistor coupled to the second input node. a source region of a shape, a drain region of a second conductivity type coupled to the input node, a current channel region of a first conductivity type between the source region and the drain region and coupled to the second input node; A second area that is adjacent to but insulated from that area.
and a fourth field effect transistor having a gate electrode coupled to the operating voltage node.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a voltage detection circuit made in accordance with the present invention. FIG. 2 is a schematic diagram of a voltage conversion circuit made in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a voltage sensing circuit 10 consisting primarily of a P-channel field effect transistor 12 and an N-channel field effect transistor 14. As shown in FIG. Transistor 12 has a P-type source region coupled to positive supply voltage node 16, a P-type drain region coupled to node 18, an N-type current channel region between the source and drain regions and coupled to positive supply voltage node 16; and a gate electrode adjacent to but insulated from the current channel region and coupled to a negative supply voltage node 20. Transistor 14 has an N-type source region coupled to input node 22, an N-type drain region coupled to node 18, a P-type current channel region between the source and drain regions and coupled to input node 22, and a current channel region coupled to input node 22. It has a gate electrode adjacent to but insulated from the region and coupled to a negative supply voltage node 20.

In operation, positive and negative supply voltage nodes 16 and 20 are each coupled to a power supply (not shown) that can create a potential difference therebetween on the order of +3 to +15 volts. Therefore,
Transistor 12 is biased in the on or conducting state, thereby tending to charge node 18 toward the positive supply voltage.

As long as the voltage at input node 22 is within the supply voltage range, transistor 14 is biased in an off or non-conducting state, thereby allowing transistor 12 to charge node 18 to the positive supply voltage. However, when input node 22 is coupled to an input signal that is below the negative supply voltage by at least the threshold voltage of transistor 14, transistor 14 is biased in an on or conducting state, thereby causing node 18 to move in the direction of the voltage of the input signal. There is a tendency to discharge. Under these conditions, the voltage at node 18 settles between the positive supply voltage and the voltage of the input signal depending on the relative saturation currents of transistors 12 and 14.

For example, the width-to-length ratio of the current channel is 6/25 for transistor 12, and 6/25 for transistor 14.
If the case is 50/7, the on-resistance of transistor 14 is much smaller than the on-resistance of transistor 12, so that when the voltage of the input signal is sufficiently below the negative supply voltage, transistor 14 draws more current than transistor 12. , the voltage drop across transistor 12 will be much larger than the voltage drop across transistor 14. Therefore, the voltage at node 18 will be approximately equal to the voltage of the input signal.

In some applications, the significantly unbalanced source and sink currents at node 18 in the above example may be undesirable. In the illustrated form, transistors 12 and 14 may be much smaller than in the example above. This is because the resulting voltage increase at node 18 is compensated for by including additional gain stages 24 and 26. for example,
Using a -15 volt "design" input signal, the width-to-length ratios of transistors 12 and 14 are 8/15 and 25/10, respectively, so the resulting on-resistance of transistor 14 is still The on-resistance is smaller than that of 12. However, if the input signal is -15 volts, the voltage at node 18 will be in the range of approximately -8 volts. This voltage swing is increased by a gain stage 24 connected like transistors 12 and 14 but with their gate electrodes coupled to node 18 in a second channel field. It includes an effect transistor 28 and a second N-channel field effect transistor 30. For example, transistor 28
and 30 width-to-length ratios of 30/6 and 6/6, respectively, the switch point of gain stage 24 will be approximately 0 volts and the voltage developed at node 32 will be the voltage of the positive supply voltage and the "design" input signal. , i.e. swinging between -15 volts for the example given. However, it will be appreciated that the on-resistance of transistor 28 is still somewhat less than the on-resistance of transistor 30. A balanced current is obtained while maintaining the total voltage swing by a gain stage 26, which controls transistors 12 and 1.
4, respectively, but their gate electrodes are coupled to node 32.
3P channel field effect transistor 34 and
Includes a 3N channel field effect transistor 36.
Using conventional width-to-length ratios of 30/6 and 10/6 for transistors 34 and 36, respectively, the switch point of gain stage 26 will be midway between the positive supply voltage and the "design" input signal, and will be at node 38. The resulting voltage swings between the positive supply voltage, ie, +5 volts, and the voltage of the "design" input signal -15 volts. Furthermore,
The source and sink currents at node 38 will be the same.

Illustrated in FIG. 2 is a voltage conversion circuit 40 consisting of a P-channel field effect transistor 42 and three N-channel field effect transistors 44, 46 and 48. Transistor 42 has a P-type source region coupled to a positive supply voltage node 50, a P-type drain region coupled to an output node 52, and an N-type current channel between the source and drain regions and coupled to positive supply voltage node 50. a region, and a gate electrode adjacent to but insulated from the current channel region and coupled to a first input node 54. Transistor 44 is the second
an N-type source region coupled to input node 56; an N-type drain region; a P-type current channel region between the source and drain regions and coupled to second input node 56; and adjacent to the current channel region. is isolated from the region and has a gate electrode coupled to the first input node 54. Transistor 46 has an N-type source region coupled to the drain region of transistor 44, an N-type drain region coupled to an output node 52, and a P-type current channel between the source and drain regions and coupled to a second input node 56. a third region adjacent to but insulated from the current channel region;
It has a gate electrode coupled to input node 58 .
Transistor 48 has an N type source region coupled to a second input node 56 and an N type source region coupled to an output node 52.
a P-type current channel region between the source and drain regions and coupled to the second input node 56; and a negative supply voltage node 60 adjacent to but isolated from the current channel region. has a gate electrode coupled to the gate electrode.

In operation, positive and negative supply voltage nodes 50 and 60 are each coupled to a power supply (not shown) that can create a potential difference between as much as +3 to +15 volts therebetween. In a first mode of operation, second input node 56 is coupled to a negative supply voltage;
A third input node 58 is coupled to the positive supply voltage. Thus, transistor 46 is biased on or conducting and transistor 48 is biased off or non-conducting. Under these conditions transistors 42 and 44 connect to first input node 54.
forming an inverter in conjunction with the transistor 4
2 charges output node 52 to a positive supply voltage in response to first input node 54 coupling to the negative supply voltage, and transistor 44 charges output node 52 to a positive supply voltage in response to first input node 54 coupling to the positive supply voltage. Output node 52
discharges to the negative supply voltage.

In a second mode of operation, second and third input nodes 56 and 58 are connected to transistors 44 and 4.
At least the threshold voltages of 8 are each coupled to a control voltage below the negative supply voltage. Thus, transistor 46 is biased in an off or non-conducting state and transistor 48 is biased in an on or conducting state. Under these conditions, transistors 42 and 48 form an inverter in conjunction with first input node 54 such that transistor 42 couples output node 52 to the negative supply voltage in response to first input node 54 being coupled to the negative supply voltage. Once the transistor 48 is strong enough to charge to the positive supply voltage, the first input node 54 is coupled to the positive supply voltage and the transistor 4 is in an off or non-conducting state.
2 in response to biasing the output node 52
can be discharged to a control voltage.

One use of the voltage detection circuit 10 described above is to detect the coupling of a characteristic programming voltage outside the normal supply voltage range to a particular input pin to enable its programming logic. It is used in electrically programmable persistent memory (EPROM) integrated circuits. The voltage conversion circuit 40 is suitable for cooperating with the voltage detection circuit 10 to perform the word line selection function. In this manner, voltage detection circuit 10 selectively couples the positive supply voltage or programming voltage to the gate electrode of transistor 46 depending on whether a programming voltage is coupled to second input node 56 . In response, voltage conversion circuit 40 transfers the programming voltage from second input node 56 to output node 5.
Associated array word line (word line) connected to 2
selectively bind to.

The explanation of the operations shown in FIGS. 1 and 2 described above is as follows.

Voltage detection circuit 10 (FIG. 1) and voltage conversion circuit 40 (FIG. 2) couple output node 38 of voltage detection circuit 10 to third input node 58 of voltage conversion circuit 40, and voltage detection circuit 10 can be used cooperatively by coupling the input node 22 of the voltage conversion circuit 40 to the second input node 56 of the voltage conversion circuit 40. 2
When the two circuits are coupled in this manner, the voltages across nodes 56 and 58 of voltage conversion circuit 40, as well as nodes 22 and 38 of voltage detection circuit 10, of course vary synergistically. Voltage detection circuit 10
and the second input node 22 of the voltage conversion circuit 40
If the voltage across input node 56 is within the supply voltage range (i.e., equal to or greater than the voltage across nodes 20 and 60, node 1
6 and 50),
Voltage conversion circuit 40 operates in the first mode of operation described above. Input node 2 of voltage detection circuit 10
If the voltage across 2 is less than the negative supply voltage (nodes 20 and 60), the voltage conversion circuit operates in the second mode of operation described above.

The relationship between the voltage applied to node 54 and the voltage applied to node 52 is always an inverse relationship. When voltage conversion circuit 40 operates in its first mode of operation and node 54 is high (approximately equal to the larger positive supply voltage), the voltage across node 52 is low. In the first mode of operation (approximately equal to the larger negative supply voltage), if node 54 is high, then node 5
2 is approximately equal to the input voltage across node 22. It is lower than the larger negative supply voltage.
In the second mode of operation, when node 54 is low, node 52 is high.

From the above description, it can be seen that the voltage detection circuit 10 provides a positive supply voltage as an output when there is no input signal having a voltage less than or equal to the negative supply voltage, and provides the input signal itself when said input signal is present. I understand. However, because of their complementarity, voltage detection circuit 1
0 couples the negative supply voltage to node 22, the positive supply voltage to node 20, and the input signal to node 1.
6 can be easily used to detect input signals above the positive supply voltage. Assuming the transistor size is the same as in the last example and the "design" input signal is +20 volts, the output of node 38 will be the negative supply voltage in the absence of an input signal and the negative supply voltage in the presence of an input signal. +
20 volt input signal. Of course voltage detection circuit 1
0 by selecting the sizes of transistors 12 and 14 and the sizes of transistors 26-28 and 34-36, if present, by applying conventional arithmetic. The selection of the voltage can be made responsive to different "design" input signals that are outside the range of the selected positive and negative supply voltages.

From the above description, it is understood that voltage conversion circuit 40 will:
providing as its output a selected positive or negative supply voltage via a signal applied to a first input node 54 and a positive supply voltage and a second and third input node 56 when said signal is below the negative supply voltage; and 5
It can also be seen that a voltage between 8 and 8 is applied. However, voltage conversion circuit 40 can be easily modified to convert voltages above the positive supply voltage.

Other modifications or variations may be made to the preferred embodiments described above without departing from the spirit and scope of the invention, as set forth in the following claims.