JPH034533A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To diminish the potential fluctuation of a pad due to any leakage current between potential supply lines by a method wherein a high specific resistance layer is provided on the surface of a GaAs substrate between the first layer wiring for power supply and the first layer wiring for GND. CONSTITUTION:A high specific resistance layer 11 is provided on the surface of a GaAs substrate 1 between the first layer wiring 6 for power supply and the first layer wiring 5 for GND. This layer 11 is provided e.g. by implanting the surface of the GaAs substrate 1 with O ion e.g. acceleration voltage of 100KeV, dosage of 1X10<18>cm<-2>. This ion implantation process is performed after the formation of elements. Any leakage current running along the surface of GaAs substrate 1 can be retrained by the provision of this high specific resistance layer 11. Furthermore, this high specific resistance layer 11 can be formed into a capacitor together with the first layer wiring 6 for power supply and the first layer wiring 5 for GND thereby enabling the potentials of respective potential supply lines to be stabilized and hardly influenced by noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention is an improvement of a potential supply line for a compound semiconductor device.

(Prior Art) In recent years, large-scale integrated circuits (LSIs) have been widely used in important parts of computers and power supply devices.

These LSIs are formed by integrating field effect transistors, resistors, etc. on a semiconductor substrate several millimeters square. In particular, this substrate is made of a compound semiconductor such as InP or QaAs, which has an electron mobility several times higher than that of Sl at room temperature.
, II are attracting attention as having excellent high-speed performance. Among these LSIs, a widely known GaAs LSI is shown in FIG. 4 and will be explained.

FIG. 4(&) is a perspective view with the padding film removed. 4) and FIG. 4(e) are sectional views showing the AA' cross section and the BB' cross section of this perspective view, respectively.

First, the power supply line, which is one of the potential supply lines, connects the first layer wiring (6) for power supply and the second @ wiring (3) for power supply, which are formed directly on the GaAs substrate (t), with via metal (not shown). ).

This power line is connected to the pad (2).

The GND line, which is the other potential supply line, is also connected to the GNDm ill wiring (5) and the GND first layer 2 in the same way as the power supply line.
layer wiring) are connected by a via metal (8). This is also connected to the padded V dot (2) by a via metal (7).

In addition, (9) is a gate type field effect transistor (MES) formed in the element formation region (91).
(1 is the interlayer insulating film of sio.) By making LSI such a potential supply line structure, MESFET (
91) Power supply and GND potential can be equally supplied.

However, even though GaAs exhibits semi-insulating properties, it has been found that the league current generated between the first @ wiring for GND (5) and the first layer wiring for power supply (6) cannot be ignored. That is, due to this league current, the element formation region (9
The potential of the 2111st wiring (4) for GND formed to surround 1] and 9 increases on the Ov Yosu stamped on the pad, and the potential of the 2nd @ wiring (3) for power supply increases on the pad. The potential drops more than the applied power supply voltage. These potential fluctuations may amount to about 20% or more of the respective pad potentials.

Therefore, a potential lower or higher than the designed value is supplied to the element, resulting in malfunction of the element.

(Problems to be Solved by the Invention) As described above, conventional compound semiconductor devices have
Current leakage occurred between the potential supply lines formed on the 111i substrate and supplying different potentials, making it impossible to supply the desired potential to the element.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a compound semiconductor device that can suppress current leakage and supply a desired potential to an element f.

[Structure of the invention]

(Problem, Means for Solving the Problems) In order to achieve the above object, the present invention includes a semi-insulating compound semiconductor substrate, a first potential supply line formed on the substrate, and a semi-insulating compound semiconductor substrate. a second potential supply line formed adjacent to the first potential supply line; and a second potential supply line formed adjacent to the first potential supply line;
and a high resistivity region formed on the surface of the substrate between the potential supply lines. It is something.

(Function) The high resistivity region formed on the substrate surface between the first and second potential supply lines can suppress league current flowing along the substrate surface between the first and second potential supply lines. Furthermore, this high resistivity region plays a role similar to an insulating film interposed between the electrodes of a capacitor, further stabilizing the potential of each potential supply line, and thus reducing noise generated within the potential supply line.

(Example) The details of the present invention will be explained using examples.

FIG. 1 shows a cross section of a main part of a first embodiment of the present invention. This drawing shows an enlarged portion corresponding to FIG. 4(C) of the conventional example. Note that the same parts as in the conventional example will be described with the same numbers assigned.

The major difference from the conventional example is the first layer wiring for power supply (6)
and the GaAs substrate (1) between the first #1 wiring for GND (5)
The point is that the surface has a high specific resistance II (11). This layer is made by applying O ions to the surface of, for example, a QaAs substrate + 1) at an acceleration voltage of 100 KeV and a dose of 100 KeV.
This ion implantation process is carried out after the device is formed.This is because the heat treatment for activation during device formation causes the 0 ion implantation layer to This is because the specific resistance becomes low, which is undesirable.

Further, this high resistivity II (11) can also be formed by ion implantation of protons or B. In addition, any ion rod may be used as long as it forms a high specific resistance II) with respect to the substrate.

By providing this high specific resistance II (11), Ga
Leakage current flowing along the surface of the As substrate can be suppressed. Moreover, the high specific resistance +1 (11) forms a capacitor together with the first Ii11 wiring (6) for α source and the first - wiring (5) for GND, making the establishment of each potential supply line more stable. It can be made so that it is difficult to get on.

Next, the implementation sequence of fg2 of the present invention will be explained. The difference from the first embodiment is that the high resistivity layer is replaced by the first layer wiring (6) for the soldering source.
and Ga under each wiring of the first layer wiring for GND (5)
This is because it is formed so as to protrude from the surface of the As substrate into the GaAs substrate between the wirings. This effect is similar to that of the actual m-sequence that precedes this one.

Next, a third embodiment of the present invention will be described with reference to Figure 3. This involves digging grooves into the surface of the GaAs substrate (1),
Here, a PIN (1) is embedded as an insulator. Even in this case, the same effect as the first embodiment is achieved.In this case, an interlayer insulating film (1 By using a material having a higher dielectric constant than silicon oxide, such as silicon nitride, it is possible to stabilize the -1 potential and obtain an LSI with a noise raised to the power of v4.

Although the present invention uses a GaAs substrate, other compound semiconductors such as InP may also be used.

It should be noted that the present invention is not limited to the above embodiments, and can be implemented with various modifications without departing from the spirit thereof.

〔Effect of the invention〕

The groove bottom of the present invention can reduce potential fluctuations in the pad potential 711) caused by leakage current between the central supply lines.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the invention, FIG. 2 is a sectional view showing a second embodiment of the invention, and FIG. 3 is a sectional view showing a third embodiment of the invention. A sectional view shown. FIG. 4 is a diagram showing a conventional example. l... Semi-insulating GaAs substrate, 2... Pad, 3...
...21st wiring for power supply, 4...2nd @ wiring for GND,
5... 1st rf & wiring for GND, 6... 1st for power supply
Layer wiring, 7.8... Via metal, 9. . . . Element formation region, 10 . . . Interlayer insulating film, 11. 12 . . . Impurity injection layer, 13 .

Claims (1)

[Claims] (1) A semi-insulating compound semiconductor substrate, a first potential supply line formed on the substrate, and a second potential supply line formed on the substrate adjacent to the first supply line. , a high resistivity region formed on the surface of the substrate between the first and second potential supply lines.