JPH034327A - Central arithmetic processing unit - Google Patents

Abstract

PURPOSE:To reduce the kinds of succeeding operational codes and to reduce a hardware quantity by storing the instruction of conditions to change the execution condition of the instruction, etc., in a prebyte. CONSTITUTION:In the central arithmetic processing unit, the object is a processing system in which data called a prebyte 33 are fetched before the instruction composed of an operational code 31 and an operand 32, and the conditions of the execution condition in the central arithmetic processing unit, etc., is stored in the prebyte 33. When such an instruction format is executed, the action of the central arithmetic processing unit is indicated by the flow of a figure, the prebyte 33 is fetched in a cycle 1, and whether the conditions fetched in the cycle 1 are real or not is checked at the same time of the fetch of the operational code 31 in a cycle 2. When the conditions are real, the operand 32 to succeed to the operational code 31 is read in a cycle 3 and thereafter, the prescribed instruction execution is performed, and on the other hand, the above-mentioned conditions are not real, the cycle 3 is jumped, and the fetch of the next operational code is executed in a next cycle 1 '.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a central processing unit capable of reading specific data before instruction processing information.

[Conventional technology]

The instruction words handled by the central processing unit consist of an opcode and the operands that follow the opcode, including conditions and branches that change the execution state of the instruction. Control conditions for execution or non-execution of subroutines, etc.
Information is stored in the opcode or in the operand (post-byte) (called post-byte method).

[Problem to be solved by the invention]

Therefore, in the conventional instruction execution processing device as described above, the number of types of opcodes increases, the amount of hardware increases, and the instruction execution speed decreases because a cycle is required to read each of the above conditions. did. The present invention has been made to eliminate the above-mentioned problems, and an object of the present invention is to provide a central processing unit that can omit extra processing cycles without increasing the number of operation codes.

[Means to solve the problem]

A central processing unit according to a first aspect of the present invention is a central processing unit that can read specific information before instruction processing information, and is provided with a condition that the specific information changes the execution state of an instruction to be executed next. characterized by something. A central processing unit according to a second invention is a central processing unit that can read specific information before instruction processing information, and in which the specific information is used for branching, subroutine, etc. for the next instruction to be executed. It is characterized by being a condition for execution or non-execution.

【Example】

This invention will be explained below based on one embodiment. As shown in FIG. 3, the central processing unit of this invention has the following features:
The target is a processing system in which data called a prebyte 33 is fetched before an instruction consisting of an operation code 21 and an operand 32, and the prebyte 33 stores the conditions of the execution state in the central processing unit. With this instruction format, the operation of the central processing unit is to fetch the prebyte 33 in cycle l, fetch the opcode 31 in cycle 2, and simultaneously fetch the opcode 31 in cycle I, as shown in the flowchart in Figure 1. Check whether the fetched condition is true or not. If the condition is true, the operand 32 following the opcode 31 is read from cycle 3 onward, and the predetermined instruction is executed. On the other hand, if the condition is not true, cycle 3 is skipped and the next cycle 1' is executed. Fetch the next opcode. By performing such an operation, the central processing unit can select execution or non-execution of the instruction depending on the content of the condition. If such a condition is unnecessary, normal operation is achieved by fetching from the operation code of cycle 2 and executing with the condition always true. Next, the application of the subroutine will be explained with reference to the flow shown in FIG. An example program in this case is expressed in mnemonic representation as follows. ILD RO1234H2CEQ
JSR5UBI 3 LD RO100OH60ADR
RO#30H CEQ is a prebyte that indicates true if the Z flag (zero flag) is "BI", and JSR5UBI indicates an operand that makes a subroutine call to address 5UBI. In cycle 1, CEQ is fetched as a prebyte, and in cycle 2, it is fetched as an opcode. At the same time as fetching JSR, a check is made to see if there is a pre-byte, and a check is made to see if the Z flag is "BI". If there is no prebyte or the Z flag is “l”,
In cycle 3, the lower 8 bits of the address of 5UBI are fetched, in cycle 4, the upper 4 bits of the address are fetched, in cycle 5, the lower 8 bits of the program counter are saved to the stack, and in cycle 6, the lower 8 bits of the program counter are saved to the stack. Next, by setting the program counter to a value of 5UBI, 5UBI will be generated in the next cycle.
fetch the first instruction ADD. On the other hand, if there is a pre-byte and the Z flag is not 1, the instruction is not executed and the program counter is set to "3".
Add and fetch the next instruction LD. This operation results in 6 cycles when a subroutine call is executed and 2 cycles when it is not executed, and the processing time is shortened when it is not executed. Note that in the case of a normal JSR without conditions, by programming without adding CEQ and by taking in the opcode without pre-byte, it becomes equivalent to starting from cycle 2.

【Effect of the invention】

As explained above, this invention stores instructions such as conditions that change the execution state of the instruction in the prebyte, so the types of subsequent opcodes can be reduced and the amount of hardware can be reduced. Since the conditions can be determined based on the above information, no extra processing cycles are required, and processing speed can be increased.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a flowchart showing an example of processing for changing the execution state of instructions by the central processing unit of the present invention, and FIG. 2 is a flowchart showing an example of processing including subroutine processing.
FIG. 3 is a diagram showing the structure of command words used in the present invention. 3I...Opcode, 32...Operand, 33...Prebyte.

Claims (2)

[Claims] (1) A central processing unit capable of reading specific information before instruction processing information, wherein the specific information is a condition for changing the execution state of the next executed instruction. Device. (2) In a central processing unit that can read specific information before instruction processing information, the specific information is a condition for execution or non-execution of a branch, subroutine, etc. for the next instruction to be executed. A central processing unit characterized by: