JPH0342873A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0342873A JPH0342873A JP17850989A JP17850989A JPH0342873A JP H0342873 A JPH0342873 A JP H0342873A JP 17850989 A JP17850989 A JP 17850989A JP 17850989 A JP17850989 A JP 17850989A JP H0342873 A JPH0342873 A JP H0342873A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- source
- drain
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野】
本発明は、半導体装置に関し、特に電界効果型トランジ
スタ構造に関する。
〔従来の技術１
従来の溝掘りを利用した電界効果型トランジスタ（以降
、ＭＯＳＦＥＴと称す）構造は、第２図に示すように、
半導体基板上に溝を掘り、半導体基板（以降、ウェハー
と称す）平面に対して垂直な面にゲート電極を形成し、
ウェハーに平行な面にソース／ドレインを形成していた
。
〔発明が解決しようとする課題１
しかし、前述の従来技術では、ゲーｔ−ｉ極は、ウェハ
ー平面に対して垂直な面に形成され、ＭＯＳＦＥＴの面
積を小さくできるものの、ソース／ドレイン領域は、ウ
ェハー平面と平行な面に形成されていたため、集積化に
対して、大きな効果を上げることができなかった。
そこで、本発明は、このような課題を解決するもので、
その目的とするところは、ソース／ドレイン領域の面積
を低減することによって、集積化を可能としたＭＯＳ・
ＦＥＴの構造を提供するところにある。
【課題を解決するための手段］
本発明の半導体装置は、半導体基板上に形成された第１
の溝の底面に、更に第２の溝を形成し、前記第１の溝の
側面と前記第２の溝の側面にドレインまたはソースを形
成し、前記第１の溝の側面と前記第２の溝の側面との間
の前記第１の溝の底面上にゲート絶縁膜を介してゲート
電極を形成したことを特徴とする。
〔作 用１
本発明の上記の構造によれば、ソース／ドレイン領域は
、ウェハー平面に対して垂直な面に形成されるためウェ
ハー平面上において占める面積は非常に小さい、一般的
にゲート電極の占める面積より、ソース／ドレイン領域
の占める面積の方が大きいため、ゲート電極の面積を縮
小するより、ソース／ドレイン領域の面積を縮小する方
が、より面積の縮小化が画れる。
［実 施 例］
第１図は、本発明の一実施例における断面図であり、以
下に製造方法について順次説明していく。
まず、ウェハー表面を写真食刻法により、第１の溝を形
成する領域を開口する。
次に、エツチングガスとしてＣＦ、（四フッ化炭素）を
用い、圧力２５Ｏｍｔｏｒｒ下において、２５０Ｗのパ
ワーの条件でシリコン基板をエツチングし、第３図（２
）の構造を得る。
そして、再度、写真食刻法により、第２の溝を形成する
領域を開口する。次に、第１の溝を形成する時と同様に
、エツチングガスＣＦ４を用い、圧力２５０ｍｔｏｒｒ
下において、２５０Ｗのパワーで、シリコン基板をエツ
チングし、第２の溝を形成し、第３図（ｂ）に示す構造
を得る。
それから、１１００℃の酸素雰囲気中で、約１０分間の
熱酸化を行ない約３００六のシリコン酸化膜１０８を形
成した後、トランジスタのしきい値電圧の調整のために
、Ｂ（ボロン）をイオン注入する。
次いでＣＶＤ法により、全面に約４０００Ａの多結晶性
シリコン膜を堆積させた後、Ａｓ（ヒ素）イオンをエネ
ルギー６０ｋｅＶ、ドーズ量８ｘｌＯ”ｃｍ−”の条件
でイオン注入を行なう。
それから、窒素雰囲気中で、１０４０℃１５秒のランプ
アニールを行なう。
そして、写真食刻法により、ゲート電極１０４以外の多
結晶性シリコンをＣＦ４によりドライエツチングし、第
３図（Ｃ）の構造を得る。
次に、Ａｓ（ヒ素）イオンをエネルギー１００ｋｅＶ、
ドーズ量８Ｘ１０”ｃｍ−”の条件でイオン注入を行な
い、第３図（ｄ）の構造となる。
次いで、第３図（ｅ）に示すようにＣＶＤ法により、層
間絶縁１１ｉ３０６としてＰＳＧ膜を形成した後、フッ
酸で等方エツチングを行ない、ソース／ドレインである
第１の溝の側面を開口する。
そして、ＡＲ（アルミニウム）をスパッタしたのち、写
真食刻法によるアルミ配線１０５のパクーニングを行な
い、第３図（ｆ）の構造を得る。
最後に、シリコン酸化膜のパッシベーション１０７を堆
積し、第１図のＭＯＳＦＥＴ構造を得る。
このように、構成されたＭＯＳＦＥＴは、ソース／ドレ
イン領域をウェハー平面に対して垂直な面に形成される
ため、一つのＭＯＳＦＥＴの面積を考えた場合、小面積
で形成できる。
［発明の効果〕
以上、述べたように本発明によれば、従来のＭＯＳＦＥ
Ｔ構造より、小面積で形成可能なため、高集積化が可能
となる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a field effect transistor structure. [Conventional technology 1] The conventional field effect transistor (hereinafter referred to as MOSFET) structure using trenching is as shown in Fig. 2.
A trench is dug on the semiconductor substrate and a gate electrode is formed on a plane perpendicular to the plane of the semiconductor substrate (hereinafter referred to as wafer).
The source/drain was formed on a plane parallel to the wafer. [Problem to be Solved by the Invention 1] However, in the prior art described above, although the gate t-i pole is formed on a plane perpendicular to the wafer plane and the area of the MOSFET can be reduced, the source/drain region is Since it was formed on a plane parallel to the wafer plane, it was not possible to achieve a great effect on integration. Therefore, the present invention is intended to solve such problems,
The purpose of this is to reduce the area of the source/drain regions to enable integration of MOS/Drain regions.
It provides the structure of the FET. [Means for Solving the Problems] A semiconductor device of the present invention includes a first semiconductor device formed on a semiconductor substrate.
A second groove is further formed in the bottom surface of the groove, a drain or a source is formed on the side surface of the first groove and the side surface of the second groove, and a drain or source is formed on the side surface of the first groove and the second groove. The present invention is characterized in that a gate electrode is formed on the bottom surface of the first trench between the side surfaces of the trench and a gate insulating film therebetween. [Function 1] According to the above structure of the present invention, the source/drain region is formed on a plane perpendicular to the wafer plane, so the area occupied on the wafer plane is very small. Since the area occupied by the source/drain region is larger than the area occupied by the source/drain region, the area can be reduced more by reducing the area of the source/drain region than by reducing the area of the gate electrode. [Example] FIG. 1 is a cross-sectional view of an example of the present invention, and the manufacturing method will be sequentially explained below. First, a region where a first groove will be formed is opened on the wafer surface by photolithography. Next, using CF (carbon tetrafluoride) as an etching gas, the silicon substrate was etched under a pressure of 25 Omtorr and a power of 250 W.
) to obtain the structure. Then, the area where the second groove will be formed is opened again by photolithography. Next, in the same way as when forming the first groove, etching gas was used at a pressure of 250 mtorr.
Below, the silicon substrate is etched with a power of 250 W to form a second groove, resulting in the structure shown in FIG. 3(b). After that, thermal oxidation was performed for about 10 minutes in an oxygen atmosphere at 1100° C. to form a silicon oxide film 108 of about 300° C., and then B (boron) was ion-implanted to adjust the threshold voltage of the transistor. do. Next, a polycrystalline silicon film of approximately 4000 A is deposited on the entire surface by CVD, and then As (arsenic) ions are implanted at an energy of 60 keV and a dose of 8xlO cm-. Then, lamp annealing is performed at 1040° C. for 15 seconds in a nitrogen atmosphere. Then, by photolithography, the polycrystalline silicon other than the gate electrode 104 is dry-etched with CF4 to obtain the structure shown in FIG. 3(C). Next, As (arsenic) ions were irradiated with an energy of 100 keV.
Ion implantation is carried out at a dose of 8.times.10"cm.sup.-", resulting in the structure shown in FIG. 3(d). Next, as shown in FIG. 3(e), a PSG film is formed as an interlayer insulator 11i306 by the CVD method, and then isotropic etching is performed with hydrofluoric acid to open the side surfaces of the first trenches that are the source/drain. . After sputtering AR (aluminum), the aluminum wiring 105 is patterned by photolithography to obtain the structure shown in FIG. 3(f). Finally, a passivation film 107 of silicon oxide is deposited to obtain the MOSFET structure shown in FIG. Since the MOSFET thus configured has its source/drain regions formed in a plane perpendicular to the wafer plane, it can be formed with a small area when considering the area of one MOSFET. [Effects of the Invention] As described above, according to the present invention, the conventional MOSFE
Since it can be formed in a smaller area than the T structure, higher integration is possible.
第１図は、本発明のＭＯＳＦＥＴ構造の断面図。
第２図は、従来の満掘り技術を用いたＭＯＳＦＥＴ構造
の断面図。
第３図は、本発明のＭＯＳＦＥＴの製造方法の一例を製
造順に沿った断面図。
１０１．２０１．３０１・・・シリコン基板１０２、１
０３、２０２、２０３、３０２．３０３・・・・・・・
・・ ・・ソース／ドレイン
１０４．２０４．３０４・・・ゲート電極１０５．２０
５．３０５・・・アルミ配線１０６．
１０７．
１０８．
３０６ ・ ・ ・ ・ ・ ・
２０７．
３０７ ・
２０８．
３０８ ・ ・
・層間絶縁膜
・パッシベーショ
ン膜
・ゲート絶縁膜
以
上FIG. 1 is a cross-sectional view of the MOSFET structure of the present invention. FIG. 2 is a cross-sectional view of a MOSFET structure using conventional full-hole technology. FIG. 3 is a cross-sectional view showing an example of the method for manufacturing a MOSFET according to the present invention along the manufacturing order. 101.201.301...Silicon substrate 102, 1
03, 202, 203, 302.303...
... Source/drain 104.204.304... Gate electrode 105.20
5.305...Aluminum wiring 106. 107. 108. 306 ・ ・ ・ ・ ・ 207. 307 ・208. 308 ・ ・ ・ Interlayer insulation film, passivation film, gate insulation film or more
Claims (1)
２の溝を形成し、前記第１の溝の側面と前記第２の溝の
側面にドレインまたはソースを形成し、前記第１の溝の
側面と前記第２の溝の側面との間の前記第１の溝の底面
上にゲート絶縁膜を介してゲート電極を形成したことを
特徴とする半導体装置。A second groove is further formed in the bottom surface of the first groove formed on the semiconductor substrate, a drain or a source is formed on a side surface of the first groove and a side surface of the second groove, and a drain or a source is formed on a side surface of the first groove and a side surface of the second groove. 1. A semiconductor device, wherein a gate electrode is formed on a bottom surface of the first trench between a side surface of the first trench and a side surface of the second trench, with a gate insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17850989A JPH0342873A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17850989A JPH0342873A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342873A true JPH0342873A (en) | 1991-02-25 |
Family
ID=16049714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17850989A Pending JPH0342873A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342873A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324673A (en) * | 1992-11-19 | 1994-06-28 | Motorola, Inc. | Method of formation of vertical transistor |
| US6894343B2 (en) | 2001-05-18 | 2005-05-17 | Sandisk Corporation | Floating gate memory cells utilizing substrate trenches to scale down their size |
| US6936887B2 (en) | 2001-05-18 | 2005-08-30 | Sandisk Corporation | Non-volatile memory cells utilizing substrate trenches |
-
1989
- 1989-07-11 JP JP17850989A patent/JPH0342873A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324673A (en) * | 1992-11-19 | 1994-06-28 | Motorola, Inc. | Method of formation of vertical transistor |
| US5414288A (en) * | 1992-11-19 | 1995-05-09 | Motorola, Inc. | Vertical transistor having an underlying gate electrode contact |
| US6894343B2 (en) | 2001-05-18 | 2005-05-17 | Sandisk Corporation | Floating gate memory cells utilizing substrate trenches to scale down their size |
| US6936887B2 (en) | 2001-05-18 | 2005-08-30 | Sandisk Corporation | Non-volatile memory cells utilizing substrate trenches |
| US7087951B2 (en) | 2001-05-18 | 2006-08-08 | Sandisk Corporation | Non-volatile memory cells utilizing substrate trenches |
| US7491999B2 (en) | 2001-05-18 | 2009-02-17 | Sandisk Corporation | Non-volatile memory cells utilizing substrate trenches |
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