JPH0341854B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an access priority control method, and particularly to an access priority control method that accepts and processes access requests from a plurality of access sources according to a predetermined duty. This concerns the control method.

[Problems to be solved by conventional technology and invention]

Traditionally, from multiple access sources such as CPU (Central Processing Unit) and CHP (Channel Processing Unit)
Access requests (REQ) to the MSU (main storage unit) are comprehensively controlled by the MCU (main storage control unit), and the optimal system that matches the intended use is fixedly configured at the time of design etc. has been done. For example, when access requests from multiple access sources conflict, priority is set so that the CHP, which accesses the main memory less frequently, receives access requests preferentially than the CPU. Settings are being made.

However, in actual operation, if the frequency of processing access requests from the CPU becomes too high, the cycle time of the CPU is twice that of the CHP. Due to the decrease in the processing capacity of the MCU in response to requests, processing data may be lost within a certain time interval.
There was a problem in that so-called overruns, which were not sent back to the CHP, occurred, making it difficult to perform normal data transfer. Also,
There was a problem in that if access requests from the CHP were prioritized and processed too frequently, the data processing speed executed by the CPU would decrease. As described above, there is a problem in that the processing speed of the computer system as a whole decreases unless control is executed to appropriately accept access requests notified from the access source in accordance with the actual situation.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention accepts each access request from a plurality of access sources with a predetermined duty, and processes each received access request. This enables efficient access processing that matches the purpose of use. Therefore, in the access priority control method of the present invention, in a storage control device that processes access requests to a storage device notified from a plurality of access sources, the access priority control method according to the present invention an access request receiving unit that accepts requests for a predetermined period of time at predetermined sequential timings for each generation source; and an access request holding unit that stores the access requests accepted by the access request receiving unit in association with the access request source. and a priority determining unit that determines the priority of an access request to the storage device based on the access request held by the access request holding unit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of the present invention shown in FIG. 1, and FIG. 3 is an explanatory diagram for explaining a conventional access request.

In the figure, 1-1 to 1-4 are access sources,
2 is MCU (memory control unit), 3-1 to 3-4
is a port, 4 is a duty setting section, 4-1 or 4-4 is an AND circuit, 5 is an access request holding section,
5-1 to 5-4 are latch, 5-5 to 5-
8 is an OR circuit, 6-1 is a priority determining section,
6-2 is a pipeline processing unit, 7-1 is a 4-bit down counter, 7-2 is a decoder, and 8 is an MSU.
Ports 9-1 to 9-4 represent MSUs (main storage units).

In FIG. 1, 1-1 to 1-4 are access generation sources, for example, as shown in the figure, the CPU
(0), CPU(1), CHP(0) and CHP(1), respectively. The REQ signals, which are access requests notified by the access sources 1-1 to 1-4, are each
It is once received by each port 3-1 to 3-4 provided in the MCU 2. and,
The accepted REQ signal is searched at predetermined time intervals by the duty setting unit 4 as described later, and the searched REQ signal is applied to the latches 5-1 to 5-5 in the illustrated access request holding unit 5.
4 and the priority determining unit 6-
1 to determine priority. In addition, the REQ signal stored in each latch 5-1 to 5-4 is used when the access request based on the searched REQ signal cannot be prioritized for some reason (for example, due to a conflict with other access requests). (if the bank used by the preceding memory access request is busy and cannot be taken), or if the access request being processed by the pipeline processing unit 6-2 is prioritized and is canceled and the process is restarted. There are cases. At this time, the REQ signals stored in the latches 5-1 to 5-4 are sent to the priority determining section 6-1 to determine the priority order. Next, the pipeline processing section 6-2
MSU port 8 is processed sequentially based on a predetermined priority order by
1 to 9-4 are accessed. In this way, access from access sources 1-1 to 1-4
Data is written to or read from MSUs 9-1 to 9-4 based on the REQ signal.

At this time, by providing a duty setting unit 4, the duty (time percentage) at which the access request notified from the access source 1-1 to 1-4 is accepted can be arbitrarily set from the outside in a manner consistent with the purpose of use. becomes possible. Furthermore, by providing the access request holding section 5, the priority determining section 6--
During a period in which the cycle of the REQ signal notified to the bank busy signal is not accepted by the priority determining unit 6-1, for example, when the access request to be processed in advance is synchronized with the cycle of issuing the bank busy signal,
It is possible to prevent a situation in which reception of the REQ signal is continuously refused. In this way, by providing the duty setting section 4, the access request holding section 5, etc., the access request (REQ signal) notified from the access source 1-1 to 1-4 can be processed.
The duties are assigned and processed in a manner that maximizes the efficiency of the computer system.

In the figure, a 4-bit down counter 7-1 and a decoder 7-2 output an enable signal EN having a predetermined duty time at predetermined time intervals to be supplied to the AND circuits 4-1 to 4-4 in the duty setting section 4. It is used to generate ₀ to EN ₃ , etc. By inputting a clock signal (not shown) to the 4-bit down counter 7-1, enable signals _EN0 to _EN3 , which are output signals from the decoder 7-2, are circulated to the AND circuit 4-1.
1 to 4-4. As a result, it is once accepted on ports 3-1 to 3-4.
The REQ signal is the illustrated enable signal EN ₀ to EN ₃
The latch 5-
1 to 5-4 and sent to the priority determining section 6-1. On this occasion,
When starting up the MCU2, or externally as required, use the indicated OPSR (reset signal at startup).
By setting an arbitrary initial value to the 4-bit down counter 7-1 using
Enable signal output from EN ₀ to EN ₁₅
The duty can be set to a desired value.

For example, by setting the initial value to "3",
The 4-bit down counter 7-1 is “3-2-
1-0" is repeatedly counted, enable signals EN ₀ to EN ₃ having a duty of 25% can be obtained as shown in FIG. 2.
If the REQ signal is accepted at the ports 3-1 to 3-4 within the 25% duty time interval, the AND circuit 4 in the duty setting unit 4 to which the enable signal EN ₀ to EN ₃ has been notified −
1 to 4-4 notify the REQ signal to the latches 5-1 to 5-4 and also to the priority determining section 6-1. At this time, the individual duties of the enable signals EN ₀ to EN ₃ to be notified to the AND circuits 4-1 to 4-4 can also be arbitrarily set as necessary. For example, if the initial setting of the 4-bit down counter 7-1 is "4", and
The logical sum signal of EN ₀ and EN ₁ is notified to the AND circuit 4-1, and the mode is different from that shown in the figure.
AND circuit 4-2 or 4 for EN ₂ or EN ₄ , respectively.
-4 by notifying the access source 1-
The duty for 1 is 40%, and the duty for other access sources 1-2 or 1-4 is 40%.
It can also be set to 20%. Furthermore, access source 1
The REQ signal notified from -1 to 1-4 is
The next item will not be accepted until the pipeline processing unit 6-2 determines that it will be processed reliably. Then, the REQ signal searched by the duty setting section 4 and the latches 5-1 to 5
The REQ signals stored in -4 are processed in the order in which they were searched, in the order in which they were received by the relevant latches 5-1 to 5-4, or in the order in which they were received at the same time, according to the priority set in advance. It is processed.

Next, the REQ notified from the conventional access source (CPU side or CHP side) shown in Figure 3
Examples of signals and signals representing processing states within the MCU will be briefly explained.

Graphical representation notified from the access source in the diagram
The REQ signal is illustrated by the port on the MCU side.
Accepted as REQ signal. If the REQ signal is accepted by the port, the
The PORT ACCEPT signal is generated and a graphical signal indicating that the REQ signal has been accepted is sent to the access source, and the graphical INT
PORT BUSY signal is set. As a result, even if the next REQ signal is notified from the access source, it will not be accepted. and,
The illustrated REQ signal received by the MCU side executes pipeline processing indicated using “T ₁ ”, “T ₂ ”, etc. following “P” in the figure based on predetermined data, address information, etc. in a form synchronized with the clock. Run it with At this time, the pipeline process that started execution based on the illustrated REQ signal etc. is “T ₂ ”
When the step reaches the position shown in the diagram and the state is established,
BUSY signal is released. Along with this, the illustration
The REQ signal is now ready to be accepted again. In addition, in response to the indicated REQ signal notified from the access originator, after the MCU side notifies the access originator of the indicated signal indicating that the indicated REQ signal has been received, the indicated REQ signal is sent at the next clock. will be reset.

In the conventional REQ signal reception method as described above,
The REQ signal sent to the MCU side first will be accepted, and as described above, the computer system as a whole may not be able to perform efficient processing. For this reason, for example, by providing the duty setting section 4 and the access request holding section 5 described using FIGS. 1 and 2 in the input section on the MCU side shown using the conventional signal example shown in FIG. , it is possible to appropriately process the REQ signal notified from the access source with a duty that matches the aspect of the computer system, thereby improving the efficiency of the entire computer system.

〔Effect of the invention〕

As explained above, according to the present invention, each access request received from a plurality of access sources is received with a predetermined duty, and each of the received access requests is sequentially processed. Therefore, efficient access processing can be performed that matches the purpose of use of the computer system, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of the present invention shown in FIG. 1, and FIG. 3 is an explanatory diagram for explaining a conventional access request. In the figure, 1-1 to 1-4 are access sources,
2 is MCU (memory control unit), 3-1 to 3-4
is a port, 4 is a duty setting section, 4-1 or 4-4 is an AND circuit, 5 is an access request holding section,
5-1 to 5-4 are latch, 5-5 to 5-
8 is an OR circuit, 6-1 is a priority determining section,
6-2 is a pipeline processing unit, 7-1 is a 4-bit down counter, 7-2 is a decoder, and 8 is an MSU.
Ports 9-1 to 9-4 represent MSUs (main storage units).

Claims (1)

[Scope of Claims] 1. In a storage control device that processes access requests to a storage device notified from a plurality of access sources, the access requests notified from the plurality of access sources are processed in advance for each access source. an access request receiving unit that accepts requests for a predetermined period of time at predetermined sequential timings; an access request holding unit that stores access requests accepted by the access request receiving unit in association with access request sources; and the access requests. 1. A priority control method, comprising: a priority determining unit that determines the priority of an access request to a storage device based on an access request held by a holding unit. 2. The access priority control method according to claim 1, wherein the access request reception unit includes means for determining the predetermined timing and predetermined time.