JPH0341490Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a multilayer printed wiring board in which a plurality of printed wiring boards are laminated in a predetermined order.

(Prior Art) In recent years, with the demand for electronic devices to be smaller and lighter, multi-functional, faster processing, and more reliable, various types of electronic devices have been developed, for example, as shown in Figure 6. Multilayer printed wiring boards in which a plurality of printed wiring boards (for example, six) are laminated in a predetermined order are widely used. In addition, in FIG. 6, A indicates an insulating substrate, and B indicates a conductive layer.

By the way, such a multilayer printed wiring board is
Unlike double-sided printed wiring boards, it is difficult to visually inspect inner printed wiring boards, which may cause omissions in the inner printed wiring boards or errors in the order of stacking the inner printed wiring boards.

As a result, if the inner layer printed wiring board is not laminated, it will become inoperable, and if the inner layer printed wiring board is laminated in the wrong order, it will work, but the electrical circuit conditions such as characteristic impedance etc. Since the value differs from the design value, sufficient performance may not be achieved.

Therefore, as a countermeasure against layer dropout of the inner layer printed wiring boards, for example, as shown in FIGS. A predetermined area is allocated to each area, and each area has an identification symbol pattern P ₁ to _{P 6} to distinguish it from other printed wiring boards.
(for example, lamination numbers 1 to 6) are provided so as to be visible to the outside.

As a result, when six printed wiring boards 1 to 6 are stacked, the identification symbol patterns P ₁ to P _{6 of each printed wiring board 1 to 6} can be read from the common portion C as shown in FIG. 8a. However, for example, if the fourth printed wiring board 4 is missing, the identification symbol pattern _P4 of the fourth printed wiring board 4 can be read from the common part C as shown in FIG. 8b. This makes it possible to visually inspect whether or not the inner layer printed wiring board is missing.

(Problem to be solved by the invention) However, according to such a conventional configuration, six printed wiring boards 1 to 6 are stacked regardless of whether or not there is a mistake in the stacking order of the inner layer printed wiring boards. In this case, the identification symbol patterns P ₁ to _{P 6} of each printed wiring board 1 to 6 can always be read from the common portion C as shown in FIG. It is not possible to visually inspect the presence or absence of

The present invention focuses on these points, and its purpose is to provide a multilayer printed wiring board that can visually inspect not only missing layers in the inner printed wiring board but also errors in the stacking order of the inner printed wiring boards. It's about doing.

(Means for Solving the Problems) The present invention that achieves the above purpose is a multilayer printed wiring board in which a plurality of printed wiring boards are laminated in a predetermined order. A predetermined area is allocated to each printed wiring board, and each area has an identification symbol pattern for distinguishing it from other printed wiring boards and an identification symbol pattern of other printed wiring boards according to the stacking order. A mask pattern is provided for selective masking, and when these printed wiring boards are laminated in a predetermined order, the identification symbol pattern of each printed wiring board in the common part can be read, and when laminated in a different order, the identification symbol pattern of each printed wiring board can be read. is characterized in that the identification symbol patterns of printed wiring boards in different orders are masked so that they cannot be read.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, and the same parts as in FIG. 7 are given the same reference numerals. In FIG. 1, a predetermined area is allocated to each printed wiring board 1 to 6 in a common portion C of the laminated printed wiring boards 1 to 6, and the area is divided into a similar area as in FIG. 7. Identification symbol patterns P ₁ to _{P 6} (for example, lamination numbers 1 to 6) are provided so as to be visible to the outside to distinguish them from other printed wiring boards, and identification symbol patterns of other printed wiring boards are set in the lamination order. Mask patterns M ₂ to _{M 6} are provided for selectively masking according to the following. That is, assuming that six printed wiring boards 1 to 6 are stacked in order from the top according to the stacking numbers 1 to 6 as in FIG. Only the identification symbol pattern P ₁ is provided in the area, and the identification symbol pattern P ₂ and the identification symbol pattern P 1 of the uppermost printed wiring board 1 are provided in a predetermined area of the common portion C of the second printed wiring board _2. Mask pattern M ₂ to mask
An identification symbol pattern P 3 is provided in a predetermined area of the common portion C of the third printed wiring board 3 and identification symbol patterns P ₁ , P of the uppermost _printed wiring board 1 and the second printed wiring board 2 are provided. A mask pattern _M3 is provided for masking the identification symbol pattern _P4 and the third printed wiring boards 3 from the top layer printed wiring board 1 in a predetermined area of the common portion C of the fourth printed wiring board 4 _. Mask pattern _M4 that masks the identification symbol patterns _P1 to _P3 up to
are provided in a predetermined area of the common portion C of the fifth printed wiring board 5, and an identification symbol pattern P ₅ from the top layer printed wiring board 1 to the fourth printed wiring board ₄ are provided. A mask pattern _M5 for masking _P4 is provided in a predetermined area of the common portion C of the sixth printed wiring board 6, and an identification symbol pattern _P6 and the fifth printed wiring boards from the top layer printed wiring board 1 are provided. A mask pattern _M6 is provided for masking up to ₅ identification symbol patterns P1 to _P5 . In addition, these identification symbol patterns P ₁ to _{P 6} and mask patterns M ₂ to _{M 6}
can be formed as a conductor pattern in the same process as the circuit pattern.

In such a configuration, as shown in FIG. 2a, when the mask pattern M overlaps the identification symbol pattern P, the identification symbol pattern P is masked by the mask pattern M and becomes invisible, but as shown in FIG. 2b. When the identification symbol pattern P overlaps the mask pattern M, the identification symbol pattern P is not masked by the mask pattern M and can be read.

Figures 3 to 5 show six printed wiring boards 1 to 6.
Lamination example and identification symbol pattern P from common part C
FIG.

In FIG. 3, the printed wiring boards 1 to 6 are stacked in a predetermined order as shown in a, and each printed wiring board 1 provided in a common portion C of each
-6 identification symbol patterns _P1 to _P6 can be read as shown in b.

On the other hand, in FIG. 4, the third printed wiring board 3 and the fourth printed wiring board 4 are stacked in reverse, as shown in a. In this case, as shown in b, the identification symbol pattern P ₃ of the third printed wiring board 3 is masked by the mask pattern M ₄ of the fourth printed wiring board 4 and becomes unreadable.
Visual inspection for errors in stacking order is possible.

Furthermore, in FIG. 5, as shown in a, the second to fifth inner layer printed wiring boards 2 to 5 are "1".
-5-2-3-4-6'' is shown. In this case, as shown in b, the identification symbol patterns P ₂ to P 4 of the second to fourth printed wiring boards 2 to ₄ are masked with the mask pattern M ₅ of the fifth printed wiring board 5 and cannot be read. This allows visual inspection for errors in the stacking order.

In addition, in the above embodiment, an example was explained in which the lamination number is used as the identification symbol pattern of each printed wiring board, but any symbol may be used as long as each printed wiring board can be distinguished from other printed wiring boards. Good too.

Further, the maximum number of laminated layers of the printed wiring board is determined depending on the light transmittance of the insulating substrate of the printed wiring board, and is not limited to six layers.

(Effects of the invention) As explained above, according to the invention, it is possible to realize a multilayer printed wiring board that can visually inspect not only omissions in the lamination of the inner layer printed wiring board but also errors in the stacking order of the inner layer printed wiring board, and to put it into practical use. The above effect is significant.

[Brief explanation of the drawing]

Fig. 1 is a structural explanatory diagram showing a specific example of a printed wiring board used in the present invention, Fig. 2 is an explanatory diagram of the operation of the present invention, and Figs. 3 to 5 are structural explanatory diagrams showing specific examples of the present invention. , FIG. 6 is a structural explanatory diagram showing an example of a multilayer printed wiring board, FIG. 7 is a structural explanatory diagram showing an example of a conventional countermeasure against lamination omission, and FIG. 8 is an explanatory diagram of the operation of FIG. 1 to 6 printed wiring board, C...common part, P...identification symbol pattern, M...mask pattern.

Claims (1)

[Scope of utility model registration request] In a multilayer printed wiring board in which a plurality of printed wiring boards are laminated in a predetermined order, a predetermined area is assigned to each printed wiring board to the common part of the stacked printed wiring boards. is provided with an identification symbol pattern for distinguishing it from other printed wiring boards and a mask pattern for selectively masking the identification symbol pattern of other printed wiring boards according to the stacking order, and these printed wiring boards are stacked in a predetermined order. When laminated in a different order, the identification symbol pattern of each printed wiring board in the common area can be read, and when laminated in a different order, the identification symbol pattern of the printed wiring boards in a different order is masked and cannot be read. A multilayer printed wiring board characterized by: