JPH0340937B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for annealing semiconductor wafers.

In recent years, research and development has been actively conducted on discrete FETs, digital integrated circuits, and analog integrated circuits using compound semiconductors such as GaAs. In this case, one of the important research issues is to reduce the gate-source parasitic resistance and gate-drain parasitic resistance of Schottky barrier gate field effect transistors (MESFETs), which are commonly used as active devices. It is. There are several approaches to reducing this parasitic resistance, but the most commonly used method is self-aligned ion implantation of the n ⁺ layer using a heat-resistant gate metal as a mask, which is relatively easy to manufacture. It is being In this method, after ion-implanting the n ⁺ layer, it is necessary to perform annealing at a high temperature of around 800°C with the gate metal attached to activate the ion-implanted layer. Therefore, heat resistance is required for the gate metal, and TiW, TiW silicide, WAl, W
Heat-resistant metals such as these are used as gate metals. However, there is a problem in that the heat resistance of these metals is not necessarily sufficient. Furthermore, these so-called heat-resistant metals have higher resistance and lower reliability than Al, which is widely used as a gate metal (Al has no heat resistance).

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for annealing a semiconductor wafer, which can activate an ion-implanted layer even when a non-heat-resistant metal such as Al is attached.

That is, in the present invention, when annealing the selective ion implanted layer using monochromatic light, ε _r =120Π/Z _l (where Z _l is the electromagnetic wave of the semiconductor into which the selective ions are implanted) A semiconductor wafer characterized by being provided with a film having a relative dielectric constant ε _r thickness (2n+1)/4λ ₀ (where n=0, 1, 2..., λ ₀ is the wavelength) expressed by the relationship (impedance). In the annealing method and during annealing of the selective ion implantation layer using monochromatic light, ε _r
= 120Π/Z _l (where Z _l is the electromagnetic wave _impedance of the semiconductor into _which selective ions have been implanted)
, 1, 2..., λ ₀ is the wavelength), and the conductivity of the first film is arbitrary, and the thickness is (n+1)/2λ ₀ (n=0, 1, 2...). This is a semiconductor wafer annealing method characterized by providing a second film and further providing only the second film in a portion other than the selective ion implantation layer.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1 and 2 are diagrams for explaining the principle of the present invention. In FIG. 1, media 1, 2, and 3 whose electromagnetic wave impedances are Z ₀ , Z, and Z _l are arranged in contact with each other. The thickness of the medium 2 is 1/4 of the wavelength of the electromagnetic wave incident from the medium 1 side. On the other hand, in FIG. 2, media 6, 7, and 8 whose electromagnetic wave impedances are Z ₀ , Z, and Z _l are arranged in contact with each other.
The thickness of medium 2 is 1/2 of the incident wavelength. In Fig. 1, the impedance Z' when looking at the medium 2 side from the interface 4 between media 1 and 2 is Z'=ZZ _l cos2π/λl+jZsin2π/λl/Zcos2π/
It can be expressed as λl+jZ _l sin2π/λl(1). However, l is the length of the medium 2, and λ is the wavelength in the medium 2. As is clear from equation (1), l=
When λ/4, Z′=Z ² /Z _l (2). Here, if the relationship Z ₀ =Z' (3) or Z=√ _{0 l} (4) holds, so-called impedance matching occurs, all of the energy incident on medium 1 is transmitted to medium 3. If the relative permittivity of medium 2 is ε _r , the permittivity in vacuum is ε ₀ , the relative permittivity of medium 2 is μ _r , and the magnetic permeability in vacuum is μ ₀ , becomes. μ _r is usually 1. In equation (4), if Z ₀ is the electromagnetic wave impedance in vacuum, Therefore, from equations (4), (5), and (6), it can be seen that impedance matching occurs when ε _r = 120π/Z _l (7).

On the other hand, if the length of the medium 2 is λ/2, the impedance Z'' when looking from the interface 9 to the medium 2 side is Z''=Z _l (8) from equation (1). In this case, impedance matching does not occur,
At the interface 9, the electromagnetic wave is reflected toward the light source with a reflection coefficient Γ Γ=Z _l −Z ₀ /Z _l +Z ₀ (9).

FIG. 3 is a diagram showing a first embodiment of the present invention. In the figure, a GaAs substrate 11 has an n-layer 12 activated in advance by ion implantation.
Further, on the surface of the GaAs substrate 11, a film 14 having a dielectric constant of 120π/ _Zl and a thickness of λ/4 is provided. Also
In GaAs substrate 11 there is an n ⁺ region implanted through film 14 using gate metal 15 as a mask. Planar electromagnetic waves 16 from a light source are incident 17 on the surface of the GaAs substrate 11 in the form of monochromatic light. The energy of electromagnetic waves is efficiently transmitted to the lower part of the membrane 14,
Heat the n ⁺ region and activate the n ⁺ region. On the other hand, since the impedance of the portion to which the film 14 is not attached, that is, the gate metal 15 and the GaAs substrate 18, is very low, there is a large impedance mismatch between the substrate surface 18 and the spatial impedance of 120πΩ, and most of the incident energy is Since the light is reflected, the temperature of the gate metal 15 and the GaAs substrate surface 18 does not rise much.

FIG. 4 is a diagram showing a second embodiment of the present invention. In the figure, a GaAs substrate 21 has an n-layer 22 which has been ion-implanted and activated in advance. Also
A first film 24 having a dielectric constant of 120π/Z _l and a thickness of λ/4 is provided on the surface of the GaAs substrate 21 . Also
In the GaAs substrate 21, there is an n ⁺ region ion-implanted using the gate metal 25 as a mask. membrane 2
A second film 29 having a thickness of λ/2 is attached to cover the entire gate metal 25 and gate metal 25 . As explained in FIG. 2, the impedance seen through a λ/2 thick membrane is equal to the impedance seen not through the membrane. Therefore, even if the second film 29 is placed on the part where the first film 24 is attached, the impedance matching condition is satisfied, so that the electromagnetic wave energy is efficiently absorbed into the n ⁺ layer.
7 will be done. On the other hand, the gate metal 25 and GaAs surface 30 to which the first film 24 is not attached have only the second film 29 and have a very low impedance.
Even when viewed through the second film 29, the impedance is very low. Therefore, most of the incident electromagnetic wave energy is reflected 28 on the surface of the second film 29 and returns to the light source side, so that the gate metal 25
The temperature rise in the area will be extremely small.

In FIGS. 3 and 4, the substrates 11 and 21 are made of GaAs with a dielectric constant of 12.7, so in the case of low doping,
Z _l becomes 120Π/√12.7, and the optimal ε _r =3.56.

As described above, according to the invention, the electromagnetic wave energy emitted from the light source can be efficiently absorbed only by the selective ion implantation layer, so there is an advantage that the energy emitted from the light source can be small. Furthermore, according to the present invention, the electromagnetic wave energy emitted from the light source is efficiently absorbed only in the selective ion implantation layer, and in areas other than the selective ion implantation layer, the electromagnetic wave energy is absorbed into the components on the semiconductor wafer such as the gate metal. It can be reflected back to the light source before reaching the selective ion implantation layer, so the temperature rise in areas other than the selective ion implantation layer is small, and the ion implantation layer can be annealed even with non-heat resistant gate metal attached. It is something that you have.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining the principle of the present invention, and FIGS. 3 and 4 are cross-sectional views of a semiconductor wafer, respectively, for explaining an embodiment of the present invention. 1, 6, 7, 3, and 8 are media with electromagnetic wave impedances Z ₀ , Z, and Z _l , respectively; 11 and 21 are GaAs substrates;
14, 24, 29 are dielectric films, 12, 22 are n
Layers 13 and 23 are n ⁺ layers, 15 and 25 are gate metals, and 16 and 26 are monochromatic lights.

Claims (1)

[Claims] 1. On the selective ion implantation layer of the semiconductor wafer,
ε _r =120Π/Z _l (where Z _l is the electromagnetic wave impedance of the semiconductor into _which selective ions have been implanted) 2. A method for annealing a semiconductor wafer, which comprises providing a film (where λ is a wavelength) and annealing a selective ion implantation layer by irradiating electromagnetic wave energy emitted from a monochromatic light source from above the film. 2 ε _r on the selective ion implantation layer of the semiconductor wafer
= 120Π/Z _l (where Z _{l is} the electromagnetic wave impedance of the semiconductor into which selective ions have been implanted)
= 0, 1, 2..., λ is the wavelength) and a thickness of n+1/ on the first film with an arbitrary dielectric constant.
A second film of 2·λ (n=0, 1, 2...) is provided,
Semiconductor wafer annealing further comprises providing only the second film in a portion other than the selective ion implantation layer, and annealing the selective ion implantation layer by irradiating electromagnetic energy emitted from a monochromatic light source from above. Method.