JPH0138368B2 - - Google Patents
Info
- Publication number
- JPH0138368B2 JPH0138368B2 JP58121318A JP12131883A JPH0138368B2 JP H0138368 B2 JPH0138368 B2 JP H0138368B2 JP 58121318 A JP58121318 A JP 58121318A JP 12131883 A JP12131883 A JP 12131883A JP H0138368 B2 JPH0138368 B2 JP H0138368B2
- Authority
- JP
- Japan
- Prior art keywords
- electromagnetic wave
- film
- thin film
- ion implantation
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 235000012431 wafers Nutrition 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000000758 substrate Substances 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 3
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000035699 permeability Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Description
【発明の詳細な説明】
本発明は半導体ウエハーの選択アニール方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selectively annealing semiconductor wafers.
近年、GaAs等の化合物半導体を用いたデイス
クリートFET、デイジタル集積回路、アナログ
集積回路の研究開発が活発に行なわれている。こ
れらのデバイスにおいて、アクテイブ素子として
通常用いられているシヨツトキー障壁ゲート型電
界効果トランジスタ（MESFET）が有するゲー
ト・ソース間寄生抵抗およびゲートドレイン間寄
生抵抗を低減することが、研究の重要な課題の一
つとなつている。この寄生抵抗を低減するために
はいくつかのアプローチがあるが、製造プロセス
が比較的容易な、耐熱性ゲート金属をマスクとし
てn+層をセルフアラインでイオン注入する方法
が広く用いられている。この方法はn+層をイオ
ン注入した後にゲート金属を付けたまま、800℃
前後の高温でアニールを行い、イオン注入層の活
性化を行う必要がある。したがつてゲート金属に
は耐熱性が要求され、TiW、TiWシリサイド、
WAl、Ｗ等の耐熱性金属がゲート金属として採
用されている。しかしながら、これらの金属の耐
熱性は必ずしも十分でないという問題があつた。
さらにこれらのいわゆる耐熱性金属は、ゲート金
属として広く用いられているAlに比べて（Alに
は耐熱性はない）、抵抗が大きく、信頼性も劣る
という問題があつた。 In recent years, research and development of discrete FETs, digital integrated circuits, and analog integrated circuits using compound semiconductors such as GaAs have been actively conducted. One of the important research issues in these devices is to reduce the gate-source parasitic resistance and gate-drain parasitic resistance of Schottky barrier gate field effect transistors (MESFETs), which are commonly used as active elements. It's becoming one. There are several approaches to reducing this parasitic resistance, but the widely used method is to self-align ion implantation into the n + layer using a heat-resistant gate metal as a mask, which has a relatively easy manufacturing process. This method involves ion-implanting the n + layer and then heating it to 800°C with the gate metal attached.
It is necessary to perform annealing at high temperatures before and after to activate the ion-implanted layer. Therefore, the gate metal is required to have heat resistance, and TiW, TiW silicide,
Heat-resistant metals such as WAl and W are used as gate metals. However, there is a problem in that the heat resistance of these metals is not necessarily sufficient.
Furthermore, these so-called heat-resistant metals have higher resistance and lower reliability than Al, which is widely used as a gate metal (Al has no heat resistance).
本発明の目的は前記問題を解決し、Alのよう
に耐熱性のない金属を着けたままでもイオン注入
層の活性化を図ることができる半導体ウエハーの
選択アニール方法を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a selective annealing method for semiconductor wafers, which can activate an ion-implanted layer even when a non-heat-resistant metal such as Al is attached.
すなわち、本発明は半導体ウエハーの選択イオ
ン注入層の上に抵抗体薄膜を設け、さらにその上
にεr＝120π／Zl（ただしZlは抵抗体薄膜表面から下
部を見込んだ電磁波インピーダンス）の関係で表
わされる比誘電率εr、厚さ（2n＋１）／４λ（ただし
ｎ
＝０、１、２、………、λは波長）なる膜を設
け、その上方より単色光源より発せられる電磁波
エネルギーを照射して選択イオン注入層のアニー
ルを行う半導体ウエハーのアニール方法および該
選択イオン注入層の上に抵抗体の薄膜を設け、さ
らにその上にεr＝120π／Zl（ただしZlは抵抗体薄膜
表面から下部を見込んだ電磁波インピーダンス）
の関係で表わされる比誘電率εr、厚さ（2n＋１）／４
λ（ただしｎ＝０、１、２、………、λは波長）
なる第一の誘電体膜を設け、さらにその上に誘電
率は任意で厚さが（ｎ＋１）／２λ（ただしｎ＝０、
１、２、………）なる第二の誘電体膜を設け、選
択イオン注入層以外の部分には前記第二の誘電体
膜のみを設け、その上方より単色光源より発せら
れる電磁波エネルギーを照射して選択イオン注入
層のアニールを行う半導体ウエハーの選択アニー
ル方法である。 That is, in the present invention, a resistor thin film is provided on the selective ion implantation layer of a semiconductor wafer, and a resistor thin film is further provided on the resistor thin film with ε r =120π/Z l (where Z l is the electromagnetic wave impedance looking downward from the resistor thin film surface). Electromagnetic wave energy emitted from a monochromatic light source from above a film with relative dielectric constant ε r expressed by the relationship and thickness (2n+1)/4λ (where n = 0, 1, 2, ......, λ is the wavelength). A method of annealing a semiconductor wafer in which a selective ion implantation layer is annealed by irradiation with Electromagnetic wave impedance looking down from the surface of body thin membranes)
Relative permittivity ε r expressed by the relationship, thickness (2n + 1)/4 λ (where n = 0, 1, 2, ......, λ is the wavelength)
A first dielectric film having a dielectric constant of (n+1)/2λ (where n=0, 1, 2, . , a selective annealing method for a semiconductor wafer in which only the second dielectric film is provided in a portion other than the selective ion implantation layer, and the selective ion implantation layer is annealed by irradiating electromagnetic wave energy emitted from a monochromatic light source from above. be.
以下に本発明の実施例を図面と数式を用いて詳
述する。 Embodiments of the present invention will be described in detail below using drawings and mathematical formulas.
第１図および第２図は本発明の原理を説明する
ための図である。第１図において、電磁波インピ
ーダンスがそれぞれZp，Ｚであるような媒質１に
および２が互いに接して配列され、さらに媒質２
に抵抗体薄膜３が接し、抵抗体薄膜３には半導体
基板４が接している。媒質２と抵抗体薄膜３との
界面６から右側を見込んだ電磁波インピーダンス
をZlとすると、界面５から右側を見込んだ電磁波
インピーダンスZ′は
Z′＝ＺZlcos2n／λｌ＋jZsin2n／λｌ／Zcos2n／λｌ
＋jZlsin2n／λｌ(1)
と表わすことができる。ただしｌは媒質２の長
さ、λは媒質２中の波長である。(1)式から明らか
なようにｌ＝λ／４のとき
Z′＝Z2／Zl (2)
となる。ここでもし
Zp＝Z′ (3)
すなわち
Ｚ＝√p l (4)
の関係が成立するとき、インピーダンス整合が起
こり、媒質１に入射されたエネルギーは全て界面
６より右に伝送される。ただしTaの損失が大き
いため、電磁波のエネルギーの大半は抵抗体薄膜
３中で熱に変わる。ところで媒質２の比誘電率を
εr、真空中の誘電率をεp、媒質２の比透磁率を
μr、真空中の透磁率をμpとすると、
となる。μrは通常１である。(4)式においてZpを真
空中の電磁波インピーダンスとすると
であるから、(4)、(5)、(6)式より
εr＝120π／Zl (7)
のとき、インピーダンス整合が起こることが分
る。 FIGS. 1 and 2 are diagrams for explaining the principle of the present invention. In FIG. 1, media 1 and 2 are arranged in contact with each other and the electromagnetic wave impedances are Z p and Z, respectively, and the medium 2
A resistor thin film 3 is in contact with the resistor thin film 3, and a semiconductor substrate 4 is in contact with the resistor thin film 3. If the electromagnetic wave impedance looking to the right from the interface 6 between the medium 2 and the resistor thin film 3 is Zl , the electromagnetic wave impedance Z' looking from the interface 5 to the right is Z'=ZZ l cos2n/λl+jZsin2n/λl/Zcos2n/λl
+jZ l sin2n/λl(1). However, l is the length of the medium 2, and λ is the wavelength in the medium 2. As is clear from equation (1), when l=λ/4, Z'=Z 2 /Z l (2). Here, if the relationship Z p =Z' (3) or Z = √ p l (4) holds, impedance matching occurs and all the energy incident on the medium 1 is transmitted to the right from the interface 6. However, since the loss of T a is large, most of the energy of the electromagnetic wave is converted into heat in the resistor thin film 3. By the way, if the relative permittivity of medium 2 is ε r , the permittivity in vacuum is ε p , the relative magnetic permeability of medium 2 is μ r , and the magnetic permeability in vacuum is μ p , then becomes. μ r is usually 1. In equation (4), if Z p is the electromagnetic wave impedance in vacuum, then Therefore, from equations (4), (5), and (6), it can be seen that impedance matching occurs when ε r = 120π/Z l (7).
第２図において、電磁波インピーダンスがそれ
ぞれZp，Ｚ，Zlであるような３つの媒質１１，１
２および１３が接している。第２図において媒質
１２の長さをλ／２とすると(1)式より
Z′＝Zl (8)
となる。この場合、インピーダンス整合は起こら
ず、媒質１２を通しても媒質１３のインピーダン
スがそのまま見える。このときの界面１４におけ
る反射係数Γ
Γ＝Zl＋Zp／Zl＋Zp
をもつて電磁波は光源側へ反射する。 In Fig. 2, three media 11 and 1 whose electromagnetic wave impedances are Z p , Z and Z l respectively
2 and 13 are in contact. In FIG. 2, if the length of the medium 12 is λ/2, then Z'=Z l (8) from equation (1). In this case, impedance matching does not occur, and the impedance of the medium 13 is visible as it is even through the medium 12. At this time, the electromagnetic wave is reflected toward the light source with a reflection coefficient Γ Γ=Z l +Z p /Z l +Z p at the interface 14.
第３図は本発明の第１の実施例を示す図であ
る。図において、GaAs基板２１はあらかじめイ
オン注入した後アニールされ、活性化されたｎ層
２２を有する。またGaAs基板２１の表面にはZl
＝10ΩのTa薄膜２４および比誘電率εr＝120π／Zl≒
38で厚さがλ／４のチタン酸バリウム膜２５が設
けられている。またGaAs基板２１中にはゲート
金属２６をマスクとして膜２４および２５を通し
て注入されたn+領域（n+層）２３が存在する。
GaAs基板２１の表面には平面電磁波２７が入射
される。ゲート金属２６ではインピーダンスが低
いために電磁波は反射される。また膜２５が付け
られた部分では効率よく電磁波は吸収され、損失
の大きいTa膜２４中で熱に代わる。この熱によ
りn+層２３を活性化する。 FIG. 3 is a diagram showing a first embodiment of the present invention. In the figure, a GaAs substrate 21 has an n-layer 22 which is annealed and activated after ion implantation. Also, on the surface of the GaAs substrate 21, Z l
A Ta thin film 24 having a thickness of 10Ω and a barium titanate film 25 having a relative permittivity of ε r =120π/Z l ≈38 and a thickness of λ/4 are provided. Also, in the GaAs substrate 21 there is an n + region (n + layer) 23 implanted through the films 24 and 25 using the gate metal 26 as a mask.
Planar electromagnetic waves 27 are incident on the surface of the GaAs substrate 21 . Since the impedance of the gate metal 26 is low, electromagnetic waves are reflected. In addition, the electromagnetic waves are efficiently absorbed in the portion where the film 25 is attached, and are converted into heat in the Ta film 24, which has a large loss. This heat activates the n + layer 23.
第４図は本発明の第２の実施例を示す図であ
る。図において、GaAs基板３１はあらかじめイ
オン注入した後アニールされ、活性化されたｎ層
３２を有する。またGaAs基板３１の表面にはZl
＝10ΩのTa薄膜３４および比誘電率εr＝120π／Zl≒
38で厚さがλ／４のチタン酸バリウム膜３５が設
けられている。またGaAs基板３１中にはゲート
金属３６をマスクとし、膜３４，３５を通してイ
オン注入されたn+領域（n+層）３３が存在する。
GaAs基板３１の表面には平面電磁波３７が入射
される。膜３５が付けられた部分では電磁波は反
射されることなく主として膜３４の中で熱に変わ
る。この熱によりイオン注入n+層３３がアニー
ルされ活性化される。一方、ゲート金属のインピ
ーダンスは非常に低いため、厚さλ／２の膜３８
の表面から下部を見込んだインピーダンスも非常
に低い。このためゲート金属部に入射した電磁波
は膜３８の表面で反射する。なお、実施例では抵
抗体薄膜としてTa膜を用いたが、Taに限らず抵
抗体なら何でもよい。 FIG. 4 is a diagram showing a second embodiment of the present invention. In the figure, a GaAs substrate 31 has an n-layer 32 which is annealed and activated after ion implantation. Also, on the surface of the GaAs substrate 31, Z l
A Ta thin film 34 having a thickness of 10Ω and a barium titanate film 35 having a relative permittivity of ε r =120π/Z l ≈38 and a thickness of λ/4 are provided. Further, in the GaAs substrate 31, there is an n + region (n + layer) 33 in which ions are implanted through the films 34 and 35 using the gate metal 36 as a mask.
Planar electromagnetic waves 37 are incident on the surface of the GaAs substrate 31 . In the area where the film 35 is attached, the electromagnetic waves are not reflected and are mainly converted into heat within the film 34. The ion-implanted n + layer 33 is annealed and activated by this heat. On the other hand, since the impedance of the gate metal is very low, the film 38 with a thickness of λ/2
The impedance looking down from the surface is also very low. Therefore, the electromagnetic waves incident on the gate metal portion are reflected on the surface of the film 38. In addition, in the embodiment, a T a film was used as the resistor thin film, but the resistor is not limited to T a and any resistor may be used.
以上のように本発明によれば、光源から発せら
れる電磁波エネルギーが選択イオン注入層の上の
抵抗体薄膜に効率よく吸収されて熱に変わるた
め、光源から発せられる電磁波エネルギーが小さ
くても選択的にアニールを行うことができる。さ
らに光源から発せられる電磁波エネルギーは選択
イオン注入層の上の抵抗体薄膜に効率よく吸収さ
れ熱に変わる一方、選択イオン注入層以外の部分
では電磁波エネルギーをゲート金属等の半導体ウ
エハー上の構成物に達する前に反射して光源側に
もどすことができる。このため選択イオン注入層
以外の部分での温度上昇が小さく耐熱性のないゲ
ート金属を付けたままでもイオン注入層のアニー
ルを行うことができる効果を有するものである。 As described above, according to the present invention, the electromagnetic wave energy emitted from the light source is efficiently absorbed by the resistor thin film on the selective ion implantation layer and converted into heat, so even if the electromagnetic wave energy emitted from the light source is small, it can be selectively absorbed. can be annealed. Furthermore, the electromagnetic wave energy emitted from the light source is efficiently absorbed by the resistor thin film on the selective ion implantation layer and converted into heat, while the electromagnetic wave energy is transferred to components on the semiconductor wafer such as gate metal in areas other than the selective ion implantation layer. It can be reflected back to the light source before it reaches the light source. For this reason, the temperature rise in parts other than the selective ion-implanted layer is small, and the ion-implanted layer can be annealed even with the gate metal having no heat resistance attached.
第１図、第２図は本発明の原理を説明する図、
第３図、第４図はそれぞれ本発明の実施例を示す
半導体ウエハーの断面図である。
図において、１，１１は電磁波インピーダンス
Zpの媒質、２，１２は電磁波インピーダンスＺの
媒質、３はTa薄膜、４は半導体基板、５，６，
７，１４，１５は界面、１３は電磁波インピーダ
ンスZlの媒質、２１，３１はGaAs基板、２２，
３２はｎ層、２３，３３はn+層、２６，３６は
ゲート金属、２４，３４はTa薄膜、２５，３５
はチタン酸バリウム膜、３８は誘電体膜、２７，
３７は平面電磁波である。
1 and 2 are diagrams explaining the principle of the present invention,
3 and 4 are cross-sectional views of semiconductor wafers showing embodiments of the present invention, respectively. In the figure, 1 and 11 are electromagnetic wave impedances
Z p medium, 2 and 12 are electromagnetic wave impedance Z medium, 3 is T a thin film, 4 is a semiconductor substrate, 5, 6,
7, 14, 15 are interfaces, 13 is a medium with electromagnetic impedance Z l , 21, 31 is a GaAs substrate, 22,
32 is an n layer, 23, 33 is an n + layer, 26, 36 is a gate metal, 24, 34 is a T a thin film, 25, 35
is a barium titanate film, 38 is a dielectric film, 27,
37 is a plane electromagnetic wave.
Claims (1)
抵抗体薄膜を設け、さらにその上にεr＝120π／Zl
（ただしZlは抵抗体薄膜表面から下部を見込んだ
電磁波インピーダンス）の関係で表わされる比誘
電率εr、厚さ（2n＋１）／４・λ（ただしｎ＝０、
１、２、………、λは波長）なる膜を設け、その
上方より単色光源より発せられる電磁波エネルギ
ーを照射して選択イオン注入層のアニールを行う
ことを特徴とする半導体ウエハーの選択アニール
方法。 ２ 半導体ウエハーの選択イオン注入層の上に抵
抗体薄膜を設け、さらにその上にεr＝120π／Zl
（ただしZlは抵抗体薄膜表面から下部を見込んだ
電磁波インピーダンス）の関係で表わされる比誘
電率εr、厚さ（2n＋１）／４・λ（ただしｎ＝０、
１、２、………、λは波長）なる第一の誘電体膜
を設け、さらにその上に任意の誘電率で厚さが
（ｎ＋１）／２・λ（ただしｎ＝０、１、２、……
…）なる第二の誘電体膜を設け、選択イオン注入
層以外の部分には前記第二の誘電体膜のみを設
け、その上方より単色光源より発せられた電磁波
エネルギーを照射して選択イオン注入層のアニー
ルを行うことを特徴とする半導体ウエハーの選択
アニール方法。[Claims] 1. On the selective ion implantation layer of the semiconductor wafer,
A resistor thin film is provided, and ε r =120π/Z l
(where, Z l is the electromagnetic wave impedance looking down from the surface of the resistor thin film).
A selective annealing method for a semiconductor wafer, characterized by providing a film (1, 2, ......, where λ is a wavelength) and annealing a selective ion implantation layer by irradiating electromagnetic wave energy emitted from a monochromatic light source from above the film. . 2 A resistor thin film is provided on the selective ion implantation layer of the semiconductor wafer, and ε r =120π/Z l
(where, Z l is the electromagnetic wave impedance looking down from the surface of the resistor thin film).
1, 2, ......, λ is the wavelength), and furthermore, a first dielectric film with an arbitrary dielectric constant and a thickness of (n+1)/2・λ (where n=0, 1, 2 ,...
...) is provided, and only the second dielectric film is provided in the area other than the selective ion implantation layer, and selective ion implantation is performed by irradiating electromagnetic wave energy emitted from a monochromatic light source from above. A selective annealing method for semiconductor wafers, characterized by annealing layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58121318A JPS6014444A (en) | 1983-07-04 | 1983-07-04 | Selective annealing method of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58121318A JPS6014444A (en) | 1983-07-04 | 1983-07-04 | Selective annealing method of semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6014444A JPS6014444A (en) | 1985-01-25 |
| JPH0138368B2 true JPH0138368B2 (en) | 1989-08-14 |
Family
ID=14808274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58121318A Granted JPS6014444A (en) | 1983-07-04 | 1983-07-04 | Selective annealing method of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6014444A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5548926A (en) * | 1978-10-02 | 1980-04-08 | Hitachi Ltd | Preparation of semiconductor device |
-
1983
- 1983-07-04 JP JP58121318A patent/JPS6014444A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5548926A (en) * | 1978-10-02 | 1980-04-08 | Hitachi Ltd | Preparation of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6014444A (en) | 1985-01-25 |
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