JPS6014444A - Selective annealing method of semiconductor wafer - Google Patents

Selective annealing method of semiconductor wafer

Info

Publication number
JPS6014444A
JPS6014444A JP58121318A JP12131883A JPS6014444A JP S6014444 A JPS6014444 A JP S6014444A JP 58121318 A JP58121318 A JP 58121318A JP 12131883 A JP12131883 A JP 12131883A JP S6014444 A JPS6014444 A JP S6014444A
Authority
JP
Japan
Prior art keywords
film
layer
ion implantation
thickness
electromagnetic wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58121318A
Other languages
Japanese (ja)
Other versions
JPH0138368B2 (en
Inventor
Kazuhiko Honjo
和彦 本城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58121318A priority Critical patent/JPS6014444A/en
Publication of JPS6014444A publication Critical patent/JPS6014444A/en
Publication of JPH0138368B2 publication Critical patent/JPH0138368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

PURPOSE:To activate a selective ion implantation layer as a metal having no heat resistance such as Al is left as it adheres by forming a resistor thin-film on the ion implantation layer and forming a film having specific relative permittivity and thickness on the thin-film and annealing the film having said permittivity and thickness. CONSTITUTION:A Ta thin-film 24 and a film 25, relative permittivity epsilontau thereof satisfies the formula of 1<epsilontau<=120pi/Zl (Zl represents electromagnetic wave impedance obtained by estimating a lower section from the surface of a resistor thin-film) and thickness thereof satisfies the formula of (2n+1)lambda/4(n=0,1..., lambda represents a wavelength), are formed on the surface of a GaAs substrate 21 with an activated n layer 22. There is an n<+> layer 23 injected through the films 24, 25 while using a gate metal 26 as a mask in the substrate 21, electromagnetic waves are reflected because impedance lows in the gate metal 26 when planar electromagnetic waves 27 are projected, and electromagnetic waves are absorbed efficiently in a section to which the film 25 is attached, and activate the n<+> layer 23 in place of heat in the Ta film 24, loss thereof is large.

Description

【発明の詳細な説明】 本発明は半導体ウェハーの選択アニール方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selectively annealing semiconductor wafers.

近年、ＧａＡｓ等の化合物半尋体を用いたディスクリ−
）　ＦＥＴ　、ディジタル集λデ゛１回路、アナログ１
１．へ積回路の研究開発が活発に行なわれ−Ｃいる。こ
れらのデバイスにおいて、アクティブ素子として通常用
いられているショットキー障壁ゲートμ）１昌ｆｊ界効
果トランジスタ（八ＥＳＦＥＴ）が有するゲート・ソー
ス間寄生抵抗およびゲートドレイン四吾生抵抗を低減す
ることが、ゲ［究の盾要な１１°１題の一つとなってい
る。この寄生抵抗を低減するだめにはいくつかのアプロ
ーチがあるが、工：、”Ｌ造プロセスが比Ｉｉ；テ的容
易な、側熱性ゲート金属をマスクとしてＩｆ　）ｒ、Ｖ
をセルファラインでイオン注入する方法が広く用いられ
ている。この方法はｎ＋）○をイオン注入した後にゲー
ト金属を付けＩＣまま、８００℃前後の高温でアニール
を行い、イオン注入層の活性化を行う必要がある。した
がってゲート金属には耐熱性が要求され、ＴｉＷ　、　
ＴｉＷシリザイド、　ＷＡＧ　、ルＶ等のｈ４熱性金属
がゲート金属として採用されている。In recent years, discretization using compound hemibases such as GaAs has been developed.
) FET, digital integrated λ di 1 circuit, analog 1
1. Research and development of hexagonal circuits is being actively conducted. In these devices, reducing the gate-source parasitic resistance and gate-drain resistance of the Schottky barrier gate μ) 1-sho fj field-effect transistor (ESFET), which is commonly used as an active element, is [This is one of the 11°1 questions that are essential to studying. There are several approaches to reducing this parasitic resistance.
The method of ion implantation using self-alignment is widely used. In this method, after ion implantation of n+)○, it is necessary to attach a gate metal and perform annealing at a high temperature of around 800° C. to activate the ion implantation layer. Therefore, the gate metal is required to have heat resistance, and TiW,
H4 thermal metals such as TiW silicide, WAG, and LuV are employed as gate metals.

しかしながら、これらの金１１の耐熱性は必ずしも十分
でないという問題があった。さらにこれらのいわゆる耐
熱性金属は、ゲート金属として広く用いられているＭに
比べて（Ｍには耐熱性はない）、抵抗が大きく、信頼性
も劣るという問題があった。However, there was a problem in that the heat resistance of these gold 11s was not necessarily sufficient. Furthermore, these so-called heat-resistant metals have a problem in that they have higher resistance and lower reliability than M, which is widely used as a gate metal (M has no heat resistance).

本発明の目的は前記問題を解決し、ＭのようにｉＪ’　
Ａ’６性のない金スう１を着けたままでも・ｆオン注入
Ｊ１１の活性化を図ることができる半導体ウェハーの通
釈アニール方法を提供することに必る。The purpose of the present invention is to solve the above problem and to
It is necessary to provide a method for annealing a semiconductor wafer, which can activate the f-on implantation J11 even with the gold film 1 having no A'6 properties attached.

すなわち、本発明は半導体ウェハーの選択イオン注入層
の上に抵抗体薄膜を設け、さらにその上／１２０π に１くεｒ’＞　ｚ、　（ただし２．は抵抗休み１９表
面から下部を見込んだ電磁波インピーダンス）の＋３’
ｊ係で表１．２．・・・、λは波長）なる膜を設け、そ
の上方より単色光源より発せられる電磁波エネルギーを
照射して選択イオン注入層のアニールを行う半導体ウェ
ハーのアニール方法およびＨ’ＩＵ択イカイオン注入層
に抵抗体の薄膜を設け、さらにその上に１〈１２０π Ｃｒ＜　ｚ、（ただしＺ、は抵抗体薄膜表面から下部を
見込んだ電磁波インピーダンス）の関係で表わされる比
誘電率ε１、厚さくｚｎ＋Ｊ、　（ただしｎ＝０　、１
　、２　。That is, in the present invention, a resistor thin film is provided on the selective ion implantation layer of the semiconductor wafer, and furthermore, εr'> z, (where 2. is the electromagnetic wave impedance looking down from the surface of the resistor 19) ) +3'
Table 1.2 for section j. A semiconductor wafer annealing method in which a selective ion-implanted layer is annealed by irradiating electromagnetic wave energy emitted from a monochromatic light source from above the film, and resistance to the H'IU selective ion-implanted layer. A thin film of the resistor is provided on top of the thin film of the resistor, and a relative dielectric constant ε1 expressed by the relationship 1<120π Cr<z, (where Z is the electromagnetic wave impedance looking down from the surface of the resistor thin film) and a thickness zn+J, (where Z is n=0, 1
, 2.

・・・、λは波長）なる第一の誘電体ＪｌΔを設け、さ
らにその上に誘電率は任意で厚さが剰λ（ただしｎ””
Ｏｒ　１　＋　２　＋・・・）なる第二の「し電体膜を
設け、選択イオン注入磨以外の部分には前記第二の誘電
体膜のみを設け、その上方より単色光源より発せられる
電磁波エネルギーを照射して選択イオン注入ＪＩ′ｔの
アニールを行う半導体ウェハーの選択アニール方法であ
る。..., λ is the wavelength), and on top of that a first dielectric material JlΔ with an arbitrary dielectric constant and a thickness of λ (where n"") is provided.
Or 1 + 2 + . This is a selective annealing method for semiconductor wafers in which selective ion implantation JI't is annealed by irradiating energy.

以下に本発明の実施例を図面と数式を用いてｈ）′−述
する。Embodiments of the present invention will be described below using drawings and numerical formulas.

２ｆ１１図および第２図は本発明の詳細な説明するため
の図である。＠１図において、′１」磁波インピーダン
スがそれぞれ７．　、　Ｚであるようす媒質１および２
が互いに接して配列され、さらに芳質２に抵抗体薄膜３
が接し、抵抗体薄膜３には半ｄ１体基板４が接している
。旋質２と抵抗体ｒ、７１藤３との界面６から右側を児
込んだ電磁波インピーダンスを２、とすると、界面５か
ら右側を見込んだ電磁波インピーダンスＺ′は と表わすことができる。たｌビしｌは婬ｆ！１２の長さ
、Ｚ’−’−（２） Ｚノ となる。ここでもし ｚｏ　＝　ｚ’　（３） すなわち ｚ　＝　Ｊ　ＺｏＺ７　（４） の関係が成立するとき、インピーダンス２’、ｉ＞合が
起こり、媒Ｚｊ　ｉ、　（ｃ入射されたエネルギーは全
て界面６より右に伝送される。ただしＴユの損失が大き
いだめ、電イ：’１．波のエネルギーの大半ｔよ抵抗体
薄Ｉｌ′１！３中で熱に変わる。ととろで智：Ｈｉｔｔ
　２の比誘電〉（、可をε１、真空中の誘電率をε。、
群１１２の比透磁率なｉｔ、、真空中の透磁阜をμ。と
すると、 となる。μ、は通常１である。（４）式において７０を
Ｊ゛〔空中の電磁波インピーダンスとすると ２゜−／］− Ｊ−０−１２０π　（６） であるから、（’）　、（５）　、　（６）式よりＣｒ
ぐ覇　（７） のとき、インピーダンス整合が起こることが分る。FIG. 2f11 and FIG. 2 are diagrams for explaining the present invention in detail. In Figure @1, the '1' magnetic wave impedance is 7. , Z medium 1 and 2
are arranged in contact with each other, and a resistor thin film 3 is further placed on the aromatic layer 2.
is in contact with the resistor thin film 3, and the semi-d1 substrate 4 is in contact with the resistor thin film 3. If the electromagnetic wave impedance looking right from the interface 6 between the stratum 2, the resistor r, and the 71 rattan 3 is 2, then the electromagnetic wave impedance Z' looking right from the interface 5 can be expressed as. Tabishi l is 婬f! The length of 12 is Z'-'-(2) Zノ. Here, if the relationship zo = z' (3), that is, z = J ZoZ7 (4) holds, impedance 2', i > combination will occur, and all the energy incident on the medium Zj i, (c will be It is transmitted to the right.However, the loss of T is large, so most of the energy of the wave turns into heat in the thin resistor Il'1!3.Torode Satoshi: Hitt
2 relative permittivity〉(, ε1 is the permittivity, ε is the dielectric constant in vacuum,
The relative permeability of group 112 is it, and the permeability in vacuum is μ. Then, it becomes . μ is usually 1. In equation (4), 70 is J゛[2゜-/]-J-0-120π (6), so from equations ('), (5), and (6), Cr
It can be seen that impedance matching occurs when (7).

第２図において、電磁波インピーダンスがそれぞれ２．
．２，２．であるような３つの媒質１１．１２および１
３が接している。第２図において媒質１２の長さをλ／
２とすると（Ｆ、）式より Ｚ′＝Ｚ、（８） となる。この場合、インピーダンス整合は起こらず、媒
質１２を通しても媒質１３のインピーダンスがそのまま
見える。このときの界面１４における反射係数Ｆ をもって電磁波は光汀側へ反射する。In FIG. 2, the electromagnetic wave impedance is 2.
．． 2,2. Three media 11.12 and 1 such that
3 are in contact. In Fig. 2, the length of the medium 12 is λ/
2, then Z'=Z, (8) from equation (F,). In this case, impedance matching does not occur, and the impedance of the medium 13 is visible as it is even through the medium 12. At this time, the electromagnetic wave is reflected toward the light shore with the reflection coefficient F at the interface 14.

第３図は本発明の第１の実施例を示す図である。FIG. 3 is a diagram showing a first embodiment of the present invention.

図において、ＧａＡｓ基板２１はあらかじめイオン注入
した後アニールされ、活性化されたｎ層２２を有する。In the figure, a GaAs substrate 21 has an n-layer 22 which is annealed and activated after ion implantation.

才たＧａＡｓ基板２１の表面には′ｒａ薄膜２４およら
れている。まだＧａＡｓ基板２１中にはゲート金属２６
をマスクとして膜２４および２５を通して注入されたｎ
＋領領域ｎ＋層）２３が存在する。ＧａＡｓ基板２１の
表面には平面電磁波２６が入射される。ゲート金属２６
ではインピーダンスが低いために電磁波は反射される。The surface of the aged GaAs substrate 21 is covered with a RA thin film 24. There is still gate metal 26 in the GaAs substrate 21.
n implanted through films 24 and 25 using as a mask
+ area (n+ layer) 23 exists. Planar electromagnetic waves 26 are incident on the surface of the GaAs substrate 21 . gate metal 26
Since the impedance is low, electromagnetic waves are reflected.

まだ膜２５が付けられた部分では効率よく電磁波は吸収
され、損失の大きいＴａ１ＢＩ　２４中で熱に代わる。In the portion where the film 25 is still attached, the electromagnetic waves are efficiently absorbed and converted into heat in the Ta1BI 24, which has a large loss.

この貼により’ｒＴ５２３を活性化する。This patch activates 'rT523.

第４図１は本発明の第２の実施例を示す図である。。FIG. 4 1 is a diagram showing a second embodiment of the present invention. .

図において、ＧａＡｓ基板３１はあらかじめイオン注入
した後アニールされ、活性化されたｎ層３２を有する。In the figure, a GaAs substrate 31 has an n-layer 32 which is annealed and activated after ion implantation.

またＧａＡｓ基板３１の表面にはＴａ薄膜３４およ１２
０π び比誘電率が１７　で厚さがλ／４の膜３５が設けられ
ている。またＧａＡｓ基板３１中にはゲート金属３６を
マスクとし、１２（３４，３５を通してイオン注入され
たｎ＋領領域　ｎ＋居）　３３が存在する。ＧａＡｓ基
板３１ノ表面には平面電磁波３７が入射される。膜３５
が付けられた部分では電磁波は反射されることなく主と
して圧・工３４の中で熱に変わる。この１″！ｊシによ
りイオン注入ｎ／’、’５３３がアニールされ活性化さ
れる。一方、ゲート金属のインピーダンスは非常に低い
だめ、厚さλ／２の膜３８の表面から下部を見込んだイ
ンピーダンスも非常に低い。このだめゲート金ｋ”５　
ｒｔｌｓに入射した電磁波は膜３８の表面で反射する。Further, on the surface of the GaAs substrate 31, there are Ta thin films 34 and 12.
A film 35 having a dielectric constant of 0π and a relative dielectric constant of 17 and a thickness of λ/4 is provided. Further, in the GaAs substrate 31, using the gate metal 36 as a mask, there are 12 (n+ regions 33 into which ions are implanted through 34 and 35). Planar electromagnetic waves 37 are incident on the surface of the GaAs substrate 31 . membrane 35
At the portion marked with , the electromagnetic waves are not reflected and are mainly converted into heat within the pressure/workpiece 34. Due to this 1"!j, the ion implantation n/', '533 is annealed and activated. On the other hand, since the impedance of the gate metal is very low, the lower part is viewed from the surface of the film 38 with a thickness of λ/2. The impedance is also very low.Konodame gate gold k”5
The electromagnetic waves incident on the rtls are reflected by the surface of the membrane 38.

なお、実施例では抵抗体薄膜として’１’ａＮを用いた
が、Ｔａに限らず抵抗体なら何でもよい。In the embodiment, '1'aN was used as the resistor thin film, but the resistor is not limited to Ta, and any resistor may be used.

以上のように本発明によれば、光源から発せられる電磁
波エネルギーが選択イオン注入層の上の抵抗体薄膜に効
率よく吸収されて熱に変わるため、光源から発せられる
電磁波エネルギーが小さくても選択的にアニールを行う
ことができる。さらに光源から発せられる電磁波エネル
ギーは選択イオン注入層の上の抵抗体薄膜に効率よく吸
収され熱に変わる一方、選択イオン注入層以外の部分で
は電磁波エネルギーをゲート金属等の半尋体つエノ・−
上の宿成物に達する前に反射して光汀佃にもどすことが
できる。このだめ込択イオン注入層以外の部分での温度
上昇が小さく耐熱性のないゲート金属を付けたま１でも
イオン注入層のアニールを行うことができる効果を有す
るものである。As described above, according to the present invention, the electromagnetic wave energy emitted from the light source is efficiently absorbed by the resistor thin film on the selective ion implantation layer and converted into heat, so even if the electromagnetic wave energy emitted from the light source is small, it can be selectively absorbed. can be annealed. Furthermore, the electromagnetic wave energy emitted from the light source is efficiently absorbed by the resistor thin film on the selective ion implantation layer and converted into heat, while the electromagnetic wave energy is transferred to the gate metal etc.
It is possible to reflect the light and return it to the light trap before it reaches the host above. This has the effect that the temperature rise in parts other than the selective ion implantation layer is small, and the ion implantation layer can be annealed even when a gate metal with no heat resistance is attached.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は本発明の詳細な説明する図、第３図、
第４図はそれぞれ本発明の実施例を示す半導体ウェハー
の断面図である。 図において、１，１１は電磁波インピーダンス２゜の媒
質、２．１２はｔＥａ波インピーダンスＺの媒質、３は
Ｔａ薄ｌＩ；３．４は半導体基板、１３は電イ１λ（波
インピーダンスＺ、のＪｊ％ｔ　５１．２１　、３１は
ＧａＡｓ；Ｓ鈑、２２　、３２はｎ磨、２３　、３３は
ｎ＋層、２６　、３６はゲート金属、２・１゜３４はＴ
ａｆｆｚ　膜、２５．３５．３０は誘１（）体ｊ虞であ
る。 ！１Ｓ許出顕人　日本？、ｌ気株式会社第１図 第２図 笠Figures 1 and 2 are diagrams explaining the invention in detail, Figure 3,
FIG. 4 is a sectional view of a semiconductor wafer showing an embodiment of the present invention. In the figure, 1 and 11 are mediums with electromagnetic wave impedance 2°, 2.12 are mediums with tEa wave impedance Z, 3 is Ta thin lI; 3.4 is a semiconductor substrate, and 13 is Jj of electric wave impedance 1λ (wave impedance Z). %t 51.21, 31 is GaAs; S plate, 22, 32 is n-polished, 23, 33 is n+ layer, 26, 36 is gate metal, 2.1° 34 is T
affz film, 25.35.30 is an attractant. ! 1S Kento Akito Japan? , Lki Co., Ltd. Figure 1 Figure 2 Kasa

Claims (2)

【特許請求の範囲】[Claims] （１）半導体ウェハーの選択イオン注入層の上に、ただ
しＺ、は抵抗体薄膜表面から下部を見込んだ電磁波イン
ピーダンス）の関係で表わされる比誘電率ε７、厚さ−
〈剋λ（ただしｎ＝＝ｏ、１，２．・・・、λは波長）
なる腹を設け、その上方より単色光源より発ぜられる電
磁波エネルギーを照射して選択イオン注入層のアニール
を行うことを特徴とする半導体ウェハーの選択アニール
方法〇(1) Above the selective ion-implanted layer of the semiconductor wafer, where Z is the electromagnetic wave impedance looking down from the surface of the resistor thin film), the relative dielectric constant ε7, the thickness -
<剋λ (where n==o, 1, 2..., λ is the wavelength)
A selective annealing method for semiconductor wafers, which is characterized by providing an antinode and annealing the selective ion implantation layer by irradiating electromagnetic wave energy emitted from a monochromatic light source from above the antinode. （２）半導体ウェハーの選択イオン注入層の上に抵だし
２．は抵抗体薄膜表面から下部を見込んだ電磁波インピ
ーダンス）の関係で表わされる比誘電率ε１．厚さ且λ
（ただしｎ＝０　、１　、２　、・・・、λは波長）な
る第一の誘電体膜を設け、さらにその上に任意の誘電率
で厚さが可λ（ただしｎ＝＝０　＋　１　ｖ　２　ｒ・
・・）なる第二の誘電体膜を設け、選択イオン注入層以
外の部分には前記第二の誘電体膜のみを設け、その上方
より単色光源より発ぜられた電磁波エネルギーを照射し
て９３択イオン注入層の７ニールを行うことを４４ｐ　
Ｑとする半導体ウェハーの選択アニール方法。(2) resisting on the selective ion implantation layer of the semiconductor wafer; is the relative dielectric constant ε1. Thickness and λ
(where n = 0, 1, 2, ..., λ is the wavelength), and furthermore, a first dielectric film with an arbitrary dielectric constant and a thickness of λ (where n = 0 + 1) is provided. v 2 r・
) is provided, only the second dielectric film is provided in the area other than the selective ion implantation layer, and electromagnetic wave energy emitted from a monochromatic light source is irradiated from above. Performing 7 anneals of selective ion implantation layer 44p
Selective annealing method for semiconductor wafers with Q.
JP58121318A 1983-07-04 1983-07-04 Selective annealing method of semiconductor wafer Granted JPS6014444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58121318A JPS6014444A (en) 1983-07-04 1983-07-04 Selective annealing method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58121318A JPS6014444A (en) 1983-07-04 1983-07-04 Selective annealing method of semiconductor wafer

Publications (2)

Publication Number Publication Date
JPS6014444A true JPS6014444A (en) 1985-01-25
JPH0138368B2 JPH0138368B2 (en) 1989-08-14

Family

ID=14808274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58121318A Granted JPS6014444A (en) 1983-07-04 1983-07-04 Selective annealing method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS6014444A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548926A (en) * 1978-10-02 1980-04-08 Hitachi Ltd Preparation of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548926A (en) * 1978-10-02 1980-04-08 Hitachi Ltd Preparation of semiconductor device

Also Published As

Publication number Publication date
JPH0138368B2 (en) 1989-08-14

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