JPH0339854U - - Google Patents

Info

Publication number
JPH0339854U
JPH0339854U JP10135589U JP10135589U JPH0339854U JP H0339854 U JPH0339854 U JP H0339854U JP 10135589 U JP10135589 U JP 10135589U JP 10135589 U JP10135589 U JP 10135589U JP H0339854 U JPH0339854 U JP H0339854U
Authority
JP
Japan
Prior art keywords
semiconductor package
jig
sectional
view
taken along
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10135589U
Other languages
Japanese (ja)
Other versions
JP2510569Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989101355U priority Critical patent/JP2510569Y2/en
Publication of JPH0339854U publication Critical patent/JPH0339854U/ja
Application granted granted Critical
Publication of JP2510569Y2 publication Critical patent/JP2510569Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本考案実施例に係る半導体パツケー
ジのリードピン保護用治具を示す平面図、第1図
bは同図a中A部の拡大図である。第2図は第1
図a中のB−B線断面図である。第3図はピン孔
の他の実施例を示す部分拡大断面図である。第4
図a,bは本考案の治具の使用方法を説明するた
めの断面図、第5図は本考案の治具をPGAパツ
ケージに取り付けた状態を示す部分拡大断面図で
ある。第6図〜第9図は本考案の治具における半
導体パツケージとの取付手段のさまざまな実施例
を示しており、第6図a、第7図a、第8図aは
それぞれ平面図、第6図bは同図a中のC−C線
断面図、第7図bは同図a中のD−D線断面図、
第8図bは同図a中のE−E線断面図、第9図a
は分解斜視図、第9図bは部分断面図である。 10……治具、11……貫通孔、12……ピン
孔、13……溝、14……取付具、15……ボル
ト、16……固定具、17……ボルト、18……
スライド固定具、19……偏心回転体、20……
カバー、21……留具、30……PGAパツケー
ジ、31……リードピン。
FIG. 1a is a plan view showing a jig for protecting lead pins of a semiconductor package according to an embodiment of the present invention, and FIG. 1b is an enlarged view of section A in FIG. 1a. Figure 2 is the first
It is a sectional view taken along the line BB in figure a. FIG. 3 is a partially enlarged sectional view showing another embodiment of the pin hole. Fourth
Figures a and b are cross-sectional views for explaining how to use the jig of the present invention, and Fig. 5 is a partially enlarged cross-sectional view showing the jig of the present invention attached to a PGA package. 6 to 9 show various embodiments of the mounting means for the semiconductor package in the jig of the present invention, and FIG. 6a, FIG. 7a, and FIG. 8a are plan views, respectively. Figure 6b is a sectional view taken along the line CC in Figure a, Figure 7b is a sectional view taken along the line D-D in Figure A,
Figure 8b is a sectional view taken along the line E-E in Figure 9a, Figure 9a
9 is an exploded perspective view, and FIG. 9b is a partial sectional view. 10...Jig, 11...Through hole, 12...Pin hole, 13...Groove, 14...Mounting tool, 15...Bolt, 16...Fixing tool, 17...Bolt, 18...
Slide fixture, 19... Eccentric rotating body, 20...
Cover, 21...fastener, 30...PGA package cage, 31...lead pin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツクス板状体からなり、PGA型半導体
パツケージのリードピン配置に対応した複数のピ
ン孔を備え、かつ半導体パツケージとの取付手段
を具備したことを特徴とする半導体パツケージの
リードピン保護用治具。
A jig for protecting lead pins of a semiconductor package, which is made of a ceramic plate-like body, has a plurality of pin holes corresponding to the lead pin arrangement of a PGA type semiconductor package, and has means for attaching to the semiconductor package.
JP1989101355U 1989-08-30 1989-08-30 Jig for protecting lead pin of semiconductor package Expired - Lifetime JP2510569Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989101355U JP2510569Y2 (en) 1989-08-30 1989-08-30 Jig for protecting lead pin of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989101355U JP2510569Y2 (en) 1989-08-30 1989-08-30 Jig for protecting lead pin of semiconductor package

Publications (2)

Publication Number Publication Date
JPH0339854U true JPH0339854U (en) 1991-04-17
JP2510569Y2 JP2510569Y2 (en) 1996-09-11

Family

ID=31650313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989101355U Expired - Lifetime JP2510569Y2 (en) 1989-08-30 1989-08-30 Jig for protecting lead pin of semiconductor package

Country Status (1)

Country Link
JP (1) JP2510569Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006199520A (en) * 2005-01-18 2006-08-03 Zikusu Kogyo Kk Ceramic tool and method of manufacturing the same
US7887899B2 (en) 2005-08-25 2011-02-15 Sumitomo Electric Industries, Ltd. Anisotropic conductive sheet, production method thereof, connection method and inspection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62274646A (en) * 1986-05-22 1987-11-28 Nec Corp Terminal correcting jig
JPS6447050U (en) * 1987-09-16 1989-03-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62274646A (en) * 1986-05-22 1987-11-28 Nec Corp Terminal correcting jig
JPS6447050U (en) * 1987-09-16 1989-03-23

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006199520A (en) * 2005-01-18 2006-08-03 Zikusu Kogyo Kk Ceramic tool and method of manufacturing the same
US7887899B2 (en) 2005-08-25 2011-02-15 Sumitomo Electric Industries, Ltd. Anisotropic conductive sheet, production method thereof, connection method and inspection method

Also Published As

Publication number Publication date
JP2510569Y2 (en) 1996-09-11

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