JPH0338913U - - Google Patents
Info
- Publication number
- JPH0338913U JPH0338913U JP9853389U JP9853389U JPH0338913U JP H0338913 U JPH0338913 U JP H0338913U JP 9853389 U JP9853389 U JP 9853389U JP 9853389 U JP9853389 U JP 9853389U JP H0338913 U JPH0338913 U JP H0338913U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- variable resistor
- operational amplifier
- input terminal
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第1図及び第2図はこの考案に係るバランス調
整回路の実施例を示し、第1図は回路図、第2図
はこの考案の他の実施例を示す回路図である。第
3図は従来の実施例を示す回路図である。
主な符号の説明、1,2……オペアンプ、3…
…連動ボリウム、3a,3b,10……可変抵抗
器。
1 and 2 show an embodiment of the balance adjustment circuit according to this invention, FIG. 1 is a circuit diagram, and FIG. 2 is a circuit diagram showing another embodiment of this invention. FIG. 3 is a circuit diagram showing a conventional embodiment. Explanation of main symbols, 1, 2... operational amplifier, 3...
...Interlocking volume, 3a, 3b, 10...variable resistor.
Claims (1)
第1の可変抵抗器と第2の可変抵抗器を連動させ
た連動ボリウムとを設け、前記第1のオペアンプ
の(−)入力端子と出力端子及び第2のオペアン
プの(−)入力端子と出力端子とをそれぞれ第1
の抵抗器、第2の抵抗器を介して接続し、第1の
オペアンプの(−)入力端子と第2のオペアンプ
の(−)入力端子とを第3の抵抗器を介して接続
し、第1の可変抵抗器の摺動子の端子の第1のオ
ペアンプの(+)入力端子及び第2の可変抵抗器
の摺動子の端子と第2のオプアンプの(+)入力
端子とをそれぞれ接続し、第1の可変抵抗器の一
方の端子と第2の可変抵抗器の一方の端子とを接
続すると共に、第1の可変抵抗器の他方の端子及
び第2の可変抵抗器の他方の端子にはそれぞれ位
相が180度異なる信号を加えるように構成した
ことを特徴とするバランス調整回路。 2 第3の抵抗器は可変抵抗器であり、この可変
抵抗器は連動ボリウムと連動するように構成した
ことを特徴とする請求項1記載のバランス調整回
路。[Scope of claims for utility model registration] 1. A first operational amplifier, a second operational amplifier,
An interlocking volume in which a first variable resistor and a second variable resistor are linked is provided, and the (-) input terminal and output terminal of the first operational amplifier and the (-) input terminal and output of the second operational amplifier are provided. terminal and the first
the (-) input terminal of the first operational amplifier and the (-) input terminal of the second operational amplifier are connected through the third resistor, and the (-) input terminal of the second operational amplifier is connected through the third resistor. Connect the terminal of the slider of the first variable resistor to the (+) input terminal of the first operational amplifier and the terminal of the slider of the second variable resistor to the (+) input terminal of the second operational amplifier, respectively. and connect one terminal of the first variable resistor and one terminal of the second variable resistor, and connect the other terminal of the first variable resistor and the other terminal of the second variable resistor. A balance adjustment circuit characterized in that the balance adjustment circuit is configured to apply signals having a phase difference of 180 degrees to each. 2. The balance adjustment circuit according to claim 1, wherein the third resistor is a variable resistor, and the variable resistor is configured to operate in conjunction with an interlocking volume.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989098533U JPH083056Y2 (en) | 1989-08-25 | 1989-08-25 | Balanced volume control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989098533U JPH083056Y2 (en) | 1989-08-25 | 1989-08-25 | Balanced volume control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0338913U true JPH0338913U (en) | 1991-04-15 |
JPH083056Y2 JPH083056Y2 (en) | 1996-01-29 |
Family
ID=31647628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989098533U Expired - Lifetime JPH083056Y2 (en) | 1989-08-25 | 1989-08-25 | Balanced volume control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH083056Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2024064551A (en) * | 2022-10-28 | 2024-05-14 | 日置電機株式会社 | Differential input differential output type inversion amplifier circuit and measurement device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62158919U (en) * | 1986-03-29 | 1987-10-08 |
-
1989
- 1989-08-25 JP JP1989098533U patent/JPH083056Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62158919U (en) * | 1986-03-29 | 1987-10-08 |
Also Published As
Publication number | Publication date |
---|---|
JPH083056Y2 (en) | 1996-01-29 |