JPH0338913U - - Google Patents

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Publication number
JPH0338913U
JPH0338913U JP9853389U JP9853389U JPH0338913U JP H0338913 U JPH0338913 U JP H0338913U JP 9853389 U JP9853389 U JP 9853389U JP 9853389 U JP9853389 U JP 9853389U JP H0338913 U JPH0338913 U JP H0338913U
Authority
JP
Japan
Prior art keywords
terminal
variable resistor
operational amplifier
input terminal
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9853389U
Other languages
Japanese (ja)
Other versions
JPH083056Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989098533U priority Critical patent/JPH083056Y2/en
Publication of JPH0338913U publication Critical patent/JPH0338913U/ja
Application granted granted Critical
Publication of JPH083056Y2 publication Critical patent/JPH083056Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図はこの考案に係るバランス調
整回路の実施例を示し、第１図は回路図、第２図
はこの考案の他の実施例を示す回路図である。第
３図は従来の実施例を示す回路図である。 主な符号の説明、１，２……オペアンプ、３…
…連動ボリウム、３ａ，３ｂ，１０……可変抵抗
器。 1 and 2 show an embodiment of the balance adjustment circuit according to this invention, FIG. 1 is a circuit diagram, and FIG. 2 is a circuit diagram showing another embodiment of this invention. FIG. 3 is a circuit diagram showing a conventional embodiment. Explanation of main symbols, 1, 2... operational amplifier, 3...
...Interlocking volume, 3a, 3b, 10...variable resistor.

Claims (1)

【実用新案登録請求の範囲】 １ 第１のオペアンプと、第２のオペアンプと、
第１の可変抵抗器と第２の可変抵抗器を連動させ
た連動ボリウムとを設け、前記第１のオペアンプ
の（−）入力端子と出力端子及び第２のオペアン
プの（−）入力端子と出力端子とをそれぞれ第１
の抵抗器、第２の抵抗器を介して接続し、第１の
オペアンプの（−）入力端子と第２のオペアンプ
の（−）入力端子とを第３の抵抗器を介して接続
し、第１の可変抵抗器の摺動子の端子の第１のオ
ペアンプの（＋）入力端子及び第２の可変抵抗器
の摺動子の端子と第２のオプアンプの（＋）入力
端子とをそれぞれ接続し、第１の可変抵抗器の一
方の端子と第２の可変抵抗器の一方の端子とを接
続すると共に、第１の可変抵抗器の他方の端子及
び第２の可変抵抗器の他方の端子にはそれぞれ位
相が１８０度異なる信号を加えるように構成した
ことを特徴とするバランス調整回路。 ２ 第３の抵抗器は可変抵抗器であり、この可変
抵抗器は連動ボリウムと連動するように構成した
ことを特徴とする請求項１記載のバランス調整回
路。[Scope of claims for utility model registration] 1. A first operational amplifier, a second operational amplifier,
An interlocking volume in which a first variable resistor and a second variable resistor are linked is provided, and the (-) input terminal and output terminal of the first operational amplifier and the (-) input terminal and output of the second operational amplifier are provided. terminal and the first
the (-) input terminal of the first operational amplifier and the (-) input terminal of the second operational amplifier are connected through the third resistor, and the (-) input terminal of the second operational amplifier is connected through the third resistor. Connect the terminal of the slider of the first variable resistor to the (+) input terminal of the first operational amplifier and the terminal of the slider of the second variable resistor to the (+) input terminal of the second operational amplifier, respectively. and connect one terminal of the first variable resistor and one terminal of the second variable resistor, and connect the other terminal of the first variable resistor and the other terminal of the second variable resistor. A balance adjustment circuit characterized in that the balance adjustment circuit is configured to apply signals having a phase difference of 180 degrees to each. 2. The balance adjustment circuit according to claim 1, wherein the third resistor is a variable resistor, and the variable resistor is configured to operate in conjunction with an interlocking volume.
JP1989098533U 1989-08-25 1989-08-25 Balanced volume control circuit Expired - Lifetime JPH083056Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989098533U JPH083056Y2 (en) 1989-08-25 1989-08-25 Balanced volume control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989098533U JPH083056Y2 (en) 1989-08-25 1989-08-25 Balanced volume control circuit

Publications (2)

Publication Number Publication Date
JPH0338913U true JPH0338913U (en) 1991-04-15
JPH083056Y2 JPH083056Y2 (en) 1996-01-29

Family

ID=31647628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989098533U Expired - Lifetime JPH083056Y2 (en) 1989-08-25 1989-08-25 Balanced volume control circuit

Country Status (1)

Country Link
JP (1) JPH083056Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024064551A (en) * 2022-10-28 2024-05-14 日置電機株式会社 Differential input differential output type inversion amplifier circuit and measurement device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158919U (en) * 1986-03-29 1987-10-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158919U (en) * 1986-03-29 1987-10-08

Also Published As

Publication number Publication date
JPH083056Y2 (en) 1996-01-29

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