JPH033853U

JPH033853U -

Info

Publication number: JPH033853U
Application number: JP6472089U
Authority: JP
Priority date: 1989-06-02
Filing date: 1989-06-02
Publication date: 1991-01-16

Description

[Brief explanation of the drawing]

第１図は本考案の実施例をブロツク図で示した
回路図、第２図ａ〜ｈは第１図に示した回路のタ
イミングチヤート、第３図は従来のＡＤ変換回路
をブロツク図で示した回路図、第４図ａ〜ｄは第
３図に示した回路のタイミングチヤートである。第１図において、３０１……ゼロクロスデイテ
クタ、３０２……ゼロレベルタイミングデイテク
タ、３０３……ピークデイテクタ、３０４……ピ
ークタイミングデイテクタ、３０５……ピークホ
ールド回路、３０６……ピークＡＤコンバータ、
３０７……サンプル＆ホールド回路、３０８……
ＡＤコンバータ、３０９……ＡＤタイミングコン
トローラ、３１０……基準クロツク発生器、３ａ
……入力アナログ信号、３ｂ……ＬＺ信号、３ｃ
……ゼロレベルタイミング信号、３ｄ……Ｐ信号
、３ｅ……ＰＡＤ信号、３ｆ……ＰＨ信号、３ｇ
……ＰＳＨ信号、３ｈ……ピークレベル信号、３
ｉ……ＰＣＥ信号、３ｊ……ＳＨＤ信号、３ｋ…
…ＡＤ変換データ信号、３ｌ……基準クロツク、
３ｍ……タイミングクロツク、３ｎ……ＳＨ信号
、３ｐ……ＡＤＳ信号、３ｇ……ＡＤＥ信号、３
ｒ……ＡＤタイミング信号。第２図において、ａ……入力アナログ信号３ａ
、ｃ１，ｃ２，ｃ３……ＡＤ変換を行うレベル、
Ｚ１，Ｚ２……ゼロレベル、Ｐ１，Ｐ２，Ｐ３，
Ｐ４，Ｐ５……極値のレベル、ＴＣ１，ＴＣ２，
ＴＣ３……ＡＤ変換を行う時刻、ＴＺ１，ＴＺ２
……ゼロレベルとなる時刻、ＴＰ１，ＴＰ２，Ｔ
Ｐ３，ＴＰ４，ＴＰ５……極値をとる時刻、ｂ…
…ＬＺ信号３ｂ（入力アナログ信号３ａがゼロレ
ベルとなつたときの出力）、ｃ……Ｐ信号３ｄ（
入力アナログ信号３ａが極値をとるときに出力さ
れる信号）、ｄ……ピークレベル信号３ｈの時間
軸を移動した波形、ｅ……ＳＨ信号３ｎ（ＡＤ変
換を行うときに出る信号）、ｆ……ＡＤ変換デー
タ信号３ｋの時間軸を移動した波形、ｇ……ＬＺ
信号３ｂ、Ｐ信号３ｄ、ＳＨ信号３ｎを合成した
波形、ｈ……ゼロレベルタイミング信号３ｃ、ピ
ークタイミング信号３ｅ、ピークレベル信号３ｈ
、ＡＤ変換データ信号３ｋ、ＡＤタイミング信号
３ｒの合成波形。第３図において、１１……サンプル＆ホールド
回路、１２……ＡＤコンバータ、１３……基準ク
ロツク発生器、１４……ＡＤタイミングコントロ
ーラ、１ａ……入力アナログ信号、１ｂ……ＳＨ
Ｄ信号、１ｃ……ＡＤ変換データ信号、１ｄ……
ＳＨ信号、１ｅ……ＡＤＳ信号、１ｆ……基準ク
ロツク、１ｇ……ＡＤＥ信号。第４図において、ａ……入力アナログ信号１ａ
、Ｃ１，Ｃ２，Ｃ３……ＡＤ変換を行うレベル、
ＴＣ１，ＴＣ２，ＴＣ３……ＡＤ変換を行う時刻
、ｂ……ＳＨＤ信号１ｂ、ｃ……ＡＤ変換データ
信号１ｃ、ｄ……ｃの時間軸を移動した波形。 Fig. 1 is a circuit diagram showing an embodiment of the present invention in a block diagram, Fig. 2 a to h are timing charts of the circuit shown in Fig. 1, and Fig. 3 is a block diagram showing a conventional AD conversion circuit. The circuit diagrams shown in FIGS. 4a to 4d are timing charts of the circuit shown in FIG. In FIG. 1, 301...Zero cross detector, 302...Zero level timing detector, 303...Peak detector, 304...Peak timing detector, 305...Peak hold circuit, 306...Peak AD converter,
307...Sample & hold circuit, 308...
AD converter, 309...AD timing controller, 310... Reference clock generator, 3a
...Input analog signal, 3b...LZ signal, 3c
...Zero level timing signal, 3d...P signal, 3e...PAD signal, 3f...PH signal, 3g
...PSH signal, 3h ...Peak level signal, 3
i...PCE signal, 3j...SHD signal, 3k...
...AD conversion data signal, 3l...reference clock,
3m...Timing clock, 3n...SH signal, 3p...ADS signal, 3g...ADE signal, 3
r...AD timing signal. In FIG. 2, a...input analog signal 3a
, c1, c2, c3... level for performing AD conversion,
Z1, Z2...Zero level, P1, P2, P3,
P4, P5...Extreme level, TC1, TC2,
TC3...Time to perform AD conversion, TZ1, TZ2
...Time at zero level, TP1, TP2, T
P3, TP4, TP5... Time at which the extreme value is taken, b...
...LZ signal 3b (output when input analog signal 3a reaches zero level), c...P signal 3d (
A signal output when the input analog signal 3a takes an extreme value), d... Waveform of the peak level signal 3h shifted on the time axis, e... SH signal 3n (signal output when AD conversion is performed), f ...Waveform of AD conversion data signal 3k shifted on the time axis, g...LZ
Waveform obtained by combining signal 3b, P signal 3d, and SH signal 3n, h...Zero level timing signal 3c, peak timing signal 3e, peak level signal 3h
, AD conversion data signal 3k, and AD timing signal 3r. In Fig. 3, 11... Sample & hold circuit, 12... AD converter, 13... Reference clock generator, 14... AD timing controller, 1a... Input analog signal, 1b... SH
D signal, 1c...AD conversion data signal, 1d...
SH signal, 1e...ADS signal, 1f...reference clock, 1g...ADE signal. In Fig. 4, a...input analog signal 1a
, C1, C2, C3...levels for performing AD conversion,
TC1, TC2, TC3...times at which AD conversion is performed, b...SHD signal 1b, c...AD conversion data signals 1c, d...waveforms obtained by moving the time axis of c.

Claims

[Scope of utility model registration request]

AD converts analog signals to digital signals
In the conversion circuit, there is a zero cross detector that detects the zero level of the input analog signal, a zero level timing detector that detects the time when the zero cross detector is activated, and a zero level timing detector that detects the time when the input analog signal becomes maximum or minimum. a peak detector that detects the peak detector's operation time, a peak timing detector that detects the operating time of the peak detector, a peak hold circuit that holds the maximum and minimum values of the input analog signal, and the output of the peak hold circuit. A peak AD converter that converts a value into a digital signal, a sample and hold circuit that holds the input analog signal, an AD converter that converts the output of the sample and hold circuit into a digital signal, and a reference clock. An AD converter detects the time of AD conversion by inputting the signal, generates an operation start signal for the sample-and-hold circuit and the AD converter, and generates a counting clock for the zero level timing detector and the peak timing detector.
An AD conversion circuit comprising a timing controller and a reference clock generator that generates a reference clock to be supplied to the AD timing controller.