JPH033583A - Signal processing circuit for high definition television receiver - Google Patents

Abstract

PURPOSE:To obtain normal freeze picture by using a memory by 4-field in a decoder section of a high definition television receiver and adding a memory storing one frame of movement detection data with a comparatively small capacity and an interpolation circuit. CONSTITUTION:Four-field of high definition television signal subjected to band compression is stored in a 1st memory circuit 6 and 2-field of an output signal of a movement detection circuit 8 detecting one frame of a television signal and 2-frame is stored in the 2nd memory circuit 7 at all times. In response to the output signal of the 2nd memory circuit, a mixture ratio between the output signal of a still picture processing circuit 9 and an output signal of the 1st and 2nd moving picture processing circuits 10, 21 is controlled. Thus, accurate movement detection data is obtained even at the freeze mode and the moving picture in the freeze mode is normally obtained by interpolating one frame picture from any of odd and even number fields.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing circuit for a high-definition television receiver that converts a band-compressed high-definition television signal into the original wideband television signal. The present invention relates to a signal processing circuit suitable for providing a freeze function suitable for a high definition television receiver.

[Prior Art] One of the methods for compressing a wideband high-definition television signal to a practical level bandwidth is a multiple subsample transmission method using offset subsampling between frames and between fields, such as MUSE (Multiple 5ub). −
Nyquist Sampling Encoding
) is a high-definition television signal multiplex sub-sampled transmission system.

This MUSE method is a method for transmitting a high-definition television signal by applying 4:1 sub-Nyquist sampling in which the signal goes around in four fields, compressing the band to about one-fourth.

Figure 2 shows a configuration in which a high-definition television signal (hereinafter referred to as the MUSE signal) band-compressed by the MUSE method is image interpolated using field memory and frame memory, and converted into the original wideband television signal. 1 is a block diagram showing a signal processing circuit of a conventional high-definition television receiver.

In Figure 2, (1) is the MUSE signal input terminal, (
3) is an A/D conversion circuit which inputs the MUSE signal arriving at the input terminal (1). (4) is a signal separation circuit which receives the output signal of the A/D conversion circuit (3). Reference numeral (5) denotes a switch circuit, one input of which is the output signal of the signal separation circuit (4), and the other input of which is an output signal of a second field memory (7), which will be described later. (6) is a first field memory, which inputs the output signal of the switch circuit (5). (7) is a second field memory, which inputs the output signal of the first field memory (6).

(8) is a motion detection circuit which uses the output signal of the switch circuit (5) as one input, and has a second field memory (7) as an input.
) is used as the other input. (9) is a static region interpolation circuit, which takes the output signal of the switch circuit (5) as one input, and takes the output signal of the first field memory (6) as the other input. (10) is a moving area interpolation circuit, and the switch circuit (5) is the same as the static area interpolation circuit (8) above.
The output signal of is input. (11) is a mix circuit that combines the output signal of the motion detection circuit (8) with
Output signal of #ff circuit (9) and dynamic area interpolation circuit (10)
The output signal of is input. (12) is a TCI decoder, which inputs the output signal of the mix circuit (12). (13) is an inverse matrix circuit, which takes the output signal of the TCI decoder (12) as one input, and takes the output signal of the mix circuit (11) as the other input. (14)
is a D/A conversion circuit, which inputs the output signal of the inverse matrix circuit (13). (2) is a D/A conversion circuit (10
This is an output terminal that outputs the output signal to the outside.

Next, the operation of the above configuration will be explained.

The MUSE signal input from the input terminal (1) is converted into, for example, 8 bits, 480 fH (f
H is the horizontal scanning frequency) It is converted into a digital signal at a sampling rate and input to the signal separation circuit (4), where the motion vector signal, audio signal, each control signal, etc. are separated in the signal separation circuit (0). The vector signal is directed to a second field memory (7).

On the other hand, the MUSE signal is connected to a switch circuit (5) that is switched by a 4BOfH sub-sample clock signal.
and is input to the first field memory (6).

The signal input to the first field memory (6) is delayed by one field and then input to the second field memory (7). The signal input to the second field memory (7) is further delayed by one field, and the above-mentioned motion vector signal is used to correct screen deviations from the current MUSE signal due to panning, etc., and the switch circuit (5) ). Here, the current MUSE signal from the signal separation circuit (4) and the previous frame signal from the second field memory (7) are input to the switch circuit (5). Since the switch circuit (5) is switched by the sub-sample clock signal, the current MUSE signal and the previous frame signal are alternately input to the first field memory (6) depending on the sub-sample phase. Therefore, the two field memories (8) and (7) have 480f
Two frames worth of signals with a sample rate of H are stored,
The current signal and the signal two fields (l frame) before are output from the switch circuit (5) at the sub-sample phase period.
The signals of 1 field before and 3 fields before are obtained at the output of the field memory (6), and the signals of 2 fields, that is, 1 frame before, and 4 fields, that is, 2 frames before, are obtained at the output of the second field memory (7). .

Each signal obtained in this way is sent to a motion detection circuit (8) consisting of the current signal, a signal two fields before, and a signal four fields before. The current signal is input to a static area interpolation circuit (9) consisting of the signal and a signal from three fields before, and a moving area interpolation circuit (lO) consisting of the current signal.

The motion detection circuit (8) detects the amount of motion between one frame and two frames (hereinafter referred to as "interframes") of the image, and inputs it as a motion signal to the mix circuit (11). 8) performs image reproduction using all the sampling points of the four fields, and the moving area interpolation circuit (10) performs image reproduction using only the sampling points of the current signal without using past sampling points. The signal is input to the mix circuit (11). The mix circuit (11) mixes the output signal of the still area interpolation circuit (9) and the output signal of the moving area interpolation circuit (10) according to the motion signal output from the motion detection circuit (8).
It is input to the TCI decoder (page 12) and also to one input of the inverse matrix circuit (13). In the TCI decoder (12), the chroma signal, that is, the color difference signal, which was line-sequential and time-base compressed to 1/4, is returned to the original time-base and inputted to the other input of the inverse matrix circuit (13). The inverse matrix circuit (13) returns the input color difference signal to the original three primary colors of R, G, and B, and then inputs it to the D/A conversion circuit (14) where it is converted into an analog signal and sent to the output terminal (1
2) is decoded into the original broadband high-definition television signal.

This MUSE decoder has a memory for four fields in order to digitally interpolate images for four fields successively and restore the original wideband signal.

Therefore, the image is frozen by using the memory for these four fields and constantly reading out the four fields' worth of signals written in the memory.

[Problems to be Solved by the Invention] The signal processing circuit of a conventional high-definition television receiver represented by the above-mentioned MUSE decoder is configured as described above. Even if freezing is possible, a normal frozen image cannot be obtained due to the influence of motion vectors that are temporally different from the signals read out from memory, and even if the motion vectors are stopped at the same time as freezing, the difference between frames cannot be obtained. Since the images cannot be obtained normally, erroneous motion detection occurs and moving parts of the image are processed as still images, resulting in a problem of multiple images.

Also, when normal video processing is performed on moving parts of an image, the first. Second. Third. Since there is a time difference in the fourth field, there is a problem in that moving parts of the image appear to flicker.

This invention was made to solve the above-mentioned problems, and an object thereof is to provide a signal processing circuit for a high-definition television receiver that can eliminate multiple images and obtain a normal frozen image. .

[Means for Solving the Problems] A signal processing circuit for a high-definition television receiver according to the present invention includes a first memory circuit that stores at least four fields of band-compressed high-definition television signals, and a still image processing circuit. a still image processing circuit, a first video processing circuit that processes video, a second video processing circuit that operates only in freeze mode, and a motion detection circuit that detects the amount of movement between l frames and between z frames; A motion detection interpolation circuit that operates only in freeze mode, a second memory circuit that stores the output signal of the motion detection circuit for two fields, and a video processing circuit that stores the output signal of the still image processing circuit and the video processing circuit according to the output of the motion detection circuit. a mix circuit for controlling the mixing ratio of the output signals of the first .
Before and after the second memory circuit and the first. and a switch circuit provided at a subsequent stage of the second video processing circuit,
In the freeze mode, the output of the first memory circuit is fed back to the input of the first memory circuit, the output of the second memory circuit is fed back to the input of the second memory circuit, and the output of the second memory circuit is fed back to the input of the second memory circuit. The output signal is interpolated, and the output signal of the still image processing circuit and the first . The present invention is characterized in that the mixing ratio of the output signal of the second moving image processing circuit is controlled by a mix circuit.

[Operation] According to the present invention, two fields of the output signal of the motion detection circuit that detects the amount of motion between one frame and between two frames of a band-compressed high-definition television signal are always stored in the second memory circuit. In response to the output signal of the 8z memory circuit, the output signal of the still image processing circuit and the first . Since the mixing ratio with the output signal of the second video processing circuit is controlled, accurate motion detection data can be obtained even in freeze mode. This can be successfully obtained by interpolating an image of l frames from either one of the images.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of a signal processing circuit of a high-definition television receiver according to an embodiment of the present invention.
1) is an input terminal for a MUSE signal, (15) is an input terminal for a freeze signal, and (3) is an A/D variable conversion circuit.The MUSE signal arriving at the input terminal (1) is input. (4
) is a signal separation circuit which inputs the output signal of the A/D conversion circuit (3).

(5) is the first switch circuit, and the signal separation circuit (4) is the first switch circuit.
) is used as one input, and the output signal of a first field memory (8), which will be described later, is used as the other input. (1B
) is the second switch circuit, and the first switch circuit (
The output signal of 5) is used as one input, and the output signal of a second field memory (7), which will be described later, is used as the other input.

(6) is a first field memory into which the output signal of the second switch circuit (16) is input. (7) is a second field memory, which is connected to the first field memory (6).
) as input. (17) is a third switch circuit, one input of which is the motion vector signal separated by the signal separation circuit (4), and the other input of which is a cutoff signal. Reference numeral (8) denotes a motion detection circuit, one input of which is the output signal of the second switch circuit (16), and the other input of which is the output signal of the second field memory (7). (t
S) is the fourth switch circuit, which is connected to the motion detection circuit (8).
) is used as one input, and the output signal of a fourth field memory (20), which will be described later, is used as the other input. (
19) is a third field memory, which receives the output signal of the fourth switch circuit (18). (20) is a fourth field memory, which inputs the output signal of the third field memory (19).

(24) is a motion detection interpolation circuit, one input of which is the output signal of the fourth switch circuit (18), and the other input of which is the output signal of the third field memory (19).
(25) is a fifth switch circuit, one input of which is the output signal of the fourth switch circuit (I8), and the other input of which is the output signal of the motion detection interpolation circuit (24). (9)
is a static region interpolation circuit, and the second switch circuit (18
) is taken as one input, and the output signal of the first field memory (6) is taken as the other input. (10) is a first dynamic area interpolation circuit, which is connected to the second switch circuit (10).
The output signal of 6) is input.

(21) is a second dynamic area interpolation circuit which receives the output signal of the first field memory (6) as input.

Reference numeral (22) denotes a field discrimination signal input terminal which inputs a field discrimination signal which is normally at H level and becomes H level in odd fields and L level in even fields only in the freeze mode. (23) is a fifth switch circuit, which takes the output signal of the first dynamic area interpolation circuit (10) as one input, and uses the output signal of the second dynamic area interpolation circuit (21) as the other input. .

(11) is a mix circuit, which is the fourth switch circuit (
18), the output signal of the static region interpolation circuit (8), and the output signal of the fifth switch circuit (23) are input. (12) is a TCI decoder, which inputs the output signal of the mix circuit (11). (13) is an inverse matrix circuit, which takes the output signal of the TCI decoder (12) as one input, and takes the output signal of the mix circuit (11) as the other input. (14) is a D/A conversion circuit which inputs the output signal of the inverse matrix circuit (13).

(2) is an output terminal for outputting the output signal of the D/A conversion circuit (14) to the outside.

Next, the operation of the above configuration will be explained.

In normal operation, the second switch circuit (1B),
Third switch circuit (17), fourth switch circuit (1
The sixth switch circuit (25) is connected in the direction shown by the dotted line in Figure 1, and the field discrimination signal input terminal (25) is connected in the direction shown by the dotted line in Figure 1.
2), the H level is input, and the fifth switch circuit (
23) is connected in the direction shown by the solid line in Figure 1, and decodes the MUSE signal input from the input terminal (1) into the original wideband television signal using exactly the same processing as the conventional example shown in Figure 2. Supplied to output terminal (2). However, the output signal of the motion detection circuit (8) is transmitted to the fourth switch circuit (18).
At the same time, the signal is input to the mix circuit (11) through the input signal, and is input to the third field memory (19), and after an l-field delay, is input to the fourth field memory (20).

In the fourth field memory (20), the input signal is further delayed by one field and then input to the fourth switch circuit (18). Therefore, two motion signals are always stored in the third and fourth field memories (19) and (20).
This means that the number of fields is stored.

Next, the operation in freeze mode will be explained.

In the freeze mode, the freeze signal input from the input terminal (15) causes the second, third, fourth, . The sixth switch circuits (1B), (17), (1B), and (25) are connected in the direction shown by the solid line in Figure 1, and the field discrimination signal input terminal (22) is high in odd fields in freeze mode. In an even field, an L level signal is input, which causes the fifth switch circuit (23) to move in the direction shown by the solid line in Figure 1 for odd fields and in the direction shown by the dotted line in Figure 1 for even fields. Connected. First, the second switch circuit (16) cuts off the current MUSE signal from the signal separation circuit (4), and the input of the first field memory (6) receives the output from the second field memory (7). A signal is input through the switch circuit (16). Therefore, at the start of freezing, the first.
In the second field memories (8) and (7), the l field and the signal from 3 fields before are stored as odd fields, the signals from 2 fields and 4 fields before are stored as even fields, and the first and second fields memory(
8), (7), circulates within the second switch circuit (16). Therefore, the output terminal (2) always has the same 4
A high-quality television signal obtained by decoding a field's worth of signals is output and becomes a frozen image.

However, when the motion vector signal is input to the second field memory (7), the first and second field memories (7)
Although the signals circulating through 8) and (7) have already been subjected to motion correction, incorrect motion correction is performed, so the third switch circuit (17) cuts off the motion vector signal. There is.

Also, since only 4 fields of data are circulated in the first and second field memories (8) and (?), the motion detection circuit (8) cannot correctly obtain the difference between frames. False detection occurs in motion detection. Therefore, at the same time that the freeze signal is input, one frame of motion detection data previously stored in the third and fourth field memories (19) and (20) is transferred to the first and second field memories (6). .

The data for the four fields stored in (7) are circulated at the same cycle as the cycle.

Next, since video processing is processed in units of one field, if you perform the same processing as normal, the video will appear in the order of the first field, second field, third field, and fourth field, and the image will be It becomes flickering. In order to turn this flickering image into a flicker-free frozen image, one representative field is selected from among the first field, second field, third field, and fourth field, and the image of that representative field is It is necessary to interpolate the image data of the other three fields using the four data to create a frozen image of the moving image.

Therefore, the operation of each circuit for obtaining such a frozen image of a moving image will be explained.

First, the normal operation and freeze operation of the first dynamic area interpolation circuit (lO) will be explained in order. Here, the video signal input to the first dynamic area interpolation circuit (lO) is transmitted between frames by the first field memory (8), the second field memory (7), and the first switch circuit (5). This is an interpolated signal, and when this video signal is expressed as a two-dimensional screen, the transmitted data of the first to fourth fields are arranged in a positional relationship as shown in FIG.

First, in the case of an odd field in normal times, the first dynamic area interpolation circuit (10) erases data in one of the first or third fields according to the above input signal, and interpolates data at that data position from the other data. Insert the data. As a result, an odd field is obtained by interpolating data from one of the first and third fields. Then, by alternately performing the operation of selecting data of either the first or third field on a frame-by-frame basis, an odd-numbered field moving image is obtained.

Furthermore, in the case of an even field, a moving image of the even field is obtained by the same operation as for the odd field described above. And the first. Second. Third. A moving image is constructed by sequentially outputting the data of odd and even fields interpolated from the data of each field of the fourth field.

Next, the first dynamic area interpolation circuit (10
) operation will be explained.

First, when the freeze signal is input, the operation of selecting data in the first or third and second or fourth fields of the odd and even fields is fixed, so that they are not selected alternately on a frame-by-frame basis. do. As a result, the odd field continues to output data interpolated from the data of either the first or third field, and the even field continues to output data interpolated from the data of either the second or fourth field.

Next, the second dynamic area interpolation circuit (21
) operation will be explained.

First, a video signal delayed by one field with respect to the video signal input to the first dynamic area interpolation circuit (10) is input to the second dynamic area interpolation circuit (21). Then, an interpolation operation is performed using the data of the odd and even fields selected by the first moving area interpolation circuit (10). ), the odd field data is used to interpolate the even field data position, and the even field data is input to the second dynamic area interpolation circuit (21
), conversely, the even field data is used to interpolate the odd field data position.

Next, the fifth switch circuit (23) selects the output of the first dynamic area interpolation circuit (10) in one field based on the field discrimination signal inputted from the field discrimination signal input terminal (22). , for the other field, it operates to select the output of the second dynamic area interpolation circuit (21).

As a result of the above operations, for example, if the data being input to the first dynamic area interpolation circuit (10) is an odd field, and the first dynamic area interpolation circuit (10) selects the first field. If an interpolation operation is performed and the fifth switch circuit (23) selects the output of the first dynamic area interpolator (10), then in the first field, the second dynamic area interpolator (21) selects the odd field. data is entered,
The second dynamic area interpolation circuit (21) selects the first field and performs an interpolation operation, and the fifth switch circuit (23) selects the output of the second dynamic area interpolation circuit (21). This operation causes the fifth switch circuit (23) to
Odd and even fields interpolated from the fields are output. In other words, a frozen image of a moving image is obtained by interpolating the image data of the other three fields using the first field.

Next, motion detection also needs to be processed in a manner compatible with frozen images. This means that the odd and even fields are
Since the relationship is as shown in Figure 3, 1. When motion is detected in a certain area within a two-dimensional screen using normal motion detection, one field is motion detected and becomes a moving image, and the other field becomes a still image. This is because there are areas that cause horizontal striped interference. Therefore, the motion detection interpolation circuit (20
The motion detection data of one field and the motion detection data obtained by vertically interpolating the motion detection data of the other field are added and sent to the mix circuit (11) via the sixth switch circuit (25). It is outputting. This results in
An area in one field is a moving area, and any area in the other field that is a stationary area is a moving area.

Through the above-described video processing and motion detection processing, it is possible to obtain a normal frozen image in which erroneous still image processing is not performed even when a video is frozen, and the video does not flicker.

[Effects of the Invention] As described above, according to the present invention, the memory for four fields provided in the decoder section of a high-definition television receiver can be used as is, and a relatively small capacity, that is, about 4 bits, can be used as is. By adding a memory that can store one frame's worth of motion detection data and an interpolation circuit, it is possible to add a freeze function and eliminate multiple images that occur when processing still images when freezing a video. , it is possible to obtain a normal frozen image.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a signal processing circuit of a high definition television receiver according to an embodiment of the present invention, FIG. 2 is a block diagram showing a signal processing circuit of a conventional high definition television receiver, and FIG. 3 is a block diagram showing a signal processing circuit of a conventional high definition television receiver.
The figure is an explanatory diagram showing the positional relationship of data in odd-numbered fields and even-numbered fields. (1)...Input terminal, (2)...Output terminal, (3)
... A/D conversion circuit, (4) ... signal separation circuit, (
5). (18), (17), (18), (23), (25)・
...Switch circuit, (8), (7), (19), (2
0)...Field memory, (8)...Motion detection circuit, (8)...Stationary area interpolation circuit, (1G). (21)...Moving area interpolation circuit, (11)...Mix circuit, (12)...TCI decoder, (13)...
・Inverse matrix circuit, (14)...D/A conversion circuit, (15)...Freeze signal input terminal, (24)...
・Motion detection interpolation circuit Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In the signal processing circuit of a high-definition television receiver that converts a high-definition television signal band-compressed by the sub-Nyquist sampling method that goes around in four fields into the original wideband television signal, at least the high-definition television signal with band compression is processed. a first memory circuit that stores signals for four fields; a still image processing circuit that processes a band-compressed high-definition television signal as a still image; and a first video processing circuit that processes a band-compressed high-definition television signal as a moving image. circuit and a second circuit that operates only when in freeze mode and processes high-definition television signals into video.
a motion detection circuit that detects the amount of motion between one frame and between two frames of a band-compressed high-definition television signal, and a second memory that stores two fields of output signals of this motion detection circuit. a motion detection interpolation circuit that operates only in freeze mode, and a mixing ratio of the output signal of the still image processing circuit and the output signal of the first moving image processing circuit according to the output signal of the motion detection circuit. and switch circuits provided before and after the first and second memory circuits and after the first and second video processing circuits, and when in the freeze mode, The output of the first memory circuit is fed back to the input of the memory circuit, and the output of the second memory circuit is fed back to the input of the second memory circuit to interpolate the output signal of the second memory circuit. , wherein the mixing ratio of the output signal of the still image processing circuit and the output signal of the first and second moving image processing circuits is controlled by the mixing circuit according to the interpolation signal. TV receiver signal processing circuit.