JP3349285B2 - Television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver, and more particularly to, for example, as a band compression method for transmitting a high-definition video signal, performing sub-Nyquist offset subsampling to three-dimensionally reduce a high-frequency component. The present invention relates to a television receiver used for high-definition television or the like that restores a band-compressed signal to an original signal by using a technique of incorporating components into components.

[0002]

2. Description of the Related Art A multi-subsampling encoding (MUSE) system is well known as a system for compressing a high-definition video signal and transmitting it using one channel of a broadcasting satellite. This method is introduced in the literature of "Development of MUSE method", written by Ninomiya and Otsuka et al. (NHK Technical Research, Vol. 39, No. 2, pp. 18-53, 1987). Here, the television receiver 1 on the receiving side of the MUSE system
Is shown in FIG.

In FIG. 7, a MUSE signal supplied from an input terminal 1a is A / D-converted by an A / D conversion circuit 1b, and is transmitted through a de-emphasis circuit 1c and a transmission inverse gamma correction circuit 1d. Interpolation circuit 1e,
Color difference signal frame interpolation circuit 1f and motion detection circuit 1
g. The MUSE signal A / D converted by the A / D conversion circuit 1b is also supplied to the control decoder 1h and the timing generation circuit 1i. The control decoder 1h obtains a vertical motion vector, a horizontal motion vector, and a luminance sub-sampling signal.
The luminance signal frame interpolation circuit 1e, the luminance signal field interpolation circuit 1j, the chrominance signal frame interpolation circuit 1f, and the chrominance signal field interpolation circuit 1k. A timing signal is output from the timing generation circuit 1i to each circuit.

Then, a luminance signal frame interpolation circuit 1e
In, the signal subjected to frame offset sub-sampling on the encoder side is interpolated between frames for a still image portion and interpolated for a field for a moving image portion, and mixed according to the amount of motion. In the luminance signal field interpolation circuit 1j, the signal subjected to the field offset sub-sampling on the encoder side is interpolated between the fields for the still image portion, and between the fields for the moving image portion. Mixed. The color difference signal is similarly processed by the color difference signal frame interpolation circuit 1f and the color difference signal field interpolation circuit 1k. The motion amount is obtained by the motion detection circuit 1g.

The luminance signal field interpolation circuit 1
Outputs of the j and chrominance signal field interpolating circuits 1k are processed by the matrix circuit 11 and the matrix circuit 11 outputs R, G, and B signals. This R,
The G and B signals are respectively supplied to the D / A conversion circuits 1m, 1n, 1
output terminals 1p and 1q after D / A conversion at o
And 1r.

Next, the luminance signal frame interpolation circuit 1e will be described with reference to FIG. The luminance signal frame interpolation circuit 1e operates at a clock rate of 32.4 MHz. The luminance signal input from the luminance signal input terminal 2a is supplied to the moving image processing filter 2b and the frame interpolation circuit 2c. The frame memory 2d stores a signal for one frame period from the frame interpolation circuit 2c.

From the terminals 2e, 2f and 2g,
The vertical motion vector, the horizontal motion vector, and the luminance sub-sampling signal from the control decoder 1h are input and supplied to the memory control circuit 2h. In the memory control circuit 2h, the frame memory 2d is controlled in consideration of horizontal and vertical motion vector correction, and interframe interpolation processing is performed by the interframe interpolation circuit 2c.

The still image signal from the frame interpolating circuit 2c and the moving image signal obtained by the moving image processing filter 2b are supplied to a MIX circuit 2i, mixed according to a motion signal from a terminal 2j, and subjected to frame interpolation. Output from the output terminal 2k.

[0009]

In the conventional television receiver 1 shown in FIGS. 7 and 8, the circuit becomes complicated and the circuit scale becomes large. In particular, a series of processing in the luminance signal frame interpolation circuit 1e is performed at a high clock rate of 32.4 MHz, and the memory control in the memory control circuit 2h is performed on the memory in consideration of horizontal and vertical motion vector correction. Writing and reading control are required, the circuit becomes complicated, and the circuit scale becomes large.

[0010] Therefore, a main object of the present invention is to provide a television receiver which can be simply constructed.

[0011]

SUMMARY OF THE INVENTION The present invention is a television receiver for obtaining a horizontal motion vector of a luminance signal for a pixel having a clock rate of mHz included in a MUSE signal. And a frame interpolating means for interpolating the high-frequency component between frames. The interframe interpolating means includes an m / 2H signal when the horizontal motion vector is an even number.
a first motion vector correction means for correcting a high frequency component of the previous frame by a horizontal motion vector at a clock rate of z, and a horizontal motion vector at a clock rate of m / 2 Hz when the horizontal motion vector is an odd number. A second motion vector correction means for correcting and correcting the phase of the high frequency component of the previous frame by one clock at a clock rate of m / 2 Hz for the line requiring correction of the phase of the high frequency component of the previous frame; A television receiver including: an interpolation component generation unit that obtains an interpolation component using the high-frequency component of the previous frame obtained by the interpolation; and a unit that interpolates the interpolation component into the high-frequency component of the current frame at a clock rate of m / 2 Hz. is there.

[0012]

The separating means separates the luminance signal included in the MUSE signal into a low-frequency component and a high-frequency component. The high-frequency components are subjected to inter-frame interpolation processing by inter-frame interpolation processing means.
The interpolation processing means switches the processing depending on whether the horizontal motion vector for a pixel having a clock rate of 32.4 MHz is an even number or an odd number. That is, if the horizontal motion vector is an even number, the first motion vector correction means
For example, the high-frequency component of the previous frame is corrected with a horizontal motion vector at a clock rate of 16.2 MHz. On the other hand, if the horizontal motion vector is an odd number, the second motion vector correction means first delays the high frequency component of the previous frame with respect to the line for which the phase of the high frequency component of the previous frame needs to be corrected. The high-frequency component of the previous frame is subjected to horizontal motion vector correction at a clock rate of 2 MHz.

The high frequency component of the previous frame, which has been subjected to the horizontal motion vector correction by the first motion vector correction means or the second motion vector correction means, is used, and then the interpolation component is obtained by the interpolation component generation means. Then, this interpolation component is interpolated into the high frequency component of the current frame at a clock rate of m / 2 Hz. As described above, the horizontal motion vector correction processing and the interpolation processing at the time of inter-frame interpolation can be performed at the m / 2 Hz clock, for example, the 16.2 MHz clock rate.

[0014]

According to the present invention, processing which has been conventionally performed at a clock rate of mHz can be performed at a clock rate of m / 2 Hz, so that the circuit scale can be reduced and a television receiver having a simple configuration can be obtained. Can be The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a television receiver 10 of this embodiment has a simple configuration M in order to reduce the circuit scale.
It is configured to include a USE decoder. The television receiver 10 includes an input terminal 12 and a MU from the input terminal 12.
The SE signal is input, and is converted into digital data by the A / D conversion circuit 14. Then, the de-emphasis circuit 1
6 is de-emphasized. De-emphasis circuit 1
The luminance signal from 6 is subjected to transmission inverse gamma processing by a transmission inverse gamma correction circuit 18. Here, the MUSE signal is
As for the luminance signal, the low frequency component (0 to 4 MHz) does not include the aliasing component due to the subsampling. Therefore, the low-frequency component of the luminance signal (hereinafter simply referred to as “luminance low-frequency component”
Can be used as is without interpolation.
Therefore, after performing the transmission inverse gamma processing on the received MUSE signal by the transmission inverse gamma correction circuit 18, the separation filter 20 including the LPF and the HPF outputs the luminance including the low-pass component and the luminance including the alias component. The signal is separated into high-frequency components (hereinafter simply referred to as “luminance high-frequency components”), and only the high-luminance components are subjected to three-dimensional interpolation as described later.

The digital data obtained by the A / D conversion circuit 14 is supplied to a control decoder 22 and a timing generation circuit 24. The control decoder 22 obtains a vertical motion vector, a horizontal motion vector, and a luminance sub-sampling signal, and outputs a luminance high frequency component inter-frame interpolation circuit 30, a luminance high frequency component inter-field interpolation circuit 32, and a chrominance signal intra-field processing circuit 40.
Given to. Further, a timing signal for setting processing timing in each circuit is output from the timing generation circuit 24. Further, a line toggle signal that is inverted every line is supplied from the timing generation circuit 24 to the high-luminance component frame interpolation circuit 30.

Further, utilizing the fact that the human visual characteristics are dull in the high frequency range, the number of quantization bits for the high frequency component is determined by a bit conversion circuit (not shown) provided at the subsequent stage of the separation filter 20. Reduce. Here, for example, 8-bit data is converted to 6 bits. The data with the reduced number of quantization bits is provided to the nonlinear processing circuit 26 and the motion detection circuit 28.

The nonlinear processing circuit 26 performs nonlinear processing in order to reduce the level distribution of the high-frequency component around 0 and to reduce interference such as false contours. The non-linear processing circuit 26 expands the low level side and compresses the high level side. The non-linear inverse processing circuit 34 conversely compresses the low level side and expands the high level side. The characteristics of the non-linear processing and the characteristics of the non-linear inverse processing are complementary to each other, and have a relationship such that the combined characteristic is linear.

The high luminance component from the nonlinear processing circuit 26 is supplied to a high luminance component frame interpolation circuit 30. As will be described in detail later, the high-luminance component frame interpolating circuit 30 interpolates the high-luminance component into frames as still image processing and performs field interpolation as moving image processing. Then, the interpolated luminance high frequency components are mixed according to the amount of motion, and an interpolation component is obtained. This interpolated component is interpolated into the high-luminance component of the current frame, and is applied to the high-luminance component field interpolation circuit 32. The luminance high frequency component field interpolation circuit 32 performs an interpolation process based on the vertical motion vector, the horizontal motion vector, and the luminance sub-sampling signal. That is, the high-luminance component is interpolated between fields as a process for a still image, and interpolated as a process for a moving image,
Each is mixed according to the amount of motion, and the nonlinear inverse processing circuit 3
4 is output. Note that the motion amount is obtained by the motion detection circuit 28.

The output from the high-luminance component field interpolating circuit 32 is subjected to nonlinear inverse processing by a nonlinear inverse processing circuit 34, and is applied to an adder 36. In the adder 36, the high luminance component from the nonlinear inverse processing circuit 34 and the low luminance component from the separation filter 20 are added, and the result is supplied to the matrix circuit 38 as a luminance signal. On the other hand, for the color difference signal, the color difference signal
For simplicity, interpolation in the time direction is not performed, and only moving image processing, that is, field interpolation (spatial interpolation) is performed, and the result is supplied to the matrix circuit 38 as an RY signal and a BY signal. Of course, it is also possible to apply the process of applying the still image and the moving image to the color difference signal in the same manner as in the related art.

The matrix circuit 38 outputs R, G, and B signals, which are converted into analog data by D / A conversion circuits 42, 44, and 46 for R, G, and B signals, respectively. From 50 and 52, R,
G and B signals are output. Luminance high frequency component frame interpolating circuit 3 of television receiver 10 thus configured
0 is configured, for example, as shown in FIG.

Referring to FIG. 2, in high-luminance component frame interpolating circuit 30, a high-luminance component from input terminal 54 is applied to delay circuit 56, moving image processing filter 58, and frame memory 60. The high-luminance component for one frame period is written in the frame memory 60. Further, from the input terminals 62, 64 and 66, a vertical motion vector, a horizontal motion vector and a luminance sub-sampling signal from the control decoder 22 are inputted. The vertical motion vector and the horizontal motion vector are obtained as data updated every field, and the luminance sub-sampling signal is inverted every frame, for example, 15 bits.
Hz signal. Further, a line toggle signal from the timing generation circuit 24 is input from the input terminal 68.

The frame memory 60 includes a memory control circuit 70
Thus, the writing position and the reading position of the high luminance component are controlled. At this time, the memory control circuit 70 may perform simple control that only considers the vertical motion vector. That is, the memory control circuit 70 controls how many lines of the luminance high-frequency component written to the frame memory 60 are shifted from the writing position and read in accordance with the input vertical motion vector.

The high-luminance component written in the frame memory 60 is read out in the next frame and supplied to the delay circuit 72 and the selector 74. The delay circuit 72 has 16.
A 2 MHz clock is supplied, and the input high luminance component is delayed by one clock and supplied to the selector 74. The horizontal motion vector given from the input terminal 64 is
As shown in Table 1, it is composed of, for example, 4 bits and has 16 levels of vector values.

[0025]

[Table 1]

The upper three bits of the horizontal motion vector shown in Table 1 are applied to a shift amount control circuit 76 including, for example, eight stages of shift registers, and the least significant bit of the horizontal motion vector is applied to an AND circuit 78. The luminance sub-sampling signal which is inverted every frame and the line toggle signal which is inverted every line are supplied to the EX-OR circuit 80. Therefore, the EX-OR circuit 80 outputs a line toggle signal, which is inverted for each line, further inverted for each frame, and outputs the AND signal 78 and the EX-OR.
A circuit 82 is provided.

Then, a selection signal according to the least significant bit of the horizontal motion vector is output from the AND circuit 78 to the selector 74.
Given to. That is, when the least significant bit of the horizontal motion vector is “0” (when the horizontal motion vector is an even number)
, The selection signal from the AND circuit 78 becomes “0”.
On the other hand, when the least significant bit of the horizontal motion vector is “1” (when the horizontal motion vector is an odd number), the selector 74
, An output from the EX-OR circuit 80 is provided as a selection signal.

Therefore, when the horizontal motion vector is an even number, the selection signal to the selector 74 is always "0", and the high-luminance component from the frame memory 60 is selected as it is and supplied to the shift amount control circuit 76. On the other hand, when the horizontal motion vector is an odd number, a selection signal that switches between “1” and “0” is provided for each line as a selection signal of the selector 74, and a high-luminance component passed through the delay circuit 72 and a frame The high luminance component provided directly from the memory 60 is selected and supplied to the shift amount control circuit 76.

In the shift amount control circuit 76, the shift amount of the high luminance component is determined according to the upper three bits of the horizontal motion vector. In this embodiment, the least significant bit of the horizontal motion vector is truncated, and only the upper three bits are used.
By truncating the least significant bit of the horizontal motion vector and using only the upper 3 bits in this way, 32.4M
The horizontal motion vector for the pixel at the Hz clock rate can be converted to the horizontal motion vector for the pixel at the 16.2 MHz clock rate, and the horizontal motion vector can be corrected at the 16.2 MHz clock rate.

As can be seen from Table 1, when horizontal motion vector correction is performed at a clock rate of 32.4 MHz,
The high luminance component must be shifted within the range of “+7” to “−8”. However, by performing the horizontal motion vector correction at a clock rate of 16.2 MHz, “+3” to
What is necessary is just to shift the high luminance component within the range of “−4”.

The output from the shift amount control circuit 76, that is, the high-luminance component subjected to the still image processing is applied to the MIX circuit 84. The MIX circuit 84 is provided with a high-luminance component that has been subjected to field interpolation, that is, processing for a moving image by the moving image processing filter 58. And MI
In the X circuit 84, these luminance high frequency components are input to an input terminal 86.
Are weighted according to the motion signal from the image signal and synthesized, and an interpolation component is obtained. The interpolation component from the MIX circuit 84 is provided to the selector 88. The high-luminance component of the current frame is supplied to the selector 88 via the delay circuit 56.

Then, the selector 88 performs inter-frame interpolation processing in accordance with a selection signal from the EX-OR circuit 82 to which an output from the EX-OR circuit 80 and a clock of 16.2 MHz are given. That is, the selector 88
In response to a selection signal (FIG. 3E) having a clock rate of 16.2 MHz and inverting the polarity for each line, a high-luminance component of the current frame from the delay circuit 56 (FIG.
(C)) and the interpolation component from the MIX circuit 78 (FIG.
(D)) and 32.4 are added to the delay circuit 90 alternately.
A signal having a MHz clock rate (FIG. 3F) is given.

As can be seen from FIGS. 3C to 3F, when the selection signal from the EX-OR circuit 82 is "1", the selector 88 selects the high luminance band component from the delay circuit 56. When the selection signal is "0", the interpolation component from the MIX circuit 78 is selected. Further, as shown in FIG. 3E, in response to the selection signal being inverted for each line,
As shown in FIG. 3 (F), the selection order of the high luminance component and the interpolation component is switched for each line (FIG. 3 (F) in FIG. 3 (E), and FIG. 3 (E)). Time is Figure 3
(F)). In the delay circuit 90, 32.4 MHz
The signal is delayed by the clock at the clock rate,
It is output from the output terminal 92 as a frame interpolation output.

Next, a method of correcting a horizontal motion vector in the high-luminance component frame interpolating circuit 30 shown in FIG. 2 will be described. For simplicity, the description of the vertical motion vector is omitted, but the horizontal motion vector correction is processed independently of the vertical motion vector. First,
Referring to FIG. 4, the horizontal motion vector is an even number (here, "-
2)) will be described. In FIGS. 4 to 6, ○ represents a high luminance component of the current frame, and ● represents a high luminance component of the previous frame.

FIG. 4A shows the sampling of an original image of a still image. In the case of FIG. 4, since the horizontal motion vector is "-2", as shown in FIG. The high frequency component is shifted to the left by 2 clocks at a clock rate of 32.4 MHz from that of the still image. As shown in FIG. 4C, at the time of transmission, the signal is transmitted at a clock rate of 16.2 MHz together with the luminance sub-sampling signal.
As shown in (D), on the decoder, that is, on the side of the television receiver 10, the shift amount control circuit 76 sets the frequency to 16.2 MHz.
The vector correction value “−” for the pixel at the z clock rate
"1" is shifted to the left by one clock. Then, finally, as shown in FIG. 4E, the high-luminance component after interpolating between frames is correctly reproduced. In FIG. 4E, a portion indicated by a dotted line indicates a combination and an order of the high luminance band component of the current frame and the high luminance band component (interpolation component) of the previous frame. The same processing is performed when the horizontal motion vector is “0”.

Next, a case where the horizontal motion vector is an odd number (here, "-1") will be described with reference to FIG. In this case, as shown in FIG. 5A, since the same point is sampled in each frame, there is no difference between the original image sampling point for each frame, that is, the subsampling phase of the current frame and the subsampling phase of the previous frame. ing. Then, as shown in FIG.
At the time of transmission, it is sent at a clock rate of 16.2 MHz as in FIG. At this time, as can be seen by comparing FIG. 5A and FIG.
Shifted by one clock at a 2.4 MHz clock rate. Then, as shown in FIG. 5C, the vector correction on the decoder side is also shifted one clock to the left at a clock rate of 16.2 MHz as in FIG. The reason why FIG. 4 and FIG. 5 are equally shifted to the left by one clock is that the clock rate for horizontal motion vector correction has been converted from 32.4 MHz to 16.2 MHz.

However, if the frame interpolation processing is simply performed as it is, the high luminance component becomes “DCFEHG” as shown in FIG. 5D, and the interpolation is not performed correctly. Therefore, when the horizontal motion vector is an odd number, it is necessary to shift the luminance sub-sampling phase to the right by two clocks at a 32.4 MHz clock rate when the interpolation order is “previous one frame, current frame”. ), The luminance high-frequency component of the previous frame is
It is necessary to perform processing for delaying one clock extra at a clock rate of 2 MHz (FIG. 5E). As a result, the high-luminance component after the interpolation between frames is finally correctly reproduced. The line whose interpolation order is “previous frame, current frame” is determined by whether or not the line is shifted by one clock at the time of transmission.

FIG. 6 shows that the horizontal motion vector is an odd number "+".
Although the case of “1” is shown, the processing is performed in the same manner as in the case of FIG. According to this embodiment, the frame interpolating process and the horizontal motion vector correction do not need to be performed at the high-speed 32.4 MHz clock rate, and the frame memory control is simplified. This is effective when a MUSE decoder having a configuration is configured.

The above-described embodiment can also be applied to a case where the image data is extended for 12/11 hours at a stage prior to the television receiver 10. In that case, 32.4M in the above embodiment is used.
Hz is 29.7MHz, 16.2MHz is 14.8M
Hz may be read.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a high-luminance component frame interpolating circuit according to the embodiment;

FIG. 3 is a timing chart for explaining frame interpolation processing according to the embodiment;

FIG. 4 is an illustrative view for explaining horizontal motion vector correction when the horizontal motion vector is “−2”;

FIG. 5 is an illustrative view for explaining horizontal motion vector correction when the horizontal motion vector is “−1”;

FIG. 6 is an illustrative view showing a case where a horizontal motion vector is “1”;

FIG. 7 is a block diagram showing a conventional technique.

FIG. 8 is a block diagram showing a conventional luminance frame interpolation circuit.

[Explanation of symbols]

 Reference Signs List 10 television receiver 30 luminance high frequency component frame interpolation circuit 56, 72, 90 delay circuit 58 moving image processing filter 60 frame memory 70 memory control circuit 74, 88 selector 76 shift amount control circuit 78 AND circuit 80, 82 EX-OR circuit 84 MIX circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/44-9/78 H04N 11/00-11/22

Claims (2)

(57) [Claims] 1. A television receiver for obtaining a horizontal motion vector of a luminance signal for a pixel having a clock rate of mHz included in a MUSE signal, wherein said separating means separates said luminance signal into a low-frequency component and a high-frequency component. And inter-frame interpolation processing means for performing inter-frame interpolation processing on the high-frequency component, wherein the inter-frame interpolation processing means operates at a clock rate of m / 2 Hz when the horizontal motion vector is an even number. First motion vector correction means for correcting a high-frequency component of a previous frame by a horizontal motion vector; when the horizontal motion vector is an odd number, correcting a high-frequency component of the previous frame by a horizontal motion vector at a clock rate of m / 2 Hz; For the line for which the phase of the high frequency component of the previous frame needs to be corrected, the high frequency component of the previous frame is expressed by m /
2nd delay of one clock at a clock rate of 2 Hz
Motion vector correction means, interpolation component generation means for obtaining an interpolation component by using the high-frequency component of the previous frame subjected to the horizontal motion vector correction, and interpolation of the interpolation component into the high-frequency component of the current frame at a clock rate of m / 2 Hz. A television receiver including a means for inserting. 2. The television receiver according to claim 1, wherein said mHz is 32.4 MHz.