JPH0335324A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPH0335324A
JPH0335324A JP1170302A JP17030289A JPH0335324A JP H0335324 A JPH0335324 A JP H0335324A JP 1170302 A JP1170302 A JP 1170302A JP 17030289 A JP17030289 A JP 17030289A JP H0335324 A JPH0335324 A JP H0335324A
Authority
JP
Japan
Prior art keywords
register
subroutine
contents
internal ram
pointer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1170302A
Other languages
Japanese (ja)
Inventor
Hiroshi Kubo
博 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1170302A priority Critical patent/JPH0335324A/en
Publication of JPH0335324A publication Critical patent/JPH0335324A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To reduce the overhead produced when a subroutine is called and to attain the effective use of a register set by using a means to set partly the adjacent register sets with overlap for a register bank consisting of an internal RAM. CONSTITUTION:When a register number is designated in an instruction, this register number is added to the contents of a register pointer. Then an area (register) of an internal RAM pointed by the result of this addition is accessed. For instance, a parameter is set to a register 7 from a register 0 in a main routine and a subroutine is called out. Then '8' is subtracted from the contents of a register pointer at the side of the subroutine. As a result, the register 0 is mapped to the register 7 in the main routine and a register 8 is mapped to a register 15 in the subroutine respectively. Thus the parameter can be transferred with no transfer of data. Furthermore, the contents of the register pointer can be reduced by an amount equal to the number of registers necessary for the subroutine. Then the internal RAM is effectively used.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、レジスタバンクにおける全く新規なレジスタ
セット設定手段を備えたマイクロコンピュータに関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a microcomputer equipped with completely new register set setting means in a register bank.

〈従来の技術・発明が解決しようとする課題〉従来のマ
イクロコンピュータに於いては、レジスタバンク内のレ
ジスタセットは個々に独立しているため、サブルーチン
呼び出し時に、メインルーチンとサブルーチンで各々別
のレジスタセットを使う場合、レジスタセクト間で、パ
ラメータの受は渡しのためのデータ転送処理を行う必要
が生じ、命令数の増加、処理時間の増大等、オーバーヘ
ッドが増大していた。また、各レジスタセットのレジス
タ数も固定されているため、レジスタを余り使わないサ
ブルーチンや割り込み処理ルーチンでも1つのレジスタ
セットを専有していた。
<Prior art/problems to be solved by the invention> In conventional microcomputers, each register set in a register bank is independent, so when a subroutine is called, separate registers are used for the main routine and subroutine. When using sets, it becomes necessary to perform data transfer processing for passing parameters between register sectors, which increases overhead such as an increase in the number of instructions and an increase in processing time. Furthermore, since the number of registers in each register set is fixed, even subroutines and interrupt processing routines that do not use registers often occupy one register set.

本発明は、上記従来技術を改善するためになされたもの
であり、サブルーチン呼び出し時のオーバーヘッドの低
減及びレジスタセ・トの効率的使用を目的とするもので
ある。
The present invention has been made in order to improve the above-mentioned prior art, and aims at reducing the overhead when calling a subroutine and efficiently using register sets.

く課題を解決するための手段〉 本発明のマイクロコンピュータは、内部RAMにより構
成されるレジスタバンクに於いて、隣接するレジスタセ
・1トの一部をオーバーラップして設定する手段を設け
たことを特徴とするものである。
Means for Solving the Problems> The microcomputer of the present invention is provided with a means for setting a part of adjacent register sets in an overlapping manner in a register bank constituted by an internal RAM. This is a characteristic feature.

く作 用〉 レジスタセットの一部をオーバーラツプさせることによ
り、従来必要であったパラメータの受は渡しのためのデ
ータ転送処理を不要とすることができる。また、サブル
ーチンで使用するレジスタ数に応じて、オーパーラ・ノ
ブ部分のレジスタ数を適宜設定することにより、内部R
AMの効率的使用が可能となる。
Function: By overlapping a part of the register set, data transfer processing for receiving and passing parameters, which was necessary in the past, can be made unnecessary. In addition, by appropriately setting the number of registers in the operating knob section according to the number of registers used in the subroutine, internal R
It becomes possible to use AM efficiently.

〈実施例〉 以下1図面に従って本発明に係るマイクロコンピュータ
の一実施例を詳細に説明する。
<Embodiment> An embodiment of a microcomputer according to the present invention will be described in detail below with reference to one drawing.

第1図に、本発明に係るマイクロコンピュータの一実施
例の内部ブロック図を示す。図に於いてDBはデータバ
ス、ROMはプログラムメモリ。
FIG. 1 shows an internal block diagram of an embodiment of a microcomputer according to the present invention. In the figure, DB is a data bus and ROM is a program memory.

PCはプログラムカウンタ、ALUは演算器。The PC is a program counter, and the ALU is an arithmetic unit.

To、T□はテンポラリレジスタ、IRは命令レジスタ
、IDは命令デコーダ、TCはタイミング制御部、RA
Mは内部RAM、RPは内部RAM上のレジスタ上1ト
の位置を指定するレジスタポインタ、ADDERは命令
レジスタ15内のレジスタ番号とレジスタバンタRPの
内容を加算する加算器で、その結果が、内部RAMのア
ドレス入力となる。すなわち、命令中でレジスタ番号を
指定すると、そのレジスタ番号とレジスタポインタの内
容が加算され、その結果で示される内部RAM上の領域
(レジスタ)がアクセスされる。
To, T□ are temporary registers, IR is an instruction register, ID is an instruction decoder, TC is a timing control unit, RA
M is the internal RAM, RP is a register pointer that specifies the position of one register on the internal RAM, and ADDER is an adder that adds the register number in the instruction register 15 and the contents of the register RP. This is the RAM address input. That is, when a register number is specified in an instruction, the register number and the contents of the register pointer are added, and the area (register) on the internal RAM indicated by the result is accessed.

例えば、レジスタセットを構成するレジスタ数がr16
J(レジスタ15設定手段ジスタ15)で。
For example, the number of registers that make up the register set is r16.
J (register 15 setting means register 15).

レジスタポインタの内容がrlooJとすると、内部R
AMの100番地から115番地にレジスタセノトが構
成され、レジスタ8を指定すると、1(M1番地がアク
セスされる(第2図参照)。
If the contents of the register pointer are rlooJ, then the internal R
A register is constructed from addresses 100 to 115 of AM, and when register 8 is specified, address 1 (M1) is accessed (see FIG. 2).

メインルーチンでレジスタ0(100番地)からレジス
タ?(107番地)にパラメータをセノトし、サブルー
チンを呼び出す。次に、サブルーチン側で、レジスタポ
インタの内容から「8」を引く処理を実行することによ
り2メインルーチンのレジスタ0からレジスタ7がサブ
ルーチンのレジスタ8からレジスタ15にマノピングさ
れ、従来の様なデータ転送処理を行うこと無く、パラメ
ータの受は渡しが行える(第3図参照)。
Register from register 0 (address 100) in the main routine? Set the parameters to (address 107) and call the subroutine. Next, on the subroutine side, by executing the process of subtracting "8" from the contents of the register pointer, registers 0 to 7 of the 2nd main routine are manoped to registers 8 to 15 of the subroutine, and the data is transferred as before. Parameters can be received and passed without any processing (see Figure 3).

また、サブルーチンに必要なレジスタ数だけレジスタポ
インタの内容を減ずればよく、内部RAMを効率的に使
用できる。例えば、サブルーチンで必要なレジスタ数が
「5」であれば、「5」を減ずればよい。
Furthermore, the contents of the register pointer need only be reduced by the number of registers required for the subroutine, and the internal RAM can be used efficiently. For example, if the number of registers required for a subroutine is "5", then "5" can be subtracted.

〈発明の効果〉 以上詳細に説明したように1本発明によれば、サブルー
チン呼び出し時に於けるパラメータの受は渡しを高速に
実行することができ、オーバーヘノドの低減をはかるこ
とができる。筐た。サブルーチンで使用するレジスタ数
に応じて、レジスタバンクを構成する内部RAMの量を
設定できるため、内部RAMを効率よく使用することが
できる。
<Effects of the Invention> As described above in detail, according to the present invention, parameters can be passed at high speed when a subroutine is called, and overhead can be reduced. It was a cabinet. Since the amount of internal RAM constituting a register bank can be set according to the number of registers used in the subroutine, the internal RAM can be used efficiently.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るマイクロコンピュータの一実施例
の内部ブロック図、第2図はレジスタポインタの内容と
レジスタセットとの関係を示す図。 第8図はメインルーチン・レジスタセットとサブルーチ
ン・レジスタセノトとの関係を示す図である。 符号の説明 RAM:内部RAM、RP ニレジスタボインタ、AD
DER:加算器。
FIG. 1 is an internal block diagram of an embodiment of a microcomputer according to the present invention, and FIG. 2 is a diagram showing the relationship between the contents of a register pointer and a register set. FIG. 8 is a diagram showing the relationship between the main routine register set and the subroutine register set. Code explanation RAM: Internal RAM, RP register pointer, AD
DER: Adder.

Claims (1)

【特許請求の範囲】[Claims] 1、内部RAMにより構成されるレジスタバンクにおい
て、隣接するレジスタセットの一部をオーバーラップし
て設定する手段を具備したことを特徴とするマイクロコ
ンピュータ。
1. A microcomputer characterized by comprising means for setting a part of adjacent register sets in an overlapping manner in a register bank constituted by an internal RAM.
JP1170302A 1989-06-30 1989-06-30 Microcomputer Pending JPH0335324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1170302A JPH0335324A (en) 1989-06-30 1989-06-30 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1170302A JPH0335324A (en) 1989-06-30 1989-06-30 Microcomputer

Publications (1)

Publication Number Publication Date
JPH0335324A true JPH0335324A (en) 1991-02-15

Family

ID=15902451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1170302A Pending JPH0335324A (en) 1989-06-30 1989-06-30 Microcomputer

Country Status (1)

Country Link
JP (1) JPH0335324A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704858B1 (en) 1999-06-09 2004-03-09 Nec Electronics Corporation Information processor and method for switching those register files
US7555631B2 (en) 1991-07-08 2009-06-30 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7555631B2 (en) 1991-07-08 2009-06-30 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets
US6704858B1 (en) 1999-06-09 2004-03-09 Nec Electronics Corporation Information processor and method for switching those register files

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