JPH02196333A - Subroutine calling system - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of an argument when a subroutine is carried out by designating an optional register for transfer of the argument data with a subroutine calling instruction. CONSTITUTION:A register number 31 can be designated with a subroutine calling instruction 3 for transfer of data. A subroutine main body 2 indirectly designates a virtual register number 21 that does not exist as a data transfer register. A virtual register access means 13 is added to a processor 1 to replace the register number 21 which is indirectly designated with an instruction stored in the main body 2 with the register number 31 designated by the instruction 3 and performs an access. In such a way, a register that presently stores the argument data is designated as it is as a data transfer register. As a result, no process is required for setting the transfer data and the processing time is shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding subroutine calls in a program using machine language instructions of an information processing device, for the purpose of improving the efficiency of passing arguments during subroutine execution, the main body of the subroutine includes a function for passing argument data. A means for indirectly specifying a register with a virtual register number that does not exist, a means for specifying a register for passing argument data in a subroutine call instruction, and a means for specifying a register for passing argument data in a subroutine call instruction; A virtual register access means is provided for accessing by replacing the virtual register number specified by the subroutine call instruction with a register number specified by the subroutine call instruction, and the subroutine call instruction is configured to specify an arbitrary register for receiving and passing argument data. .

[Industrial application field]

The present invention relates to a subroutine call instruction in an information processing device, and more particularly to improving the efficiency of passing arguments when executing a subroutine in a program using machine language instructions.

[Conventional technology]

In a program using machine language instructions, the conventional high-speed method for passing argument data (independent variables used to define the contents of a procedure and pass the necessary values when using it) when realizing a subroutine is as follows. This is done using register passing as shown below.

That is, as shown in FIG. 4, a register to which argument data is transferred is determined on the subroutine main body side, and on the subroutine calling side, the argument data is set in the determined register and the subroutine is called.

[Problems to be Solved by the Invention] The disadvantage of the argument data passing method according to the prior art described above is that, as explained below, argument data must be stored in a register determined for each subroutine, The problem is that processing before and after the call is required.

That is, before the call, it is necessary to set the passing data in the specified argument register, and if the specified register is used for another purpose, the register must be set before the call, as shown below. It is necessary to save the contents of the register and restore the contents of the register when returning from the subroutine, which increases the processing time accordingly.

FIG. 5 is a diagram showing the necessary processing described above.

FIG. 6 is a diagram showing an example of an instruction sequence when calling a subroutine.

Assuming that there is a subroutine 5IIB that uses register 5 as a data transfer register, and the caller has transfer data in register 3, the sequence of instructions before the call, after the call, and after the call is as shown in the figure. .

The problem to be solved by the present invention is to provide a subroutine calling method that eliminates such conventional problems, reduces processing for passing arguments, and shortens processing time.

[Steps for Solving the Problems] FIG. 1 is a diagram showing the configuration of means for solving the above-mentioned problems.

In the figure, 1 is a processing device. 11 is an instruction register, and 12 is a register group.

2 is the main body of the subroutine. 21 is a part of an instruction within the subroutine body that specifies a register for passing argument data, and is a virtual register number that does not actually exist.

3 is a subroutine call instruction, and 31 is an argument data transfer register number.

13 is a virtual register access means, which when the instruction placed in the instruction register 11 is an instruction in the subroutine body 2, replaces the virtual register number 21 with the argument data transfer register number 31 specified by the subroutine call instruction 3 and accesses the register. Access group 12.

[For production]

The problem with the conventional technology is that the subroutine main body 2 side
This occurs because the transfer data is requested to be placed in a specific register. If there was a mechanism in which the subroutine itself would mark the transfer data in any register, it would be possible to transfer argument data in any register, and the processing for passing argument data could be reduced.

Therefore, the present invention has the following three functions.

■Enable subroutine call instruction 3 to specify register number 31 for data exchange.

(2) In the subroutine main body 2, a non-existent virtual register number 21 is used to indirectly specify the data transfer register.

(2) The processing device 1 is provided with a means 13 for accessing by replacing the virtual register number 21 indirectly specified in the instruction in the subroutine main body 2 with the register number 31 specified by the subroutine call instruction 3.

With the above configuration, by directly designating the register where the argument data is currently stored as the data transfer register, processing for setting the transfer data becomes unnecessary, and processing time can be shortened.

[Example] Hereinafter, the present invention will be explained in more detail with reference to the example shown in FIGS. 2 and 3.

FIG. 2 is a diagram showing a method of specifying an argument data transfer register in one embodiment of the present invention.

FIG. 2(a) shows the basic structure of a subroutine call instruction.

gosub indicates a subroutine call instruction according to the present invention.

<reg> is a register number designated for data transfer, and directly specifies the register that currently contains data to be transferred.

<address> is the address of the subroutine entrance.

FIG. 2(b) is an example of a subroutine call instruction.

Since the transfer data is stored in register 3, the transfer register is designated as r3. Subroutine entry address SUB specifies the subroutine to be called.

FIG. 2(C) shows the operations of the subroutine calling side and the subroutine main body side.

In this embodiment, the subroutine body specifies the unimplemented number 0'' as a virtual register number.

“adcl r2+ ril r” in the subroutine body
o'' is a machine language instruction that executes ``Add the contents of register 1 and the contents of register O, and set it in register 2''.

In this example, the contents of the subroutine are “Register 1
Add the value of (rl) and the value of register (r3) specified by the subroutine call instruction and set it in register 2 (r2).''

Subroutine call instruction gosub r3. addr
Access address SUB by essSUB,
In the subroutine body, the value of rl and the value of r3 are added and set to r2, the process ends, and the process returns to the next address of the subroutine call instruction.

In this way, on the subroutine calling side, there is no need for any processing before or after the call.

FIG. 3 shows details of the virtual register access means in one embodiment of the present invention, in which (a) is its hardware configuration and (b) is a flowchart showing its operation.

In FIG. 3(a), 11 is an instruction register;
11 is an instruction code section, and 112 is a register specification section.

12 is a register group.

A decoder 14 decodes the instruction code section 111 in the instruction register 11.

131 is a 0 determination circuit, which determines whether the value in the register designation section 112 is "0" or not.

Reference numeral 132 denotes an argument register number storage register, which temporarily stores the value of the register designation section 112 of the subroutine call instruction.

A multiplexer 133 selects one of the input data of one register number.

The operation will be described below with reference to the flowchart in FIG. 3(b).

A machine language instruction is set in the instruction register 11, and the decoder 1
4, the instruction code section 111 is decoded.

If the decoder 14 decodes the instruction as a normal instruction (not a subroutine call instruction) and the O determination circuit 131 determines that the contents of the register designation section 112 are not "'0", the contents of the register designation section 112 The contents (register number specified by the instruction) are transferred to register group 12 through signal line a.
The register specified by the instruction is read.

If the decoder 14 decodes it as a subroutine call instruction, the register number placed in the register specification section 112 is passed through the signal line to the argument register number storage register 1.
32.

When the decoder 14 decodes it as a normal instruction that is not a subroutine call instruction (in this case, all instructions other than the subroutine call instruction are included, and of course instructions within the subroutine itself are also included), and the 0 judgment circuit 131
If it is determined that the contents of the register specifying section 112 are 0'', the 0 determination circuit 131 controls the multiplexer 133, selects the input on the signal line C side, and selects the input from the register held by the argument register number storage register 132. The register group 12 is accessed by the number and the register is read.

Since the register number "0" is an unimplemented register number, among the instructions placed in the instruction register 11, the value of the register specification field 112 is '0' only for the virtual register access instruction in the subroutine body 2. This is the only instruction that the 0 determination circuit 131 determines as 0''.

Therefore, when a subroutine call instruction comes, the register number placed in the register specification section 112 of the instruction is stored in the argument register number storage register 132, and when a virtual register access instruction within the subroutine body comes, the register specification of the instruction is stored in the argument register number storage register 132. The register group 12 is accessed using the register number stored in the argument register number storage register 132, rather than the "0" placed in the section.

As explained above, the O determination circuit 131, the argument register number storage register 132, and the multiplexer 133 allow the subroutine call instruction to specify the virtual register number (“0”′) indirectly specified by the subroutine body 2 as the one for passing argument data. You can access it by replacing it with the registered register number. As a result, the subroutine main body 2 reads the argument data in the argument passing register specified by the subroutine call instruction and executes the predetermined subroutine.

[Effects of the Invention] As is clear from the above description, according to the present invention, when executing a subroutine in a program of machine language instructions,
There is a significant industrial effect of reducing the overhead of subroutine calls and shortening processing time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the present invention. FIG. 2 is a diagram showing how to specify the argument data transfer register in one embodiment of the present invention. FIG. 3 is a diagram showing the configuration and operation of one embodiment of the present invention. 4 is a diagram showing the exchange of argument data when calling a subroutine, FIG. 5 is a diagram showing processing when calling a subroutine, and FIG. 6 is a diagram showing an example of an instruction sequence when calling a subroutine. In the figure, 1 is the processing device, 2 is the subroutine body, and 3
is a subroutine call instruction, 11 is an instruction register, 111 is an instruction code section, 112 is a register specification section, 12 is a register group, 13
131 is a virtual register access means, 131 is an O determination circuit, 132 is an argument register number storage register, 133 is a multiplexer, 21 is a virtual register number, and 31 is an argument data transfer register number. Patent applicant: Director of the Agency of Industrial Science and Technology Sachi Iizuka

Claims (1)

[Claims] When a subroutine is called by a machine language instruction in the information processing device (1), a register for passing argument data is set in the subroutine body (2) as a virtual register number (21) that does not exist.
and means for specifying a register number (31) for passing argument data to the subroutine call instruction (3); virtual register access means (13) for accessing by replacing the virtual register number (21) indirectly specified in the instruction with the register number (31) specified by the subroutine call instruction (3);
), and the subroutine call instruction (3) is configured to specify an arbitrary register for passing argument data.