JPH0334670B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory device that has a gate insulating film having a memory function and that allows a threshold voltage to be freely shifted in parallel.

Electrically rewritable read-only memory (EAROM), which uses two-layer insulated gate field-effect transistors, has recently attracted attention as a storage device that is nonvolatile and electrically rewritable. . This type of memory device is MNOS (Metal-Nitride-Oxide-
Semiconductor) is well known.

This memory transistor is generally constructed as shown in FIG. An N ⁺ type drain region 2 and an N ⁺ type source region 3 are formed in a spaced apart manner in a P type semiconductor substrate 1, and a thickness of 500 mm is formed on the junction between the drain region 2 and source region 3 and the semiconductor substrate 1.
A thick silicon oxide film 4 of ~1500 mm is provided, and an extremely thin silicon oxide film 5 of 15 to 30 mm is further formed in the center of the channel between these layers. On this silicon oxide film 5, a silicon nitride film 6 having a memory function is formed to a thickness of 400 to 600 mm, and a conductor layer such as aluminum is further provided on this film to form a gate electrode 7, a drain electrode 8, and a source electrode. The structure is such that electrodes 9 are formed respectively.

A memory transistor having such a configuration generally exhibits characteristics as shown in FIG.

As shown in the figure, the threshold voltage of the N-channel memory transistor after erasing (hereinafter referred to as V _TH ) is on the negative side, and the threshold voltage of the drain/source protection part formed with the thick silicon oxide film 4 is on the negative side. Since V _TH is an enhancement type to obtain selectivity of memory cells, it is several volts on the positive side. Therefore, V _TH after erasing the memory section and V _TH after writing
(hereinafter referred to as threshold voltage window ΔV _TH )
became quite narrow, and if LSI memory was configured as is, the guaranteed memory retention time would be shortened. In other words, this type of memory transistor has the characteristic that V _TH after writing and V _TH after erasing attenuate over time, and the threshold voltage window ΔV _TH becomes smaller over time. A small _TH means a short memory retention time.

Therefore, in order to lengthen the memory retention time, it is desirable to make the initial threshold voltage window ΔV _TH as large as possible, and one way to do this is to change the threshold voltage window ΔV _TH in the positive direction as shown in Figure 3. It is possible to move in parallel.

As described above, the conventional method of moving the threshold voltage window ΔV _TH parallelly in the positive direction is to implant ions into the surface of the semiconductor substrate in the memory area to form an impurity layer with a higher surface impurity concentration than the surrounding area. It is being This method uses MOS transistors.
This method is similar to the method used for V _TH control. For example, boron is ion-implanted through a thick gate insulating film at an accelerating voltage of 50 to 60 kV, then the thick gate insulating film is removed, and a thin film is injected onto the semiconductor substrate surface in the removed area. A silicon oxide film is provided, a silicon nitride film is provided on top of the silicon oxide film, and a conductive layer of aluminum or the like is further provided on top of the silicon oxide film to form an MNOS transistor.

Here, the principle of selecting memory cells in EAROM will be briefly explained with reference to FIG.

Generally, a 1-transistor/cell system consisting of one MNOS transistor is used as a memory cell. In this case, the erase operation is
As shown in Figure A, this is done by grounding the gate electrode of the MNOS transistor and applying a write voltage V _W to the substrate, so that V _TH becomes a low level "0". On the other hand, a write operation is performed by grounding the substrate and applying a write voltage V _W to the gate electrode, as shown in FIG. 4B, and V _TH becomes a high level "1". Furthermore, to write “0”, that is, write inhibit operation, a write voltage is applied to the gate electrode as shown in Figure 4C.
This is done by applying V _W and simultaneously applying a write voltage V _W to the drain electrode and source electrode, and V _TH remains at a low level "0".

The present inventors used a conventional ion implantation method (implanting boron through a thick gate insulating film at an acceleration voltage of 60 kV and a dose of ~10 ¹³ cm ^-2 ).
Threshold voltage of the memory part of the MNOS transistor
Although V _TH was moved in parallel by 3 to 4 times, V _TH should remain at the low level “0” in write-protect mode.
A malfunction has occurred in which the signal moves toward the write level "1" or moves beyond the write level.

As a result of studying this phenomenon, it is believed that the malfunction occurs due to the following reasons. In the MNOS structure, since the dielectric constant of the silicon nitride film is high and the gate insulating film is thin, the surface impurity concentration must be set to ~10 ¹⁸ cm ^-3 in order to shift V _TH in parallel by 3 to 4 V. In addition, boron is accelerated at a voltage of 60kV through a silicon oxide film of the same thickness as the drain/source protection part.
However, the impurity profile in this case has a peak impurity concentration at a depth of more than 1000 mm from the semiconductor substrate surface. Furthermore, in the conventional method, one or two heat treatment steps are added after ion implantation, which further broadens the impurity profile.

For these reasons, the implanted boron ions do not contribute much to the effect of moving the V _TH of the MNOS transistor in parallel, but rather become a cause of malfunction in the write inhibit mode. This is the write voltage applied to the gate electrode in write protect mode.
When V _W is applied and a write voltage V _W is simultaneously applied to the drain electrode and source electrode, a boron impurity layer with an impurity concentration peak at a depth of 1000 mm or more is formed on the semiconductor substrate surface. This is thought to be because avalanche breakdown occurs when the substrate surface is exposed to a high electric field, and electrons are accelerated until impact ionization occurs and are easily trapped near the boundary between the thin oxide film and the nitride film.

The present invention has been made in view of the above, and an object of the present invention is to expand the threshold voltage window so that it can be effectively used by moving the threshold voltage window in parallel without malfunctioning in write-protect mode. However, an object of the present invention is to provide a nonvolatile semiconductor memory device that can maintain a long memory retention time.

That is, the present invention provides a semiconductor substrate of a first conductivity type, a source/drain region of a second conductivity type formed on the surface of this substrate and electrically isolated from each other, and a channel between these source/drain regions. , a thin oxide film formed on a central portion separated from the drain region by a desired distance, a thick oxide film formed at least on a region of the channel other than this thin oxide film, and a thin oxide film formed on each of the oxide films. A gate insulating film having a memory function, a gate electrode provided on the gate insulating film, and a gate electrode formed on the semiconductor substrate surface under the thin oxide film, having an impurity concentration peak at a depth of 500 Å or less from the substrate surface. rice cake,
and the impurity concentration at a depth exceeding 500 Å is ¹⁰ cm.
The present invention is a nonvolatile semiconductor memory device characterized by comprising a first conductivity type impurity layer having an impurity concentration profile of ^-3 or less.

For example, a silicon nitride film can be used as the gate insulating film.

In order to form an impurity layer having the above impurity profile, for example, a method of ion-implanting impurities of the second conductivity type into the semiconductor substrate from above the gate insulating film at a low acceleration voltage of about 20 kV can be adopted.

Therefore, according to the present invention, when boron is ion-implanted into an MNOS transistor at an accelerating voltage of 20 kV, the impurity profile has a peak of impurity concentration at a depth of 500 Å or less from the semiconductor substrate surface, as shown by the solid line a in the graph of FIG. The impurity concentration is 10 ¹⁸ cm ^-3 or less at a depth of more than 500 Å from the substrate surface. By forming the impurity profile in this way, the threshold voltage window ΔV _TH can be translated in the positive direction, expanding the threshold voltage window ΔV _TH that can be effectively used, and moreover, the impurity can be implanted into the semiconductor substrate. Since the total amount of impurities is small and there is no post-implantation heat treatment, the vertical electric field is small.
Malfunctions can be prevented.

On the other hand, when boron ions are implanted through a silicon oxide film using the conventional method at an acceleration voltage of 60 kV and ~10 ¹³ cm ^-2, the impurity profile is 5th.
This is shown by the broken line b in the graph of the figure. In this case, the impurity concentration peak is at a depth of 500 Å or more from the semiconductor substrate surface, and the peak concentration is 10 ¹⁸
cm ^-3 , so the total amount of impurities is large.
As a result, the threshold voltage window ΔV _TH can be shifted in parallel by 3 to 4 V in the positive direction, but as mentioned above, avalanche breakdown occurs due to the vertical electric field near the semiconductor substrate surface, and the erased V _TH A malfunction occurs in which data is written at a level higher than the write level.

Next, an embodiment in which the present invention is applied to an MNOS transistor will be described.

6A to 6F sequentially show the manufacturing process. First, as shown in FIG. 6A, a P-type semiconductor substrate (for example, a silicon substrate with an impurity concentration of about 10 ¹⁵ cm ^-3 ) 1
A silicon oxide film 10 with a thickness of about 1 μm is formed on the surface after selectively diffusing N-type impurities into the surface to form an N ⁺ drain region 2 and an N ⁺ source region 3 apart from each other. form.

Next, after selectively removing the silicon oxide film 10 on the gate and contact areas of the MNOS transistor, the exposed semiconductor substrate surface is thermally oxidized to
As shown in FIG. 2, a thick silicon oxide film 4 having a thickness of about 1000 Å and serving as a gate insulating film of the drain/source protection portion is formed.

Next, after removing the silicon oxide film 4 at the center of the channel several μm away from the drain region 2 and source region 3 of the MNOS transistor, the exposed semiconductor substrate surface is further thermally oxidized to a thickness as shown in FIG. Extremely thin silicon oxide film 5 of about 15 to 30 Å
form.

Next, as shown in FIG.
Forms between 400 and 600 Å. At this stage, a heat treatment process is appropriately performed to improve the surface mobility of the MNOS transistor and to improve the memory retention characteristics.

Next, as shown in FIG.
A P-type impurity (for example, boron) is directly ion-implanted at a dose of, for example, about 10 ¹³ cm ^-2 to form an impurity whose impurity concentration has a peak near the surface of the semiconductor substrate 1 as shown by the solid line a in the graph of FIG. A profile P-type impurity layer 11 is formed. In this case, the thick silicon oxide film 4 serves as a protective mask in the drain/source protection portion, and the implanted P-type impurity does not reach there, so that the concentration does not change. Furthermore, since a low accelerating voltage is used for ion implantation, the implanted P-type impurities seep out in the lateral direction from the memory section to the semiconductor substrate surface of the drain/source protection section to a very small extent.

Next, as shown in FIG. 6F, after forming contacts for taking out the electrodes, a conductive layer such as aluminum is deposited on the entire surface, and an etching process is performed to form the gate electrode 7, drain electrode 8, and source electrode. 9 are respectively formed to manufacture an MNOS transistor.

In the MNOS transistor obtained in this way, ion implantation is performed directly onto the silicon nitride film 6 at a low acceleration voltage, so that surface impurities in the drain/source protection portion covered with the thick silicon oxide film 4 are removed. A P-type impurity layer 11 is formed that has a peak impurity concentration at a depth of 500 Å or less on the surface of the semiconductor substrate in the memory portion without changing the concentration, and has an impurity concentration of 10 ¹⁸ cm ^-3 or less at a depth exceeding 500 Å. be able to. Further, in the above method, there is almost no heat treatment step as in the conventional method after ion implantation, so there is no re-diffusion of the ion-implanted P-type impurity into the semiconductor substrate, and a sharply shaped impurity profile can be formed.

Therefore, in the MNOS transistor obtained in the above embodiment, by forming the P-type impurity layer 11, the threshold voltage window ΔV _TH is shifted in parallel in the positive direction,
In addition, by keeping the threshold voltage of the drain-source protection section fixed, the threshold voltage window ΔV _TH that can be effectively used is expanded, as shown in Figure 3, and the memory retention characteristics can be greatly improved. ,Also
Since the level of the threshold voltage window ΔV _TH of the MNOS transistor can be freely controlled, the read voltage can be easily set. Furthermore, by defining the impurity profile of the P-type impurity layer 11 formed by ion implantation, malfunctions in the write inhibit mode can be prevented.

In fact, an MNOS transistor (example) according to the present invention in which the p ⁺ type impurity layer at the center of the channel has the impurity concentration profile shown by ^a in FIG. For the conventional MNOS transistor (conventional example) having the impurity concentration profile shown by b in Figure 5, erase operation is performed by applying -30V (Figure 4A)
After performing the write operation ( _fourth
Figure B) or write inhibit operation (Figure 4 C),
Thereafter, the threshold voltage was measured and the results are shown in FIG.

As mentioned above, in this example, after forming a thin oxide film and a nitride film on it in advance, boron was passed through them at an acceleration voltage of 20 kV and a dose of 8×10 ¹²
A p ⁺ type impurity layer is formed in the center of the channel by ion implantation under cm ^-2 conditions.
In the conventional example, boron is accelerated through a thick oxide film using a voltage
A p ⁺ -type impurity layer is formed in the center of the channel by ion implantation at 60 kV and a dose of 2 x 10 ¹³ cm ^-2 , and then a thin oxide film and a nitride film are formed on it. Also, the threshold voltage is
A drain voltage of 5.0V is applied, the relationship between the gate voltage and the source/drain current is examined, and by extrapolation, the gate voltage is defined as the value when the source/drain current = 0 μA.

As is clear from FIG. 7, the threshold voltage window (the difference between the threshold voltage after a write operation and the threshold voltage after an erase operation) is about 1 V higher in the embodiment than in the conventional example. It's getting bigger. Furthermore, in the conventional example, as the applied voltage during the write inhibit operation increases, the threshold voltage rapidly rises, resulting in the same state as when writing has been performed. On the other hand, in the embodiment, even if the applied voltage during write inhibit operation increases, the threshold voltage does not change. Here, a memory matrix is constructed using the memory cells of the embodiment and the conventional example, and selective writing is performed by performing a write operation and a write inhibit operation in a plurality of memory cells connected to the same gate line. Think about the case. As described above, in the conventional example, even though a write inhibit operation is performed, the state remains the same as if writing had been performed, resulting in erroneous writing. On the other hand, such a problem does not occur in the embodiment.

Although the above embodiments have been described with reference to the case where an n-channel type device is manufactured, the present invention is not limited to this, and can also be applied to the case where a p-channel type device is manufactured. In this case, the threshold voltage window ΔV _T.H.
will translate in the negative direction. Further, the nonvolatile semiconductor memory device of the present invention includes:
It can be applied not only to devices with the MNOS structure but also to devices such as the MAOS structure, which are made of a gate insulating film that has a memory function including trap levels.

As explained above, according to the nonvolatile semiconductor memory device of the present invention, by forming an impurity layer having a peak near the surface of the semiconductor substrate, the threshold voltage window can be closed without malfunctioning in the write inhibit mode. By moving in parallel, the threshold voltage window that can be effectively used can be expanded, and long-term memory retention characteristics can be maintained satisfactorily.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of an N-channel MNOS transistor with a conventional structure. Figure 2 is an I _DS -V _G characteristic diagram showing the threshold voltage of the drain-source protection section after writing and erasing of the MNOS transistor. 3
The figure is an I _DS -V _G characteristic diagram showing a state in which the threshold voltage of FIG. 2 is shifted in parallel, and FIGS. FIG. 5 is a graph showing the impurity profile implanted into the memory area in the case of the present invention and in the conventional case, and FIGS. 6A to 6F show the steps for manufacturing the MNOS transistor according to the present invention. FIG. 7 is a cross-sectional view sequentially showing the MNOS transistor of the embodiment of the present invention and the conventional example.
FIG. 3 is a diagram showing the relationship between applied voltages in erase, write, and write inhibit operations and threshold voltages after each operation. 1... Semiconductor substrate, 2... Drain region, 3...
...source region, 4,5,10...silicon oxide film, 6...silicon nitride film, 7...gate electrode,
8...Drain electrode, 9...Source electrode, 11...
...Impurity layer.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed on the surface of this substrate and electrically isolated from each other, and a channel between these source and drain regions. a thin oxide film formed on a central portion separated from the source and drain regions by a desired distance; a thick oxide film formed at least on a region of the channel other than this thin oxide film; and a thick oxide film formed on each of the oxide films. a gate insulating film having a memory function; a gate electrode provided on the gate insulating film; Has a concentration peak and 500〓
a first conductivity type impurity layer having an impurity concentration profile of 10 18 cm ^-3 or less at a depth exceeding 10 ¹⁸ cm -3 . 2. Claim 1, characterized in that the gate insulating film having a memory function is a silicon nitride film.
The non-volatile semiconductor memory device described in 2.