JPH0334339A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0334339A JPH0334339A JP1169505A JP16950589A JPH0334339A JP H0334339 A JPH0334339 A JP H0334339A JP 1169505 A JP1169505 A JP 1169505A JP 16950589 A JP16950589 A JP 16950589A JP H0334339 A JPH0334339 A JP H0334339A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- thin film
- metal wire
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 abstract description 18
- 230000001681 protective effect Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 229910001111 Fine metal Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 229910052804 chromium Inorganic materials 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000004021 metal welding Methods 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
- H01L2224/78314—Shape
- H01L2224/78317—Shape of other portions
- H01L2224/78318—Shape of other portions inside the capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にボンディングパッドを
有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having bonding pads.
従来の半導体装置は、第3図(a)、(b)に示すよう
にシリコン基板lの上に設けた酸化シリコン膜2の上に
選択的に設けた厚さ1〜3μmのAJ層f″Al層3を
含む表面に設けた保護膜5と、Al層3の上の保護膜5
に設けた開孔部6によりボンディングパッドを形成して
おり、ボンディングは開孔部6のAl層3の表面に金属
細線を熱圧着法又は超音波振動による金属間溶接法を用
いて接続していた。A conventional semiconductor device has an AJ layer f'' with a thickness of 1 to 3 μm selectively provided on a silicon oxide film 2 provided on a silicon substrate l, as shown in FIGS. 3(a) and 3(b). A protective film 5 provided on the surface including the Al layer 3, and a protective film 5 on the Al layer 3.
A bonding pad is formed by the opening 6 provided in the opening 6, and the bonding is performed by connecting a thin metal wire to the surface of the Al layer 3 in the opening 6 using thermocompression bonding or metal-to-metal welding using ultrasonic vibration. Ta.
最近ICチップの大電流化、高速化につれ、ボンディン
グパッドのAl層3の厚さが厚くなり、3μmの厚さを
有するものも出現している。しかし、超音波ウェッジボ
ンディングを用いた場合、Al層3の厚さが1.5μm
以上になると、パッドのAI!層の表面がめくれて剥れ
る現象が発生した。Recently, as the current and speed of IC chips have increased, the thickness of the Al layer 3 of the bonding pad has become thicker, and some have a thickness of 3 μm. However, when using ultrasonic wedge bonding, the thickness of the Al layer 3 is 1.5 μm.
When it comes to the above, the AI of the pad! A phenomenon occurred in which the surface of the layer turned over and peeled off.
第4図(a)〜(C)はボンディングの過程を説明する
ための動作中−順に示した模式的断面図である。FIGS. 4(a) to 4(C) are schematic cross-sectional views sequentially shown during operation to explain the bonding process.
第4国学(a )に示すように、ボングーのウェッジツ
ール7により金属細線8をボンディングパッドのAl層
30表面に加圧すると共に超音波振動9を印加する。As shown in FIG. 4 (a), a fine metal wire 8 is pressed against the surface of the Al layer 30 of the bonding pad using a Bongu wedge tool 7, and ultrasonic vibrations 9 are applied.
次に、第4図(b)に示すように、初期の段階では、金
属細線8はパッドのAl層3の上をすべっているが、次
第に金属細線3とパッドのAI層名
3の接割く始まる。接合が開始されると、それにひきつ
づいて、AI!層3が、塑性流動lOを起こし始める。Next, as shown in FIG. 4(b), at the initial stage, the thin metal wire 8 is sliding on the Al layer 3 of the pad, but gradually the contact between the thin metal wire 3 and the AI layer 3 of the pad begins to slide. It begins. Once the joining begins, the AI! Layer 3 begins to undergo plastic flow lO.
次に、第4図(C)に示すように、さらに接続が継続さ
れると、塑性流動10により、パッドのAl層3の表面
が金属細線8と保護膜5の間よりめくれ上り、Aj41
1を発生する。Next, as shown in FIG. 4(C), when the connection is continued, the surface of the Al layer 3 of the pad is turned up from between the thin metal wire 8 and the protective film 5 due to the plastic flow 10, and Aj41
Generates 1.
が狭い場合に隣接パッドの金属細線に接触して短線
縮させる原因となり、又、遊離した場合は、半導鰺
体チップの内部配線間の短糟を生じて半導体装置の信頼
性を低下させるという問題点がある。If the pads are narrow, they may come into contact with the thin metal wires of adjacent pads, causing the wires to shorten, and if they become loose, they can cause short breaks between the internal wiring of the semiconductor chip, reducing the reliability of the semiconductor device. There is a problem.
〔課題を解決するための手段二
本発明の半導体装置は、パッド部の、1層よりも硬度が
高く、尚かつAl層との接合性の良い薄膜を、パッド部
のA、 1層の表面に設けている。[Means for Solving the Problems 2] In the semiconductor device of the present invention, a thin film having higher hardness than the first layer of the pad portion and having good bonding properties with the Al layer is used as the surface of the first layer A of the pad portion. It is set up in
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a>、(b)は、本発明の第1の実施例の平面
図及びA−A’轢断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the first embodiment of the present invention.
第1図(a)、(b)に示すように、シリコン基板lの
上に酸化シリコン膜2を設け、酸化シリコン膜2の上に
Aj層3を1〜3μmの厚さに堆C0やStを1〜2%
含有するAA又はWS+等の薄膜を0.O1〜0.1μ
mの厚さに堆積し、こド部を含む表面に保護膜5を堆積
して薄膜4の上の保護膜5を選択的にエツチングして開
孔部6を設ける。As shown in FIGS. 1(a) and 1(b), a silicon oxide film 2 is provided on a silicon substrate l, and an Aj layer 3 is deposited on the silicon oxide film 2 to a thickness of 1 to 3 μm. 1-2%
A thin film of AA or WS+ containing 0. O1~0.1μ
A protective film 5 is deposited on the surface including the corners, and the protective film 5 on the thin film 4 is selectively etched to form an opening 6.
ってAI!層3と接合する。That's AI! Bonded with layer 3.
ここで、薄膜4は超音波振動によるAl層の塑ディング
が実現できる。Here, the thin film 4 can realize plasticizing of the Al layer by ultrasonic vibration.
第2図(a)、(b)は、本発明の第2の実施例の平面
図及びB=8’線断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line B=8' of a second embodiment of the present invention.
第2図(a)、(b)に示すように、パッドの開孔部6
の内周近傍の1層3の表面にのみ薄膜4を環状に設けて
パッドの中央部の、1層3の表面を露出させた以外は第
1の実施例と同じ構成を有しており、パッド中央部はA
l層3が露出しており、金属細線との接続はこの部分に
て直接強固に行われるので、良好な導電性が得られると
いう利点がある。As shown in FIGS. 2(a) and (b), the opening 6 of the pad
It has the same structure as the first embodiment, except that a thin film 4 is annularly provided only on the surface of the first layer 3 near the inner circumference of the pad, and the surface of the first layer 3 in the center of the pad is exposed. The center of the pad is A
Since the L layer 3 is exposed and the connection with the thin metal wire is made directly and firmly at this portion, there is an advantage that good conductivity can be obtained.
以上説明したように本発明は、パッド部の厚いAl層の
上にAlより硬度の高い薄膜を設けるこの発生を防ぎ半
導体装置の信頼性を向上させるという効果を有する。As explained above, the present invention has the effect of preventing this occurrence by providing a thin film harder than Al on the thick Al layer of the pad portion and improving the reliability of the semiconductor device.
第1図(a)ib)は本発明の第1の実施例の平面図及
びA−A’線断面図、第2図(a)。
(b)は本発明の第2の実施例の平面図及びB−B′線
断面図、第3図(a)、(b)は従来の半導体装置の平
面図及びc−c’線断面図、第4図(a)〜(C)はボ
ンディングの過程を説明するための動作手順に示した模
式的断面図である。
1・・・・・・シリコン基板、2・・・・・・酸化シリ
コン膜、3・・・・・・Al1層、4・・・・・・薄膜
、5・・・・・・保護膜、6・・・・・・開孔部、7・
・・・・・ウェッジツール、8・・・・・・金属細線、
9・・・・・・超音波振動、lO・・・・・・塑性流動
。FIG. 1(a) ib) is a plan view and a sectional view taken along the line AA' of the first embodiment of the present invention, and FIG. 2(a) is a sectional view taken along the line AA'. (b) is a plan view and a cross-sectional view taken along the line B-B' of the second embodiment of the present invention, and FIGS. 3(a) and (b) are a plan view and a cross-sectional view taken along the line c-c' of a conventional semiconductor device. , and FIGS. 4(a) to 4(c) are schematic cross-sectional views showing the operating procedure for explaining the bonding process. 1...Silicon substrate, 2...Silicon oxide film, 3...Al1 layer, 4...Thin film, 5...Protective film, 6...Opening part, 7.
... Wedge tool, 8 ... Thin metal wire,
9...Ultrasonic vibration, lO...Plastic flow.
Claims (1)
において、前記Al層の表面にAl層よりも硬度が高く
且つAl層と結合性の良い薄膜を設けたことを特徴とす
る半導体装置。1. A semiconductor device having a bonding pad made of an Al layer, characterized in that a thin film having higher hardness than the Al layer and having good bonding properties with the Al layer is provided on the surface of the Al layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1169505A JPH0334339A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1169505A JPH0334339A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0334339A true JPH0334339A (en) | 1991-02-14 |
Family
ID=15887758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1169505A Pending JPH0334339A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0334339A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6979139B2 (en) | 2003-06-27 | 2005-12-27 | King Jim Co., Ltd. | Printing apparatus, printing method, and program therefor |
-
1989
- 1989-06-29 JP JP1169505A patent/JPH0334339A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6979139B2 (en) | 2003-06-27 | 2005-12-27 | King Jim Co., Ltd. | Printing apparatus, printing method, and program therefor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6250864B2 (en) | Power semiconductor device | |
US6864166B1 (en) | Method of manufacturing wire bonded microelectronic device assemblies | |
JP2003209134A (en) | Semiconductor device and its manufacturing method | |
JPH07114214B2 (en) | Semiconductor device | |
US5442241A (en) | Bump electrode structure to be coupled to lead wire in semiconductor device | |
JPH0334339A (en) | Semiconductor device | |
JP2001176966A (en) | Semiconductor device | |
JP3151324B2 (en) | Semiconductor device | |
JPH01244625A (en) | Semiconductor device | |
JPH02114545A (en) | Connection of wire bonding | |
JPH0225045A (en) | Semiconductor device | |
JPS63293930A (en) | Electrode in semiconductor device | |
JPH01318236A (en) | Semiconductor device and manufacture thereof | |
JP3800929B2 (en) | Semiconductor package, manufacturing method thereof, and insulating tape substrate for semiconductor package | |
JP3213923B2 (en) | Underbarrier metal ribbon for bump formation and bump formation method | |
JP3220524B2 (en) | Bare chip | |
JP2006120893A (en) | Semiconductor device and its manufacturing method | |
JPH07201865A (en) | Semiconductor device provided with bump | |
JP2005302941A (en) | Manufacturing method of semiconductor device | |
JPH04258145A (en) | Semiconductor device | |
JPH05136221A (en) | Probe and inspection method using it | |
JPS61170056A (en) | Electrode material for semiconductor device | |
Tatsumi et al. | Development of ultra-fine pitch ball bonding technology | |
JPS63136537A (en) | Tape-shaped lead for semiconductor | |
JPS63293951A (en) | Semiconductor element electrode structure |