JPH033409A - Automatic digital gain control system - Google Patents

Automatic digital gain control system

Info

Publication number
JPH033409A
JPH033409A JP13595889A JP13595889A JPH033409A JP H033409 A JPH033409 A JP H033409A JP 13595889 A JP13595889 A JP 13595889A JP 13595889 A JP13595889 A JP 13595889A JP H033409 A JPH033409 A JP H033409A
Authority
JP
Japan
Prior art keywords
value
input signal
gain
arithmetic means
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13595889A
Other languages
Japanese (ja)
Inventor
Hisayoshi Matsui
久義 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP13595889A priority Critical patent/JPH033409A/en
Publication of JPH033409A publication Critical patent/JPH033409A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To remarkably shorten a time until an output signal is stabilized at a prescribed level after an input signal is fluctuated by dividing a prescribed preset value by the mean value of the absolute value of the amplitude value of the input signal, and setting a division result as a gain for the input signal. CONSTITUTION:The system is equipped with first arithmetic means 202, 203 to calculate the mean value of the absolute value of the amplitude value of the input signal, a second arithmetic means 204 to divide the prescribed preset value by the mean value of the absolute value obtained from the first arithmetic means 202, 203, and a third arithmetic means 201 to multiply the input signal by the output value of the second arithmetic means 204 as the gain. Since the mean value of the absolute value of the amplitude value of the input signal is found, and the prescribed preset value is divided by the mean value, and a result is set as the gain to be multiplied on the amplitude value of the input signal, a proper gain obtained in several or more cycles in conventional feedback control can be found in one cycle. Thereby, it is possible to remarkably shorten the time until the output signal is stabilized at the prescribed level after the input signal is fluctuated.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は各種のディジタル信号処理装首に使用されるデ
ィジタル自動利得制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital automatic gain control system used in various digital signal processing headpieces.

〔従来の技術〕[Conventional technology]

従来のディジタル自動利得制御方式の回路構成例を第2
図に示し、その回路の動作を以下に説明する。まず、入
力信号は、乗算器101により、加′IA器107の出
力値を乗ぜられて出力信号となり、外部に出力される。
The second example of the circuit configuration of the conventional digital automatic gain control method is
The operation of the circuit will be described below. First, the input signal is multiplied by the output value of the adder/IA unit 107 by the multiplier 101 to become an output signal, which is output to the outside.

同時に、この出力信号は自乗器102と平均化器103
とにより、自乗平均値が計算される。次いで、この自乗
平均値を減算器105においてあらかじめ定めた設定値
から減じることにより、その設定値との誤差を求める。
At the same time, this output signal is transmitted to the squarer 102 and the averager 103.
The root mean square value is calculated. Next, by subtracting this root mean square value from a predetermined set value in a subtracter 105, an error with respect to the set value is determined.

さらに、この誤差に乗算器106においである任意の係
数αを乗じる。この乗算器106の出力値と、加算器1
07の出力値を入力とするレジスタ108の出力値とを
加算器107で加算し、その結果を乗算器101に供給
することにより次の入力信号に対する利得を誤差が平に
なるように修正し、結果的に出カイ3号を一方レベルに
保っていた。
Furthermore, this error is multiplied by an arbitrary coefficient α in the multiplier 106. The output value of this multiplier 106 and the adder 1
Adder 107 adds the output value of register 108 which receives the output value of 07, and supplies the result to multiplier 101 to correct the gain for the next input signal so that the error is flat, As a result, I was able to keep Dekai No. 3 at one level.

(発明が解決しようとする課題) しかしながら上記のような従来例のディジタル自動利得
制御方式では、入力信号レベルと所望の出力信号レベル
との差が大きくなるにつれて、出力信号をその所望のレ
ベルに収束させるまでの時間が長くなる。
(Problem to be Solved by the Invention) However, in the conventional digital automatic gain control method as described above, as the difference between the input signal level and the desired output signal level increases, the output signal is converged to the desired level. It takes longer to do so.

この収束時間は、第2図に示す係数αの値を大きくすれ
ば、その値にほぼ反比例して短くなるが、ある程度以上
に係数αの値を大きくすると、入力信号レベルと所望の
出力信号レベルとの差が小さい時に、過剰制御となり、
そのため出力信号レベルの変動が大きくなってしまフた
り、さらには出力信号の発振につながる場合もある。
If the value of the coefficient α shown in Fig. 2 is increased, this convergence time will be shortened in almost inverse proportion to the value, but if the value of the coefficient α is increased beyond a certain level, the input signal level and the desired output signal level will be reduced. When the difference between
Therefore, fluctuations in the output signal level may become large, or even lead to oscillation of the output signal.

すなわち、従来方式では出力信号の収束時間をすべての
入力信号レベルにおいて一定時間以内におさえようとす
ると、入力信号レベルのダイナミックレンジが制限され
てしまうという欠点があった。
That is, in the conventional method, if an attempt is made to suppress the convergence time of the output signal within a certain period of time at all input signal levels, the dynamic range of the input signal level is restricted.

そこで、本発明は、上述のような欠点を除去し、入力信
号が変動してから出力信号が所定のレベルに安定するま
での時間を大幅に短縮することが可能となり、実用上の
入力信号レベルの許、容ダイナミックレンジを大きく広
げることができるディジタル自動利得制御方式を提供す
ることを目的とする。
Therefore, the present invention eliminates the above-mentioned drawbacks, makes it possible to significantly shorten the time from when the input signal fluctuates until the output signal stabilizes at a predetermined level, and thereby reduces the practical input signal level. The object of the present invention is to provide a digital automatic gain control method that can greatly expand the dynamic range.

(課題を解決するための手段〕 かかる目的を達成するため、本発明は、振幅の平均値が
変動する入力信号に対して指定の利得を乗じて出力信号
となし、出力信号の振幅の平均値を所定の値に保つよう
に利得を制御するディジタル自動利得制御方式であって
、入力信号の振幅値の絶対値の平均値を算出する第1の
演算手段と、所定の設定値を第1の演算手段から得られ
る絶対値の平均値で除する第2の演算手段と、第2の演
算手段の出力値を利得として入力信号に乗じる第3の演
算手段とを具備したことを特徴とする。
(Means for Solving the Problems) In order to achieve the above object, the present invention multiplies an input signal whose average value of amplitude varies by a specified gain to obtain an output signal, and calculates the average value of the amplitude of the output signal. is a digital automatic gain control method that controls the gain so as to maintain the amplitude at a predetermined value, the method includes: a first calculation means for calculating the average value of the absolute values of the amplitude values of the input signal; It is characterized by comprising a second calculation means that divides the absolute values obtained from the calculation means by the average value, and a third calculation means that multiplies the input signal by using the output value of the second calculation means as a gain.

(作 用) 木発明では、上記構成のように、従来技術のようなフィ
ードバック制御は行なわずに、入力信号の振幅値の絶対
値の平均値を求め、その平均値で所定の設定値を除算し
、その商を入力信号の振幅値に乗する利得とするように
したので、従来のフィードバック制御で数サイクル以上
かけて求めていた適正利得を1サイクルで求めることが
できる。従って、木発明によれば、入力信号が変動して
から出力信号が所定のレベルに安定するまでの時間を大
幅に短縮することが可能となり、またその結果実用上の
入力信号レベルの許容ダイナミックレンジを大きく広げ
ることができる。
(Function) In the tree invention, as in the above configuration, without performing feedback control as in the prior art, the average value of the absolute values of the amplitude values of the input signal is determined, and a predetermined set value is divided by the average value. However, since the quotient is used as the gain multiplied by the amplitude value of the input signal, it is possible to obtain an appropriate gain in one cycle, which was required to be obtained over several cycles using conventional feedback control. Therefore, according to the tree invention, it is possible to significantly shorten the time from when the input signal fluctuates until the output signal stabilizes at a predetermined level, and as a result, the allowable dynamic range of the input signal level in practical use. can be greatly expanded.

(実施例) 以下、図面を参照して本発明の実施例を詳細に説明する
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の特徴を最もよく表わすディジタル自動
利得制御方式を実施する回路の構成例を示す。同図にお
いて乗算器201の一方の入力端子には外部から振幅の
平均値が変動する入力信号S1が人力され、他の入力端
子には除算器204の圧力値が入力される。この乗算器
201の演算値は出力信号S2どなってそのまま外部へ
出力される。
FIG. 1 shows an example of the configuration of a circuit implementing a digital automatic gain control method that best represents the features of the present invention. In the figure, an input signal S1 whose average value of amplitude fluctuates is input from the outside to one input terminal of a multiplier 201, and a pressure value from a divider 204 is input to the other input terminal. The calculated value of this multiplier 201 becomes an output signal S2 and is outputted to the outside as it is.

同時に、上述の入力信号51は絶対値化器202の入力
端子にも人力され、絶対値化器202の出力値は平均化
器203の入力端子に人力される。従って、平均化器2
03の出力端子には入力信号Slの振幅値の絶対値を平
均化した平均値が出力され、その平均値は、除算器20
4の一方の入力端子に人力される。除算器204の他の
入力端子には外部から所定の設定値が人力される。
At the same time, the input signal 51 described above is also input to the input terminal of the absolute value generator 202, and the output value of the absolute value generator 202 is input to the input terminal of the averager 203. Therefore, averager 2
An average value obtained by averaging the absolute values of the amplitude values of the input signal Sl is output to the output terminal of the input signal Sl.
Manual input is input to one input terminal of 4. A predetermined setting value is manually input to the other input terminal of the divider 204 from the outside.

除算器204の出力端子には、上記の所定の設定値を入
力信号S1の絶対値の平均値で除した結果(商の値)が
出力される。
The output terminal of the divider 204 outputs the result (quotient value) of dividing the above predetermined setting value by the average value of the absolute values of the input signal S1.

この除算器204の出力を入力信号Stに乗ずべき利得
として乗算器201の一方の入力端子に人力しているの
で、入力信号S1の絶対値の平均値が求められた時点で
、即時に適正な利得を算出することが可能となる。
Since the output of the divider 204 is input to one input terminal of the multiplier 201 as the gain to be multiplied by the input signal St, the appropriate value can be immediately calculated as soon as the average of the absolute values of the input signal S1 is calculated. It becomes possible to calculate the gain.

そのため、最初の入力信号Slが人力されてから出力信
号の52のレベルが、所定の値に安定するまでの時間は
上述した従来方式に比べて大幅に短縮することができ、
入力信号レベルの変動に対する出力信号レベルの変動も
十分に小さくすることができる。
Therefore, the time from when the first input signal Sl is manually input until the level 52 of the output signal stabilizes to a predetermined value can be significantly shortened compared to the conventional method described above.
Fluctuations in the output signal level with respect to fluctuations in the input signal level can also be made sufficiently small.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のディジタル自動利得制御方式を実施す
る回路の構成例を示すブロック構成図、 第2図は従来のディジタル自動利得制御・方式の回路の
構成を示すブロック構成図である。 (発明の効果〕 以上説明したように、本発明によれば、入力信号の振幅
値の絶対値の平均値で所定の設定値を除し、その除算結
果を入力信号に対する利得とするようにしたので、従来
方式のフィードバック制御で数サイクル以上かけて求め
ていた適正利得を1サイクルで求められる。従って、本
発明によれば、入力信号が変動してから出力信号が所定
のレベルに安定するまでの時間を大幅に短縮することが
可能になり、その結果実用上の入力信号レベルの許容ダ
イナミックレンジを大きく広げることができるという優
れた効果が得られる。 201・・・ 乗算器、 202・・・ 絶対値化器、 203・・・ 平均化器、 204・・・ 除算器。 第1図 第2図
FIG. 1 is a block configuration diagram showing an example of the configuration of a circuit implementing the digital automatic gain control method of the present invention, and FIG. 2 is a block configuration diagram showing the circuit configuration of a conventional digital automatic gain control method. (Effects of the Invention) As explained above, according to the present invention, a predetermined set value is divided by the average value of the absolute values of the amplitude values of the input signal, and the division result is used as the gain for the input signal. Therefore, it is possible to obtain an appropriate gain in one cycle, which takes several cycles or more in conventional feedback control.Therefore, according to the present invention, it is possible to obtain an appropriate gain in one cycle after the input signal fluctuates until the output signal stabilizes at a predetermined level. 201... Multiplier, 202... Absolute value generator, 203... Averager, 204... Divider. Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】 1)振幅の平均値が変動する入力信号に対して指定の利
得を乗じて出力信号となし、該出力信号の振幅の平均値
を所定の値に保つように前記利得を制御するディジタル
自動利得制御方式であって、 前記入力信号の振幅値の絶対値の平均値を算出する第1
の演算手段と、 所定の設定値を前記第1の演算手段から得られる前記絶
対値の平均値で除する第2の演算手段と、 該第2の演算手段の出力値を前記利得として前記入力信
号に乗じる第3の演算手段と を具備したことを特徴とするディジタル自動利得制御方
式。
[Claims] 1) An input signal whose average value of amplitude fluctuates is multiplied by a specified gain to produce an output signal, and the gain is adjusted so as to maintain the average value of the amplitude of the output signal at a predetermined value. A first digital automatic gain control method for calculating an average value of absolute values of amplitude values of the input signal.
a second arithmetic means for dividing a predetermined set value by an average value of the absolute values obtained from the first arithmetic means; and an output value of the second arithmetic means as the gain. A digital automatic gain control system characterized by comprising a third calculation means for multiplying a signal.
JP13595889A 1989-05-31 1989-05-31 Automatic digital gain control system Pending JPH033409A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13595889A JPH033409A (en) 1989-05-31 1989-05-31 Automatic digital gain control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13595889A JPH033409A (en) 1989-05-31 1989-05-31 Automatic digital gain control system

Publications (1)

Publication Number Publication Date
JPH033409A true JPH033409A (en) 1991-01-09

Family

ID=15163820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13595889A Pending JPH033409A (en) 1989-05-31 1989-05-31 Automatic digital gain control system

Country Status (1)

Country Link
JP (1) JPH033409A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100664017B1 (en) * 2001-05-24 2007-01-03 엘지전자 주식회사 Apparatus for digital automatic gain control
KR100761421B1 (en) * 2003-12-26 2007-10-04 실트로닉 아게 Crucible for the growth of silicon crystal and process for the growth of silicon crystal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100664017B1 (en) * 2001-05-24 2007-01-03 엘지전자 주식회사 Apparatus for digital automatic gain control
KR100761421B1 (en) * 2003-12-26 2007-10-04 실트로닉 아게 Crucible for the growth of silicon crystal and process for the growth of silicon crystal

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