JPH0334080B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field The present invention provides a signal for selecting words in a speech synthesizer having a function of stopping the operation of an oscillator circuit except when speaking, in order to reduce power consumption. ,
Alternatively, the present invention relates to a speech synthesis device in which a signal for starting speech includes chattering.

(b) Background of the Technology Generally speaking, a speech synthesis device stores a plurality of words consisting of a set of speech data in a storage circuit such as a ROM in advance, and when the stored word is selected by a word selection signal, the synthesis is started. When a commanding start signal arrives, speech is synthesized based on the speech data that constitutes the selected word. This speech synthesizer operates using a clock signal generated by a built-in oscillation circuit.
If oscillation were to be performed even when voice synthesis was not being performed, power consumption would increase and it would be uneconomical. Normally, power consumption can be reduced by stopping oscillation and starting oscillation when the word selection signal and start signal arrive, but if the word selection signal and start signal are directly connected to the switch, power consumption can be reduced. When using open/close signals,
There is a risk of chattering and malfunction. Furthermore, it is necessary to provide a dedicated prevention circuit to prevent chattering, which has the disadvantage of complicating the circuit.

(C) Disclosure of the Invention The present invention has been made in view of the above-mentioned points, and is made to oscillate by at least an AND signal of one of the word selection signals for selecting a plurality of stored words and a start signal. An oscillation circuit that starts the oscillation and a time constant circuit that generates a signal that is delayed by a predetermined time from the start of oscillation of the oscillation circuit are provided, and the reset of the voice synthesis circuit and the start control circuit is released by the delayed signal of the time constant circuit. This provides a speech synthesis device that eliminates the influence of abnormal oscillation immediately after the oscillation circuit oscillates, and at the same time prevents malfunctions due to chattering contained in the word selection signal or the start signal.

(d) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The word selection circuit 1 receives the applied word selection signal S ₁
~ When one of S _o goes to “H” level, the word corresponding to that signal is memorized.
This specifies the address of ROM2.
The ROM 2 stores a plurality of phrases constituted by a set of voice data, and outputs the voice data constituting the phrase specified by the phrase selection circuit 1 to the voice synthesis circuit 3. The speech synthesis circuit 3 synthesizes speech based on this speech data and outputs the speech from the speaker 4.The speech synthesis circuit 3 is instructed to start synthesis by a signal ST output from the start control circuit 5. . The start control circuit 5 outputs the start control signal ST when at least one of the applied word selection signals S ₁ to _{S o} becomes "H" level and the applied start signal START becomes "H" level. At the same time as outputting, R-SFF8 is set. R-SFF8 is used as a flag indicating that the speech synthesis circuit 3 is in synthesis operation, and is reset by the signal END outputted when the synthesis operation is completed.

The oscillation circuit 6 oscillates at a frequency determined by the connected crystal oscillator 9, for example 400KHz, and each circuit,
In particular, a clock signal, which is the basis of the operation of the speech synthesis circuit 3, is created. This oscillation circuit 6 is an OR gate 1
The start and stop of oscillation is controlled by the output CLC of 0. The OR gate 10 receives the output of the OR gate 11 to which the word selection signals S ₁ to S _o are applied, and the output of the AND gate 12 to which the start signal START is applied, that is, any of the word selection signals S ₁ to _{S o} . A signal to which an AND signal with the start signal START is applied and a signal input from the outside is inverted by the inverter 13
OSCG and the output Q of R-SFF8 are applied. Therefore, when any of the signals applied to the OR gate 10 becomes "H" level, the oscillation circuit 6 starts oscillating.

On the other hand, the time constant circuit 7 outputs the output of the OR gate 10.
It consists of an inverter 14 that inverts CLC, a C-MOS transistor 15 to which the output of the inverter 14 is applied, an inverter 16 and a capacitor 17 to which the output of the C-MOS transistor 15 is applied, and the C-MOS transistor 15 The source of the P-channel MOS transistor is
A resistor 18 is connected between the power supply _VDD . That is, when the signal CLC becomes "H" level and oscillation starts, "L" level is applied to the gate of the C-MOS transistor 15, so the P channel MOS transistor is turned on, and the capacitor 17 and the resistor are turned on. 18 forms a time constant, and the voltage applied to the inverter 16 becomes a voltage that increases according to the time constant. When the threshold voltage of the inverter 16 is reached, the inverter 16
is inverted, its output becomes "L" level, and a signal delayed by a predetermined time after the start of oscillation is obtained. The delay time is somewhat longer than the time from when the oscillation circuit 6 oscillates until it stabilizes, for example, 10ms to 50ms.
It is set to about ms. The output of the inverter 16 is applied to the reset terminal R of the speech synthesis circuit 3 and also to the reset terminal R of the start control circuit 5. Therefore, for a predetermined period of time after the oscillation circuit 6 starts oscillating, the output of the inverter 16 is at the "H" level, so the speech synthesis circuit 3 and the start control circuit 5 are in a reset state and do not operate. Even if chattering occurs in the word selection signals S ₁ -S _o or the start signal START during this period, this signal is ignored.

The signal is used when the oscillation circuit 6 is forced to start operating from the outside or when it is kept in a constant oscillation state. For example, the word selection signal S ₁
When ~S _o and the start signal START are applied by a mechanical switch, chattering is always included, so in this case, the signal is fixed at the "H" level and oscillation is stopped.
If only a chattering signal is applied when the start control circuit 5 is not in the reset state,
This signal outputs the start control signal ST.
Furthermore, since R-SFF8 is set, oscillation is sustained by the output Q, resulting in malfunction.
On the other hand, when the speech synthesizer is controlled by a microcomputer, the word selection signals S ₁ to _{S o} and the start signal START are generated by the output signals of the microcomputer, so that no chattering occurs.
Therefore, in this case, the signal is kept at the "L" level and always oscillates, so that even if the start control circuit 5 is not in the reset state, it will not malfunction. An example of such usage is when a microcomputer successively selects words and phrases and edits the text. Of course, the voice synthesis circuit 3 and the start control circuit 5 are in a reset state for a predetermined period of time after the signal is set to the "L" level, and the abnormal oscillation of the oscillation circuit 6 is absorbed within this period.

Note that the output of the inverter 16 is applied to an AND gate 19 to which the signal OSCG is applied, and the output of the AND gate 19 is applied to a NOR gate 20 to which the output Q of the R-SFF 8 is applied. NOR gate 2
The output of 0 is output as, and this output
BUSY is a signal indicating whether sound synthesis is in progress or abnormal oscillation absorption of the oscillation circuit 6 is in progress.
When the output is at the "L" level, it indicates a state in which the speech synthesizer cannot be operated.

Next, the operation will be explained with reference to FIGS. 2 and 3. FIGS. 2 and 3 are waveform diagrams when the signal is fixed at the "H" level and the word selection signals S ₁ -S _o and the start signal START are applied by switches.

In FIG. 2, if only a chatter occurs in the word selection signals S ₁ to S _o or the start signal START, the output of the AND gate 12 becomes the AND signal of the chattering, and the output of the OR gate 10
CLC becomes "H" level in a pulsed manner. Therefore,
The oscillation circuit 6 oscillates only during the “H” level period,
P channel MOS of C-MOS transistor 15
Although the transistor is turned on, this period is very short, so the terminal voltage of the capacitor 17 does not rise to the threshold voltage of the inverter 16, and the output of the inverter 16 remains at "H" level, and the start control circuit 5 and The speech synthesis circuit 3 is in a reset state. Therefore, the chatter of the word selection signals S ₁ to S _o and the start signal START is not taken into the start control circuit 5, and the oscillation of the oscillation circuit 6 does not continue.

On the other hand, as shown in FIG. 3, word selection signals S ₁ to S _o
And after the start signal START is chattering,
When the level is "H" for a predetermined period of time, the initial chattering is ignored as explained in FIG. 2, but the word selection signals S ₁ to _{S o} and the start signal
When START both become “H” level,
Output of AND gate 12 and output of OR gate 10
Since CLC becomes "H" level, the oscillation circuit 6 starts continuous oscillation. However, immediately after oscillation, the frequency etc. are not stabilized and abnormal oscillation occurs. on the other hand,
Since the signal becomes "L" level, the P channel transistor of the C-MOS transistor 15 is turned on, and a charging current flows from the power supply V _DD to the capacitor 17 via the resistor 18, and the terminal voltage of the capacitor 17, that is, the inverter The input voltage of 16 is
It increases with a time constant determined by capacitor 17 and resistor 18. When the input voltage of the inverter 16 reaches the threshold voltage of the inverter 16, the inverter 16 is inverted and its output changes from the "H" level to the "L" level. As a result, the reset of the voice synthesis circuit 3 and the start control circuit 5 is released. At this time, the start control circuit 5 determines that the word selection signal 5 indicates that at least one of the word selection signals S ₁ to _{S o} is at the "H" level and that the start signal START is at the "H" level. detects that the R-SFF
8 is set state. When the R-SFF 8 is set, its output Q goes to the "H" level, and the oscillation of the oscillation circuit 6 is maintained via the OR gate 10.
At this point, even if the word selection signals S ₁ -S _o or the start signal START go to "L" level, the oscillation of the oscillation circuit 6 is continued, and the oscillation is sufficiently stable. Then, the speech synthesis circuit 3 to which the start control signal ST is applied synthesizes speech based on the speech data in the ROM 2 addressed by the word selection circuit 1, and outputs the synthesized speech from the speaker 4.

By the above operation, chattering and abnormal oscillation of the oscillation circuit 6 are absorbed. Furthermore, when the speech synthesis circuit 3 finishes pronouncing the selected word,
The speech synthesis circuit 3 sets the end signal END to the "H" level and resets the R-SFF8. As a result, the output Q goes to the "L" level, so the output CLC of the OR gate 10 goes to the "L" level, and the oscillation of the oscillation circuit 6 stops. Therefore, since oscillation is stopped except during vocalization, power consumption can be saved.

(e) Effects As described above, according to the present invention, the oscillation circuit and the time constant circuit are operated by the AND signal of at least one word selection signal and the start signal, and the start control is performed by the output of the time constant circuit. By canceling the reset of the circuit and the voice synthesis circuit, it is possible to simultaneously eliminate the effects of malfunction due to chattering and abnormal oscillation immediately after oscillation, and there is no need to provide a dedicated anti-chattering circuit. This is advantageous when

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams showing the operation of the embodiment shown in FIG. 1... word selection circuit, 2... ROM, 3... voice synthesis circuit, 4... speaker, 5... start control circuit, 6... oscillation circuit, 7... time constant circuit.

Claims (1)

[Scope of Claims] 1. A speech synthesis circuit that utters a word selected by a plurality of word selection signals generated by opening and closing a plurality of switches based on audio data; The generated start signal is applied, and the operation is started by a start control circuit that controls the start of synthesis of the speech synthesis circuit, and an AND signal of at least one of the plurality of word selection signals and the start signal. an oscillation circuit that is controlled and creates a clock signal that is the basis of the operation of each circuit; and an oscillation circuit that outputs a signal that is delayed by a predetermined time from the start of oscillation of the oscillation circuit, and that outputs a signal delayed by a predetermined time from the start of oscillation of the oscillation circuit. a time constant circuit for canceling the reset of the oscillation circuit, and removing the effects of malfunction due to chattering contained in the word selection signal and start signal caused by opening and closing of the switch and abnormal oscillation immediately after oscillation of the oscillation circuit. A speech synthesis device featuring: