JPH0332868U - - Google Patents
Info
- Publication number
- JPH0332868U JPH0332868U JP9316789U JP9316789U JPH0332868U JP H0332868 U JPH0332868 U JP H0332868U JP 9316789 U JP9316789 U JP 9316789U JP 9316789 U JP9316789 U JP 9316789U JP H0332868 U JPH0332868 U JP H0332868U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- amplitude
- delay circuit
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案による輪郭強調回路の一実施例
を示すブロツク図、第２図はその各部信号波形図
、第３図は従来回路を示すブロツク図、第４図は
その各部信号波形図である。
１０……水平輪郭強調回路、１１，１２……サ
ンプリング周期の遅延回路、１３，１４，２３，
２４……減算器、１５，１７，２５，２７……ア
ツテネータ回路、１６，２６……加算器、２０…
…垂直輪郭強調回路、２１，２２……１水平走査
期間の遅延回路。
Fig. 1 is a block diagram showing an embodiment of the edge enhancement circuit according to the present invention, Fig. 2 is a signal waveform diagram of each part thereof, Fig. 3 is a block diagram showing a conventional circuit, and Fig. 4 is a diagram of signal waveforms of each part thereof. be. 10...Horizontal contour enhancement circuit, 11, 12...Sampling period delay circuit, 13, 14, 23,
24... Subtractor, 15, 17, 25, 27... Attenuator circuit, 16, 26... Adder, 20...
... Vertical contour enhancement circuit, 21, 22 ... Delay circuit for one horizontal scanning period.
Claims (1)
せる縦続接続された第１及び第２の遅延回路と、 上記第１の遅延回路を介したビデオ信号から上
記入力ビデオ信号を減算する第１の減算器と、 この減算信号の振幅を縮小させる第１の振幅縮
小回路と、 上記第２の遅延回路を介したビデオ信号から上
記第１の遅延回路を介したビデオ信号を減算する
第２の減算器と、 この減算信号の振幅を縮小させる第２の振幅縮
小回路と、 上記第１及び第２の振幅縮小回路の出力ビデオ
信号と、上記第１の遅延回路を介したビデオ信号
とを加算する加算器とを備えた輪郭強調回路。[Claims for Utility Model Registration] First and second delay circuits connected in cascade, each delaying an input video signal by a predetermined time, and subtracting the input video signal from the video signal passed through the first delay circuit. a first subtracter for reducing the amplitude of the subtraction signal; a first amplitude reduction circuit for reducing the amplitude of the subtraction signal; and subtracting the video signal passed through the first delay circuit from the video signal passed through the second delay circuit. a second subtracter; a second amplitude reduction circuit that reduces the amplitude of the subtracted signal; an output video signal of the first and second amplitude reduction circuits; and a video signal that passes through the first delay circuit. and an adder for adding the.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9316789U JPH0332868U (en) | 1989-08-08 | 1989-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9316789U JPH0332868U (en) | 1989-08-08 | 1989-08-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332868U true JPH0332868U (en) | 1991-03-29 |
Family
ID=31642561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9316789U Pending JPH0332868U (en) | 1989-08-08 | 1989-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332868U (en) |
-
1989
- 1989-08-08 JP JP9316789U patent/JPH0332868U/ja active Pending
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